Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T12,T23
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T12,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T12,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T12,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T23
1	0	Covered	T12,T23,T41
1	1	Covered	T4,T12,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T12,T23
0	1	Covered	T4,T23,T49
1	0	Covered	T12,T23,T44

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T41,T42,T43
0	1	Covered	T41,T42,T43
1	0	Covered	T75,T240

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T41,T42,T43
1	-	Covered	T41,T42,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T12,T23
DetectSt	168	Covered	T4,T12,T23
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T41,T42,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T12,T23
DebounceSt->IdleSt	163	Covered	T87,T241,T70
DetectSt->IdleSt	186	Covered	T4,T12,T23
DetectSt->StableSt	191	Covered	T41,T42,T43
IdleSt->DebounceSt	148	Covered	T4,T12,T23
StableSt->IdleSt	206	Covered	T41,T42,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T12,T23
0	1	Covered	T4,T12,T23
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T23
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T12,T23
IdleSt	0	-	-	-	-	-	-	Covered	T4,T12,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T12,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T87,T241,T70
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T12,T23
DetectSt	-	-	-	-	1	-	-	Covered	T4,T12,T23
DetectSt	-	-	-	-	0	1	-	Covered	T41,T42,T43
DetectSt	-	-	-	-	0	0	-	Covered	T4,T12,T23
StableSt	-	-	-	-	-	-	1	Covered	T41,T42,T43
StableSt	-	-	-	-	-	-	0	Covered	T41,T42,T43
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	2830	0	0
CntIncr_A	8886315	92046	0	0
CntNoWrap_A	8886315	8211270	0	0
DetectStDropOut_A	8886315	386	0	0
DetectedOut_A	8886315	59772	0	0
DetectedPulseOut_A	8886315	816	0	0
DisabledIdleSt_A	8886315	7767888	0	0
DisabledNoDetection_A	8886315	7770128	0	0
EnterDebounceSt_A	8886315	1429	0	0
EnterDetectSt_A	8886315	1401	0	0
EnterStableSt_A	8886315	816	0	0
PulseIsPulse_A	8886315	816	0	0
StayInStableSt	8886315	58856	0	0
gen_high_event_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_high_level_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	701	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	2830	0	0
T3	12717	0	0	0
T4	4882	48	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T12	7140	44	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	20	0	0
T41	0	42	0	0
T42	0	22	0	0
T43	0	12	0	0
T44	0	34	0	0
T49	0	32	0	0
T52	79762	0	0	0
T65	0	28	0	0
T66	0	54	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	92046	0	0
T3	12717	0	0	0
T4	4882	1053	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T12	7140	1318	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	794	0	0
T41	0	756	0	0
T42	0	517	0	0
T43	0	384	0	0
T44	0	1165	0	0
T49	0	902	0	0
T52	79762	0	0	0
T65	0	798	0	0
T66	0	1538	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8211270	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	4433	0	0
T5	13605	13178	0	0
T6	17688	8412	0	0
T12	7140	6695	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	386	0	0
T3	12717	0	0	0
T4	4882	24	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	2	0	0
T49	0	16	0	0
T52	79762	0	0	0
T66	0	27	0	0
T86	0	8	0	0
T87	0	21	0	0
T91	0	18	0	0
T92	0	5	0	0
T93	0	5	0	0
T95	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	59772	0	0
T31	590	0	0	0
T41	26234	1809	0	0
T42	0	1077	0	0
T43	0	344	0	0
T58	494	0	0	0
T59	493	0	0	0
T64	1764	0	0	0
T65	0	482	0	0
T81	32839	0	0	0
T100	0	84	0	0
T103	0	15	0	0
T104	905	0	0	0
T105	586	0	0	0
T106	1646	0	0	0
T107	503	0	0	0
T179	0	790	0	0
T242	0	286	0	0
T243	0	361	0	0
T244	0	1159	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	816	0	0
T31	590	0	0	0
T41	26234	21	0	0
T42	0	11	0	0
T43	0	6	0	0
T58	494	0	0	0
T59	493	0	0	0
T64	1764	0	0	0
T65	0	14	0	0
T81	32839	0	0	0
T100	0	1	0	0
T103	0	6	0	0
T104	905	0	0	0
T105	586	0	0	0
T106	1646	0	0	0
T107	503	0	0	0
T179	0	12	0	0
T242	0	7	0	0
T243	0	5	0	0
T244	0	14	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7767888	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	2015	0	0
T5	13605	13178	0	0
T6	17688	8412	0	0
T12	7140	3593	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7770128	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	2015	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	3593	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	1429	0	0
T3	12717	0	0	0
T4	4882	24	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T12	7140	22	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	10	0	0
T41	0	21	0	0
T42	0	11	0	0
T43	0	6	0	0
T44	0	17	0	0
T49	0	16	0	0
T52	79762	0	0	0
T65	0	14	0	0
T66	0	27	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	1401	0	0
T3	12717	0	0	0
T4	4882	24	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T12	7140	22	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	10	0	0
T41	0	21	0	0
T42	0	11	0	0
T43	0	6	0	0
T44	0	17	0	0
T49	0	16	0	0
T52	79762	0	0	0
T65	0	14	0	0
T66	0	27	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	816	0	0
T31	590	0	0	0
T41	26234	21	0	0
T42	0	11	0	0
T43	0	6	0	0
T58	494	0	0	0
T59	493	0	0	0
T64	1764	0	0	0
T65	0	14	0	0
T81	32839	0	0	0
T100	0	1	0	0
T103	0	6	0	0
T104	905	0	0	0
T105	586	0	0	0
T106	1646	0	0	0
T107	503	0	0	0
T179	0	12	0	0
T242	0	7	0	0
T243	0	5	0	0
T244	0	14	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	816	0	0
T31	590	0	0	0
T41	26234	21	0	0
T42	0	11	0	0
T43	0	6	0	0
T58	494	0	0	0
T59	493	0	0	0
T64	1764	0	0	0
T65	0	14	0	0
T81	32839	0	0	0
T100	0	1	0	0
T103	0	6	0	0
T104	905	0	0	0
T105	586	0	0	0
T106	1646	0	0	0
T107	503	0	0	0
T179	0	12	0	0
T242	0	7	0	0
T243	0	5	0	0
T244	0	14	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	58856	0	0
T31	590	0	0	0
T41	26234	1781	0	0
T42	0	1061	0	0
T43	0	338	0	0
T58	494	0	0	0
T59	493	0	0	0
T64	1764	0	0	0
T65	0	468	0	0
T81	32839	0	0	0
T100	0	82	0	0
T103	0	9	0	0
T104	905	0	0	0
T105	586	0	0	0
T106	1646	0	0	0
T107	503	0	0	0
T179	0	778	0	0
T242	0	278	0	0
T243	0	355	0	0
T244	0	1142	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	701	0	0
T31	590	0	0	0
T41	26234	14	0	0
T42	0	6	0	0
T43	0	6	0	0
T58	494	0	0	0
T59	493	0	0	0
T64	1764	0	0	0
T65	0	14	0	0
T81	32839	0	0	0
T103	0	6	0	0
T104	905	0	0	0
T105	586	0	0	0
T106	1646	0	0	0
T107	503	0	0	0
T179	0	12	0	0
T242	0	6	0	0
T243	0	4	0	0
T244	0	11	0	0
T245	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T12,T3
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T5,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T3,T5,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T5,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T4,T12,T3
1	1	Covered	T3,T5,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T6
0	1	Covered	T5,T28,T39
1	0	Covered	T70,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T7,T26
1	0	Covered	T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T7
1	-	Covered	T3,T7,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T5,T6
DetectSt	168	Covered	T3,T5,T6
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T3,T6,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T5,T6
DebounceSt->IdleSt	163	Covered	T28,T246,T102
DetectSt->IdleSt	186	Covered	T5,T28,T39
DetectSt->StableSt	191	Covered	T3,T6,T7
IdleSt->DebounceSt	148	Covered	T3,T5,T6
StableSt->IdleSt	206	Covered	T3,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T5,T6
0	1	Covered	T3,T5,T6
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T5,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T5,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T246,T102
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T5,T6
DetectSt	-	-	-	-	1	-	-	Covered	T5,T28,T39
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T7
DetectSt	-	-	-	-	0	0	-	Covered	T3,T5,T6
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T26
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	972	0	0
CntIncr_A	8886315	49678	0	0
CntNoWrap_A	8886315	8213128	0	0
DetectStDropOut_A	8886315	66	0	0
DetectedOut_A	8886315	13899	0	0
DetectedPulseOut_A	8886315	373	0	0
DisabledIdleSt_A	8886315	7860655	0	0
DisabledNoDetection_A	8886315	7862348	0	0
EnterDebounceSt_A	8886315	530	0	0
EnterDetectSt_A	8886315	443	0	0
EnterStableSt_A	8886315	373	0	0
PulseIsPulse_A	8886315	373	0	0
StayInStableSt	8886315	13512	0	0
gen_high_level_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	358	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	972	0	0
T3	12717	4	0	0
T5	13605	4	0	0
T6	17688	2	0	0
T7	17691	4	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T26	0	18	0	0
T27	0	2	0	0
T28	0	12	0	0
T41	0	14	0	0
T48	0	2	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	49678	0	0
T3	12717	50	0	0
T5	13605	252	0	0
T6	17688	128	0	0
T7	17691	358	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T26	0	945	0	0
T27	0	25	0	0
T28	0	514	0	0
T41	0	364	0	0
T48	0	109	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	152	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8213128	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5870	0	0
T4	4882	4481	0	0
T5	13605	13174	0	0
T6	17688	8410	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	66	0	0
T5	13605	2	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T22	610	0	0	0
T28	0	5	0	0
T39	0	2	0	0
T52	79762	0	0	0
T53	423	0	0	0
T76	0	5	0	0
T89	0	6	0	0
T90	0	3	0	0
T94	0	3	0	0
T96	0	3	0	0
T97	0	3	0	0
T98	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	13899	0	0
T3	12717	6	0	0
T5	13605	0	0	0
T6	17688	31	0	0
T7	17691	35	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T26	0	397	0	0
T27	0	3	0	0
T41	0	497	0	0
T42	0	172	0	0
T48	0	85	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	125	0	0
T102	0	82	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	373	0	0
T3	12717	2	0	0
T5	13605	0	0	0
T6	17688	1	0	0
T7	17691	2	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T26	0	9	0	0
T27	0	1	0	0
T41	0	7	0	0
T42	0	3	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	2	0	0
T102	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7860655	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5338	0	0
T4	4882	4481	0	0
T5	13605	10073	0	0
T6	17688	7427	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7862348	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5360	0	0
T4	4882	4482	0	0
T5	13605	10073	0	0
T6	17688	7452	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	530	0	0
T3	12717	2	0	0
T5	13605	2	0	0
T6	17688	1	0	0
T7	17691	2	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T26	0	9	0	0
T27	0	1	0	0
T28	0	7	0	0
T41	0	7	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	443	0	0
T3	12717	2	0	0
T5	13605	2	0	0
T6	17688	1	0	0
T7	17691	2	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T26	0	9	0	0
T27	0	1	0	0
T28	0	5	0	0
T41	0	7	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	373	0	0
T3	12717	2	0	0
T5	13605	0	0	0
T6	17688	1	0	0
T7	17691	2	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T26	0	9	0	0
T27	0	1	0	0
T41	0	7	0	0
T42	0	3	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	2	0	0
T102	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	373	0	0
T3	12717	2	0	0
T5	13605	0	0	0
T6	17688	1	0	0
T7	17691	2	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T26	0	9	0	0
T27	0	1	0	0
T41	0	7	0	0
T42	0	3	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	2	0	0
T102	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	13512	0	0
T3	12717	4	0	0
T5	13605	0	0	0
T6	17688	29	0	0
T7	17691	33	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T26	0	388	0	0
T27	0	2	0	0
T41	0	490	0	0
T42	0	166	0	0
T48	0	84	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	123	0	0
T102	0	73	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	358	0	0
T3	12717	2	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	2	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T26	0	9	0	0
T27	0	1	0	0
T41	0	7	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	2	0	0
T102	0	9	0	0
T109	0	7	0	0
T110	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T12,T23
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T12,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T12,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T12,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T23
1	0	Covered	T12,T23,T41
1	1	Covered	T4,T12,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T12,T23
0	1	Covered	T4,T49,T43
1	0	Covered	T12,T41,T43

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T42,T44
0	1	Covered	T23,T42,T44
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T23,T42,T44
1	-	Covered	T23,T42,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T12,T23
DetectSt	168	Covered	T4,T12,T23
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T23,T42,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T12,T23
DebounceSt->IdleSt	163	Covered	T87,T241,T70
DetectSt->IdleSt	186	Covered	T4,T12,T41
DetectSt->StableSt	191	Covered	T23,T42,T44
IdleSt->DebounceSt	148	Covered	T4,T12,T23
StableSt->IdleSt	206	Covered	T23,T42,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T12,T23
0	1	Covered	T4,T12,T23
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T23
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T12,T23
IdleSt	0	-	-	-	-	-	-	Covered	T4,T12,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T12,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T87,T241,T70
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T12,T23
DetectSt	-	-	-	-	1	-	-	Covered	T4,T12,T41
DetectSt	-	-	-	-	0	1	-	Covered	T23,T42,T44
DetectSt	-	-	-	-	0	0	-	Covered	T4,T12,T23
StableSt	-	-	-	-	-	-	1	Covered	T23,T42,T44
StableSt	-	-	-	-	-	-	0	Covered	T23,T42,T44
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	3018	0	0
CntIncr_A	8886315	98465	0	0
CntNoWrap_A	8886315	8211082	0	0
DetectStDropOut_A	8886315	337	0	0
DetectedOut_A	8886315	85060	0	0
DetectedPulseOut_A	8886315	995	0	0
DisabledIdleSt_A	8886315	7748961	0	0
DisabledNoDetection_A	8886315	7751190	0	0
EnterDebounceSt_A	8886315	1526	0	0
EnterDetectSt_A	8886315	1492	0	0
EnterStableSt_A	8886315	995	0	0
PulseIsPulse_A	8886315	995	0	0
StayInStableSt	8886315	83953	0	0
gen_high_event_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_high_level_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	883	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	3018	0	0
T3	12717	0	0	0
T4	4882	40	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T12	7140	6	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	32	0	0
T41	0	12	0	0
T42	0	26	0	0
T43	0	64	0	0
T44	0	52	0	0
T49	0	6	0	0
T52	79762	0	0	0
T65	0	52	0	0
T66	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	98465	0	0
T3	12717	0	0	0
T4	4882	882	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T12	7140	179	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	800	0	0
T41	0	346	0	0
T42	0	494	0	0
T43	0	3826	0	0
T44	0	1612	0	0
T49	0	169	0	0
T52	79762	0	0	0
T65	0	1794	0	0
T66	0	394	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8211082	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	4441	0	0
T5	13605	13178	0	0
T6	17688	8412	0	0
T12	7140	6733	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	337	0	0
T3	12717	0	0	0
T4	4882	20	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T43	0	19	0	0
T49	0	3	0	0
T52	79762	0	0	0
T66	0	7	0	0
T86	0	23	0	0
T87	0	15	0	0
T91	0	2	0	0
T92	0	5	0	0
T93	0	16	0	0
T247	0	23	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	85060	0	0
T23	7818	1326	0	0
T27	2312	0	0	0
T30	505	0	0	0
T41	26234	0	0	0
T42	0	1696	0	0
T44	0	1397	0	0
T58	494	0	0	0
T63	503	0	0	0
T64	1764	0	0	0
T65	0	1925	0	0
T103	0	2646	0	0
T104	905	0	0	0
T105	586	0	0	0
T106	1646	0	0	0
T179	0	1064	0	0
T242	0	163	0	0
T243	0	519	0	0
T244	0	1389	0	0
T245	0	35	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	995	0	0
T23	7818	16	0	0
T27	2312	0	0	0
T30	505	0	0	0
T41	26234	0	0	0
T42	0	13	0	0
T44	0	26	0	0
T58	494	0	0	0
T63	503	0	0	0
T64	1764	0	0	0
T65	0	26	0	0
T103	0	29	0	0
T104	905	0	0	0
T105	586	0	0	0
T106	1646	0	0	0
T179	0	10	0	0
T242	0	7	0	0
T243	0	6	0	0
T244	0	15	0	0
T245	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7748961	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	2016	0	0
T5	13605	13178	0	0
T6	17688	8412	0	0
T12	7140	3593	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7751190	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	2016	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	3593	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	1526	0	0
T3	12717	0	0	0
T4	4882	20	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T12	7140	3	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	16	0	0
T41	0	6	0	0
T42	0	13	0	0
T43	0	32	0	0
T44	0	26	0	0
T49	0	3	0	0
T52	79762	0	0	0
T65	0	26	0	0
T66	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	1492	0	0
T3	12717	0	0	0
T4	4882	20	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T12	7140	3	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	16	0	0
T41	0	6	0	0
T42	0	13	0	0
T43	0	32	0	0
T44	0	26	0	0
T49	0	3	0	0
T52	79762	0	0	0
T65	0	26	0	0
T66	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	995	0	0
T23	7818	16	0	0
T27	2312	0	0	0
T30	505	0	0	0
T41	26234	0	0	0
T42	0	13	0	0
T44	0	26	0	0
T58	494	0	0	0
T63	503	0	0	0
T64	1764	0	0	0
T65	0	26	0	0
T103	0	29	0	0
T104	905	0	0	0
T105	586	0	0	0
T106	1646	0	0	0
T179	0	10	0	0
T242	0	7	0	0
T243	0	6	0	0
T244	0	15	0	0
T245	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	995	0	0
T23	7818	16	0	0
T27	2312	0	0	0
T30	505	0	0	0
T41	26234	0	0	0
T42	0	13	0	0
T44	0	26	0	0
T58	494	0	0	0
T63	503	0	0	0
T64	1764	0	0	0
T65	0	26	0	0
T103	0	29	0	0
T104	905	0	0	0
T105	586	0	0	0
T106	1646	0	0	0
T179	0	10	0	0
T242	0	7	0	0
T243	0	6	0	0
T244	0	15	0	0
T245	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	83953	0	0
T23	7818	1310	0	0
T27	2312	0	0	0
T30	505	0	0	0
T41	26234	0	0	0
T42	0	1679	0	0
T44	0	1371	0	0
T58	494	0	0	0
T63	503	0	0	0
T64	1764	0	0	0
T65	0	1899	0	0
T103	0	2615	0	0
T104	905	0	0	0
T105	586	0	0	0
T106	1646	0	0	0
T179	0	1054	0	0
T242	0	156	0	0
T243	0	512	0	0
T244	0	1372	0	0
T245	0	25	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	883	0	0
T23	7818	16	0	0
T27	2312	0	0	0
T30	505	0	0	0
T41	26234	0	0	0
T42	0	9	0	0
T44	0	26	0	0
T58	494	0	0	0
T63	503	0	0	0
T64	1764	0	0	0
T65	0	26	0	0
T103	0	27	0	0
T104	905	0	0	0
T105	586	0	0	0
T106	1646	0	0	0
T179	0	10	0	0
T242	0	7	0	0
T243	0	5	0	0
T244	0	13	0	0
T245	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T12,T3
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T3,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T4,T12,T3
1	1	Covered	T3,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T88,T248,T249
1	0	Covered	T70,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T7,T11
1	0	Covered	T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T7
1	-	Covered	T3,T7,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T7
DetectSt	168	Covered	T3,T6,T7
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T3,T6,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T7
DebounceSt->IdleSt	163	Covered	T6,T28,T81
DetectSt->IdleSt	186	Covered	T88,T248,T249
DetectSt->StableSt	191	Covered	T3,T6,T7
IdleSt->DebounceSt	148	Covered	T3,T6,T7
StableSt->IdleSt	206	Covered	T3,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T28,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T88,T248,T249
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T7
DetectSt	-	-	-	-	0	0	-	Covered	T3,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	898	0	0
CntIncr_A	8886315	47503	0	0
CntNoWrap_A	8886315	8213202	0	0
DetectStDropOut_A	8886315	41	0	0
DetectedOut_A	8886315	17682	0	0
DetectedPulseOut_A	8886315	376	0	0
DisabledIdleSt_A	8886315	7840646	0	0
DisabledNoDetection_A	8886315	7842400	0	0
EnterDebounceSt_A	8886315	477	0	0
EnterDetectSt_A	8886315	421	0	0
EnterStableSt_A	8886315	376	0	0
PulseIsPulse_A	8886315	376	0	0
StayInStableSt	8886315	17259	0	0
gen_high_level_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	328	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	898	0	0
T3	12717	2	0	0
T5	13605	0	0	0
T6	17688	3	0	0
T7	17691	4	0	0
T11	0	2	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	2	0	0
T26	0	10	0	0
T28	0	17	0	0
T42	0	7	0	0
T48	0	3	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	47503	0	0
T3	12717	105	0	0
T5	13605	0	0	0
T6	17688	212	0	0
T7	17691	256	0	0
T11	0	128	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	66	0	0
T26	0	715	0	0
T28	0	674	0	0
T42	0	150	0	0
T48	0	190	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	796	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8213202	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5872	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	8409	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	41	0	0
T88	4064	4	0	0
T89	7616	0	0	0
T90	14962	0	0	0
T98	0	2	0	0
T99	497	0	0	0
T100	510	0	0	0
T101	525	0	0	0
T149	0	5	0	0
T155	0	1	0	0
T248	0	1	0	0
T249	0	7	0	0
T250	0	5	0	0
T251	0	1	0	0
T252	0	12	0	0
T253	0	1	0	0
T254	403	0	0	0
T255	407	0	0	0
T256	2833	0	0	0
T257	440	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	17682	0	0
T3	12717	47	0	0
T5	13605	0	0	0
T6	17688	44	0	0
T7	17691	139	0	0
T11	0	12	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	47	0	0
T26	0	28	0	0
T28	0	85	0	0
T42	0	147	0	0
T48	0	77	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	685	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	376	0	0
T3	12717	1	0	0
T5	13605	0	0	0
T6	17688	1	0	0
T7	17691	2	0	0
T11	0	1	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	1	0	0
T26	0	5	0	0
T28	0	8	0	0
T42	0	3	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7840646	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5500	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	7427	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7842400	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5524	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	7452	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	477	0	0
T3	12717	1	0	0
T5	13605	0	0	0
T6	17688	2	0	0
T7	17691	2	0	0
T11	0	1	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	1	0	0
T26	0	5	0	0
T28	0	9	0	0
T42	0	4	0	0
T48	0	2	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	421	0	0
T3	12717	1	0	0
T5	13605	0	0	0
T6	17688	1	0	0
T7	17691	2	0	0
T11	0	1	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	1	0	0
T26	0	5	0	0
T28	0	8	0	0
T42	0	3	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	376	0	0
T3	12717	1	0	0
T5	13605	0	0	0
T6	17688	1	0	0
T7	17691	2	0	0
T11	0	1	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	1	0	0
T26	0	5	0	0
T28	0	8	0	0
T42	0	3	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	376	0	0
T3	12717	1	0	0
T5	13605	0	0	0
T6	17688	1	0	0
T7	17691	2	0	0
T11	0	1	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	1	0	0
T26	0	5	0	0
T28	0	8	0	0
T42	0	3	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	17259	0	0
T3	12717	46	0	0
T5	13605	0	0	0
T6	17688	42	0	0
T7	17691	137	0	0
T11	0	11	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	46	0	0
T26	0	23	0	0
T28	0	77	0	0
T42	0	141	0	0
T48	0	76	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	675	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	328	0	0
T3	12717	1	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	2	0	0
T11	0	1	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	1	0	0
T26	0	5	0	0
T28	0	8	0	0
T44	0	5	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	10	0	0
T258	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T12,T23
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T12,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T12,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T12,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T23
1	0	Covered	T23,T41,T42
1	1	Covered	T4,T12,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T12,T23
0	1	Covered	T4,T42,T49
1	0	Covered	T42,T103,T179

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T23,T41
0	1	Covered	T12,T23,T41
1	0	Covered	T74,T259,T71

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T23,T41
1	-	Covered	T12,T23,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T12,T23
DetectSt	168	Covered	T4,T12,T23
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T12,T23,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T12,T23
DebounceSt->IdleSt	163	Covered	T87,T241,T70
DetectSt->IdleSt	186	Covered	T4,T42,T49
DetectSt->StableSt	191	Covered	T12,T23,T41
IdleSt->DebounceSt	148	Covered	T4,T12,T23
StableSt->IdleSt	206	Covered	T12,T23,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T12,T23
0	1	Covered	T4,T12,T23
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T23
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T12,T23
IdleSt	0	-	-	-	-	-	-	Covered	T4,T12,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T12,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T87,T241,T70
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T12,T23
DetectSt	-	-	-	-	1	-	-	Covered	T4,T42,T49
DetectSt	-	-	-	-	0	1	-	Covered	T12,T23,T41
DetectSt	-	-	-	-	0	0	-	Covered	T4,T12,T23
StableSt	-	-	-	-	-	-	1	Covered	T12,T23,T41
StableSt	-	-	-	-	-	-	0	Covered	T12,T23,T41
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	3192	0	0
CntIncr_A	8886315	104276	0	0
CntNoWrap_A	8886315	8210908	0	0
DetectStDropOut_A	8886315	382	0	0
DetectedOut_A	8886315	87137	0	0
DetectedPulseOut_A	8886315	1042	0	0
DisabledIdleSt_A	8886315	7748123	0	0
DisabledNoDetection_A	8886315	7750357	0	0
EnterDebounceSt_A	8886315	1605	0	0
EnterDetectSt_A	8886315	1587	0	0
EnterStableSt_A	8886315	1042	0	0
PulseIsPulse_A	8886315	1042	0	0
StayInStableSt	8886315	85990	0	0
gen_high_event_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_high_level_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	921	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	3192	0	0
T3	12717	0	0	0
T4	4882	48	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T12	7140	44	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	16	0	0
T41	0	36	0	0
T42	0	24	0	0
T43	0	28	0	0
T44	0	58	0	0
T49	0	30	0	0
T52	79762	0	0	0
T65	0	14	0	0
T66	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	104276	0	0
T3	12717	0	0	0
T4	4882	1053	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T12	7140	1012	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	408	0	0
T41	0	720	0	0
T42	0	734	0	0
T43	0	868	0	0
T44	0	1885	0	0
T49	0	849	0	0
T52	79762	0	0	0
T65	0	406	0	0
T66	0	394	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8210908	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	4433	0	0
T5	13605	13178	0	0
T6	17688	8412	0	0
T12	7140	6695	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	382	0	0
T3	12717	0	0	0
T4	4882	24	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T42	0	5	0	0
T49	0	15	0	0
T52	79762	0	0	0
T66	0	7	0	0
T86	0	23	0	0
T87	0	3	0	0
T91	0	24	0	0
T92	0	3	0	0
T103	0	7	0	0
T179	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	87137	0	0
T3	12717	0	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T12	7140	1853	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	1060	0	0
T41	0	2282	0	0
T43	0	2470	0	0
T44	0	173	0	0
T52	79762	0	0	0
T65	0	235	0	0
T242	0	116	0	0
T243	0	3528	0	0
T244	0	1071	0	0
T260	0	464	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	1042	0	0
T3	12717	0	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T12	7140	22	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	8	0	0
T41	0	18	0	0
T43	0	14	0	0
T44	0	29	0	0
T52	79762	0	0	0
T65	0	7	0	0
T242	0	5	0	0
T243	0	24	0	0
T244	0	13	0	0
T260	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7748123	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	2016	0	0
T5	13605	13178	0	0
T6	17688	8412	0	0
T12	7140	2015	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7750357	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	2016	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	2015	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	1605	0	0
T3	12717	0	0	0
T4	4882	24	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T12	7140	22	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	8	0	0
T41	0	18	0	0
T42	0	12	0	0
T43	0	14	0	0
T44	0	29	0	0
T49	0	15	0	0
T52	79762	0	0	0
T65	0	7	0	0
T66	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	1587	0	0
T3	12717	0	0	0
T4	4882	24	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T12	7140	22	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	8	0	0
T41	0	18	0	0
T42	0	12	0	0
T43	0	14	0	0
T44	0	29	0	0
T49	0	15	0	0
T52	79762	0	0	0
T65	0	7	0	0
T66	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	1042	0	0
T3	12717	0	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T12	7140	22	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	8	0	0
T41	0	18	0	0
T43	0	14	0	0
T44	0	29	0	0
T52	79762	0	0	0
T65	0	7	0	0
T242	0	5	0	0
T243	0	24	0	0
T244	0	13	0	0
T260	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	1042	0	0
T3	12717	0	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T12	7140	22	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	8	0	0
T41	0	18	0	0
T43	0	14	0	0
T44	0	29	0	0
T52	79762	0	0	0
T65	0	7	0	0
T242	0	5	0	0
T243	0	24	0	0
T244	0	13	0	0
T260	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	85990	0	0
T3	12717	0	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T12	7140	1831	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	1052	0	0
T41	0	2258	0	0
T43	0	2455	0	0
T44	0	144	0	0
T52	79762	0	0	0
T65	0	228	0	0
T242	0	111	0	0
T243	0	3499	0	0
T244	0	1055	0	0
T260	0	451	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	921	0	0
T3	12717	0	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T12	7140	22	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	8	0	0
T41	0	12	0	0
T43	0	13	0	0
T44	0	29	0	0
T52	79762	0	0	0
T65	0	7	0	0
T242	0	5	0	0
T243	0	19	0	0
T244	0	10	0	0
T260	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T12,T3
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T7,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T5,T7,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T7,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T3,T5
1	0	Covered	T4,T12,T3
1	1	Covered	T5,T7,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T26
0	1	Covered	T26,T88,T76
1	0	Covered	T70,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T23
0	1	Covered	T5,T7,T23
1	0	Covered	T71

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T7,T23
1	-	Covered	T5,T7,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T7,T11
DetectSt	168	Covered	T5,T7,T26
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T5,T7,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T7,T26
DebounceSt->IdleSt	163	Covered	T5,T11,T41
DetectSt->IdleSt	186	Covered	T26,T88,T76
DetectSt->StableSt	191	Covered	T5,T7,T23
IdleSt->DebounceSt	148	Covered	T5,T7,T11
StableSt->IdleSt	206	Covered	T5,T7,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T7,T11
0	1	Covered	T5,T7,T11
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T26
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T7,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T7,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T5,T11,T41
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T7,T11
DetectSt	-	-	-	-	1	-	-	Covered	T26,T88,T76
DetectSt	-	-	-	-	0	1	-	Covered	T5,T7,T23
DetectSt	-	-	-	-	0	0	-	Covered	T5,T7,T26
StableSt	-	-	-	-	-	-	1	Covered	T5,T7,T23
StableSt	-	-	-	-	-	-	0	Covered	T5,T7,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	890	0	0
CntIncr_A	8886315	46473	0	0
CntNoWrap_A	8886315	8213210	0	0
DetectStDropOut_A	8886315	35	0	0
DetectedOut_A	8886315	15810	0	0
DetectedPulseOut_A	8886315	377	0	0
DisabledIdleSt_A	8886315	7846536	0	0
DisabledNoDetection_A	8886315	7848316	0	0
EnterDebounceSt_A	8886315	475	0	0
EnterDetectSt_A	8886315	415	0	0
EnterStableSt_A	8886315	377	0	0
PulseIsPulse_A	8886315	377	0	0
StayInStableSt	8886315	15401	0	0
gen_high_level_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	342	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	890	0	0
T5	13605	9	0	0
T6	17688	0	0	0
T7	17691	8	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T11	0	1	0	0
T20	503	0	0	0
T22	610	0	0	0
T23	0	2	0	0
T26	0	4	0	0
T41	0	7	0	0
T43	0	2	0	0
T48	0	3	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	4	0	0
T258	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	46473	0	0
T5	13605	477	0	0
T6	17688	0	0	0
T7	17691	468	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T11	0	32	0	0
T20	503	0	0	0
T22	610	0	0	0
T23	0	76	0	0
T26	0	296	0	0
T41	0	139	0	0
T43	0	84	0	0
T48	0	228	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	260	0	0
T258	0	357	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8213210	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	4481	0	0
T5	13605	13169	0	0
T6	17688	8412	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	35	0	0
T23	7818	0	0	0
T26	16346	2	0	0
T27	2312	0	0	0
T30	505	0	0	0
T41	26234	0	0	0
T47	795	0	0	0
T63	503	0	0	0
T76	0	6	0	0
T88	0	2	0	0
T104	905	0	0	0
T146	696	0	0	0
T147	402	0	0	0
T261	0	3	0	0
T262	0	1	0	0
T263	0	1	0	0
T264	0	8	0	0
T265	0	3	0	0
T266	0	3	0	0
T267	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	15810	0	0
T5	13605	115	0	0
T6	17688	0	0	0
T7	17691	320	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T22	610	0	0	0
T23	0	37	0	0
T41	0	254	0	0
T43	0	61	0	0
T48	0	38	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	16	0	0
T102	0	42	0	0
T109	0	54	0	0
T258	0	130	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	377	0	0
T5	13605	4	0	0
T6	17688	0	0	0
T7	17691	4	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T22	610	0	0	0
T23	0	1	0	0
T41	0	3	0	0
T43	0	1	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	2	0	0
T102	0	5	0	0
T109	0	3	0	0
T258	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7846536	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5500	0	0
T4	4882	4481	0	0
T5	13605	10073	0	0
T6	17688	7427	0	0
T12	7140	4886	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7848316	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5524	0	0
T4	4882	4482	0	0
T5	13605	10073	0	0
T6	17688	7452	0	0
T12	7140	4887	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	475	0	0
T5	13605	5	0	0
T6	17688	0	0	0
T7	17691	4	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T11	0	1	0	0
T20	503	0	0	0
T22	610	0	0	0
T23	0	1	0	0
T26	0	2	0	0
T41	0	4	0	0
T43	0	1	0	0
T48	0	2	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	2	0	0
T258	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	415	0	0
T5	13605	4	0	0
T6	17688	0	0	0
T7	17691	4	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T22	610	0	0	0
T23	0	1	0	0
T26	0	2	0	0
T41	0	3	0	0
T43	0	1	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	2	0	0
T102	0	5	0	0
T258	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	377	0	0
T5	13605	4	0	0
T6	17688	0	0	0
T7	17691	4	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T22	610	0	0	0
T23	0	1	0	0
T41	0	3	0	0
T43	0	1	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	2	0	0
T102	0	5	0	0
T109	0	3	0	0
T258	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	377	0	0
T5	13605	4	0	0
T6	17688	0	0	0
T7	17691	4	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T22	610	0	0	0
T23	0	1	0	0
T41	0	3	0	0
T43	0	1	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	2	0	0
T102	0	5	0	0
T109	0	3	0	0
T258	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	15401	0	0
T5	13605	111	0	0
T6	17688	0	0	0
T7	17691	316	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T22	610	0	0	0
T23	0	36	0	0
T41	0	251	0	0
T43	0	60	0	0
T48	0	37	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	14	0	0
T102	0	37	0	0
T109	0	51	0	0
T258	0	127	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	342	0	0
T5	13605	4	0	0
T6	17688	0	0	0
T7	17691	4	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T22	610	0	0	0
T23	0	1	0	0
T41	0	3	0	0
T43	0	1	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	2	0	0
T102	0	5	0	0
T109	0	3	0	0
T258	0	3	0	0