Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T12,T23
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T12,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T12,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T12,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T23
1	0	Covered	T12,T23,T41
1	1	Covered	T4,T12,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T12,T23
0	1	Covered	T4,T49,T65
1	0	Covered	T12,T65,T179

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T41,T42
0	1	Covered	T23,T41,T42
1	0	Covered	T65

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T23,T41,T42
1	-	Covered	T23,T41,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T12,T23
DetectSt	168	Covered	T4,T12,T23
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T23,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T12,T23
DebounceSt->IdleSt	163	Covered	T87,T241,T70
DetectSt->IdleSt	186	Covered	T4,T12,T49
DetectSt->StableSt	191	Covered	T23,T41,T42
IdleSt->DebounceSt	148	Covered	T4,T12,T23
StableSt->IdleSt	206	Covered	T23,T41,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T12,T23
0	1	Covered	T4,T12,T23
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T23
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T12,T23
IdleSt	0	-	-	-	-	-	-	Covered	T4,T12,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T12,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T87,T241,T70
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T12,T23
DetectSt	-	-	-	-	1	-	-	Covered	T4,T12,T49
DetectSt	-	-	-	-	0	1	-	Covered	T23,T41,T42
DetectSt	-	-	-	-	0	0	-	Covered	T4,T12,T23
StableSt	-	-	-	-	-	-	1	Covered	T23,T41,T42
StableSt	-	-	-	-	-	-	0	Covered	T23,T41,T42
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	2824	0	0
CntIncr_A	8886315	96757	0	0
CntNoWrap_A	8886315	8211276	0	0
DetectStDropOut_A	8886315	343	0	0
DetectedOut_A	8886315	76806	0	0
DetectedPulseOut_A	8886315	807	0	0
DisabledIdleSt_A	8886315	7757278	0	0
DisabledNoDetection_A	8886315	7759512	0	0
EnterDebounceSt_A	8886315	1427	0	0
EnterDetectSt_A	8886315	1398	0	0
EnterStableSt_A	8886315	807	0	0
PulseIsPulse_A	8886315	807	0	0
StayInStableSt	8886315	75891	0	0
gen_high_event_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_high_level_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	695	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	2824	0	0
T3	12717	0	0	0
T4	4882	52	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T12	7140	22	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	26	0	0
T41	0	24	0	0
T42	0	44	0	0
T43	0	10	0	0
T44	0	52	0	0
T49	0	50	0	0
T52	79762	0	0	0
T65	0	52	0	0
T66	0	54	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	96757	0	0
T3	12717	0	0	0
T4	4882	1141	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T12	7140	656	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	806	0	0
T41	0	672	0	0
T42	0	968	0	0
T43	0	475	0	0
T44	0	1274	0	0
T49	0	1423	0	0
T52	79762	0	0	0
T65	0	2328	0	0
T66	0	1538	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8211276	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	4429	0	0
T5	13605	13178	0	0
T6	17688	8412	0	0
T12	7140	6717	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	343	0	0
T3	12717	0	0	0
T4	4882	26	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T49	0	25	0	0
T52	79762	0	0	0
T65	0	9	0	0
T66	0	27	0	0
T86	0	9	0	0
T87	0	16	0	0
T91	0	9	0	0
T92	0	26	0	0
T93	0	9	0	0
T95	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	76806	0	0
T23	7818	1294	0	0
T27	2312	0	0	0
T30	505	0	0	0
T41	26234	311	0	0
T42	0	2017	0	0
T43	0	131	0	0
T44	0	1735	0	0
T58	494	0	0	0
T63	503	0	0	0
T64	1764	0	0	0
T65	0	4	0	0
T103	0	64	0	0
T104	905	0	0	0
T105	586	0	0	0
T106	1646	0	0	0
T242	0	2832	0	0
T243	0	3672	0	0
T244	0	2012	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	807	0	0
T23	7818	13	0	0
T27	2312	0	0	0
T30	505	0	0	0
T41	26234	12	0	0
T42	0	22	0	0
T43	0	5	0	0
T44	0	26	0	0
T58	494	0	0	0
T63	503	0	0	0
T64	1764	0	0	0
T65	0	4	0	0
T103	0	4	0	0
T104	905	0	0	0
T105	586	0	0	0
T106	1646	0	0	0
T242	0	20	0	0
T243	0	24	0	0
T244	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7757278	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	2017	0	0
T5	13605	13178	0	0
T6	17688	8412	0	0
T12	7140	3593	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7759512	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	2017	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	3593	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	1427	0	0
T3	12717	0	0	0
T4	4882	26	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T12	7140	11	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	13	0	0
T41	0	12	0	0
T42	0	22	0	0
T43	0	5	0	0
T44	0	26	0	0
T49	0	25	0	0
T52	79762	0	0	0
T65	0	26	0	0
T66	0	27	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	1398	0	0
T3	12717	0	0	0
T4	4882	26	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T12	7140	11	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T23	0	13	0	0
T41	0	12	0	0
T42	0	22	0	0
T43	0	5	0	0
T44	0	26	0	0
T49	0	25	0	0
T52	79762	0	0	0
T65	0	26	0	0
T66	0	27	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	807	0	0
T23	7818	13	0	0
T27	2312	0	0	0
T30	505	0	0	0
T41	26234	12	0	0
T42	0	22	0	0
T43	0	5	0	0
T44	0	26	0	0
T58	494	0	0	0
T63	503	0	0	0
T64	1764	0	0	0
T65	0	4	0	0
T103	0	4	0	0
T104	905	0	0	0
T105	586	0	0	0
T106	1646	0	0	0
T242	0	20	0	0
T243	0	24	0	0
T244	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	807	0	0
T23	7818	13	0	0
T27	2312	0	0	0
T30	505	0	0	0
T41	26234	12	0	0
T42	0	22	0	0
T43	0	5	0	0
T44	0	26	0	0
T58	494	0	0	0
T63	503	0	0	0
T64	1764	0	0	0
T65	0	4	0	0
T103	0	4	0	0
T104	905	0	0	0
T105	586	0	0	0
T106	1646	0	0	0
T242	0	20	0	0
T243	0	24	0	0
T244	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	75891	0	0
T23	7818	1281	0	0
T27	2312	0	0	0
T30	505	0	0	0
T41	26234	297	0	0
T42	0	1989	0	0
T43	0	126	0	0
T44	0	1709	0	0
T58	494	0	0	0
T63	503	0	0	0
T64	1764	0	0	0
T103	0	60	0	0
T104	905	0	0	0
T105	586	0	0	0
T106	1646	0	0	0
T242	0	2807	0	0
T243	0	3643	0	0
T244	0	1982	0	0
T245	0	1262	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	695	0	0
T23	7818	13	0	0
T27	2312	0	0	0
T30	505	0	0	0
T41	26234	10	0	0
T42	0	16	0	0
T43	0	5	0	0
T44	0	26	0	0
T58	494	0	0	0
T63	503	0	0	0
T64	1764	0	0	0
T103	0	4	0	0
T104	905	0	0	0
T105	586	0	0	0
T106	1646	0	0	0
T242	0	15	0	0
T243	0	19	0	0
T244	0	20	0	0
T245	0	18	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T12,T3
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T5,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T4,T12,T3
1	1	Covered	T5,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T268,T94,T261
1	0	Covered	T70,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T6,T7
1	-	Covered	T5,T6,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T6,T7
DetectSt	168	Covered	T5,T6,T7
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T5,T6,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T6,T7
DebounceSt->IdleSt	163	Covered	T6,T11,T28
DetectSt->IdleSt	186	Covered	T268,T94,T261
DetectSt->StableSt	191	Covered	T5,T6,T7
IdleSt->DebounceSt	148	Covered	T5,T6,T7
StableSt->IdleSt	206	Covered	T5,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T11,T28
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T268,T94,T261
DetectSt	-	-	-	-	0	1	-	Covered	T5,T6,T7
DetectSt	-	-	-	-	0	0	-	Covered	T5,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T5,T6,T7
StableSt	-	-	-	-	-	-	0	Covered	T5,T6,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	901	0	0
CntIncr_A	8886315	51306	0	0
CntNoWrap_A	8886315	8213199	0	0
DetectStDropOut_A	8886315	86	0	0
DetectedOut_A	8886315	15958	0	0
DetectedPulseOut_A	8886315	334	0	0
DisabledIdleSt_A	8886315	7845791	0	0
DisabledNoDetection_A	8886315	7847544	0	0
EnterDebounceSt_A	8886315	478	0	0
EnterDetectSt_A	8886315	423	0	0
EnterStableSt_A	8886315	334	0	0
PulseIsPulse_A	8886315	334	0	0
StayInStableSt	8886315	15598	0	0
gen_high_level_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	306	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	901	0	0
T5	13605	6	0	0
T6	17688	3	0	0
T7	17691	2	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T11	0	1	0	0
T20	503	0	0	0
T22	610	0	0	0
T23	0	6	0	0
T26	0	6	0	0
T28	0	9	0	0
T42	0	4	0	0
T48	0	2	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	25	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	51306	0	0
T5	13605	306	0	0
T6	17688	273	0	0
T7	17691	154	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T11	0	32	0	0
T20	503	0	0	0
T22	610	0	0	0
T23	0	207	0	0
T26	0	375	0	0
T28	0	270	0	0
T42	0	58	0	0
T48	0	101	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	979	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8213199	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	4481	0	0
T5	13605	13172	0	0
T6	17688	8409	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	86	0	0
T70	0	1	0	0
T80	523	0	0	0
T94	0	3	0	0
T185	0	3	0	0
T244	21887	0	0	0
T261	0	3	0	0
T262	0	12	0	0
T268	31229	4	0	0
T269	0	5	0	0
T270	0	5	0	0
T271	0	2	0	0
T272	0	3	0	0
T273	503	0	0	0
T274	502	0	0	0
T275	402	0	0	0
T276	422	0	0	0
T277	490	0	0	0
T278	422	0	0	0
T279	436	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	15958	0	0
T5	13605	72	0	0
T6	17688	20	0	0
T7	17691	42	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T22	610	0	0	0
T23	0	361	0	0
T26	0	71	0	0
T28	0	120	0	0
T42	0	132	0	0
T48	0	93	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	740	0	0
T258	0	106	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	334	0	0
T5	13605	3	0	0
T6	17688	1	0	0
T7	17691	1	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T22	610	0	0	0
T23	0	3	0	0
T26	0	3	0	0
T28	0	4	0	0
T42	0	2	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	12	0	0
T258	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7845791	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5500	0	0
T4	4882	4481	0	0
T5	13605	10073	0	0
T6	17688	7427	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7847544	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5524	0	0
T4	4882	4482	0	0
T5	13605	10073	0	0
T6	17688	7452	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	478	0	0
T5	13605	3	0	0
T6	17688	2	0	0
T7	17691	1	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T11	0	1	0	0
T20	503	0	0	0
T22	610	0	0	0
T23	0	3	0	0
T26	0	3	0	0
T28	0	5	0	0
T42	0	2	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	423	0	0
T5	13605	3	0	0
T6	17688	1	0	0
T7	17691	1	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T22	610	0	0	0
T23	0	3	0	0
T26	0	3	0	0
T28	0	4	0	0
T42	0	2	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	12	0	0
T258	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	334	0	0
T5	13605	3	0	0
T6	17688	1	0	0
T7	17691	1	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T22	610	0	0	0
T23	0	3	0	0
T26	0	3	0	0
T28	0	4	0	0
T42	0	2	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	12	0	0
T258	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	334	0	0
T5	13605	3	0	0
T6	17688	1	0	0
T7	17691	1	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T22	610	0	0	0
T23	0	3	0	0
T26	0	3	0	0
T28	0	4	0	0
T42	0	2	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	12	0	0
T258	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	15598	0	0
T5	13605	69	0	0
T6	17688	19	0	0
T7	17691	41	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T22	610	0	0	0
T23	0	358	0	0
T26	0	68	0	0
T28	0	116	0	0
T42	0	130	0	0
T48	0	92	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	728	0	0
T258	0	104	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	306	0	0
T5	13605	3	0	0
T6	17688	1	0	0
T7	17691	1	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T22	610	0	0	0
T23	0	3	0	0
T26	0	3	0	0
T28	0	4	0	0
T42	0	2	0	0
T48	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T81	0	12	0	0
T258	0	2	0	0