Module Definition
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Module : sysrst_ctrl_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sysrst_ctrl_csr_assert 100.00 100.00


Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.02 100.00 96.08 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 36 36 100.00 36 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 36 36 100.00 36 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 1291141418 10240 0 0
auto_block_debounce_ctl_rd_A 1291141418 1202 0 0
auto_block_out_ctl_rd_A 1291141418 1694 0 0
com_det_ctl_0_rd_A 1291141418 3348 0 0
com_det_ctl_1_rd_A 1291141418 3427 0 0
com_det_ctl_2_rd_A 1291141418 3505 0 0
com_det_ctl_3_rd_A 1291141418 3429 0 0
com_out_ctl_0_rd_A 1291141418 3782 0 0
com_out_ctl_1_rd_A 1291141418 3898 0 0
com_out_ctl_2_rd_A 1291141418 3688 0 0
com_out_ctl_3_rd_A 1291141418 3798 0 0
com_pre_det_ctl_0_rd_A 1291141418 953 0 0
com_pre_det_ctl_1_rd_A 1291141418 909 0 0
com_pre_det_ctl_2_rd_A 1291141418 896 0 0
com_pre_det_ctl_3_rd_A 1291141418 1013 0 0
com_pre_sel_ctl_0_rd_A 1291141418 3666 0 0
com_pre_sel_ctl_1_rd_A 1291141418 3754 0 0
com_pre_sel_ctl_2_rd_A 1291141418 3829 0 0
com_pre_sel_ctl_3_rd_A 1291141418 3717 0 0
com_sel_ctl_0_rd_A 1291141418 3869 0 0
com_sel_ctl_1_rd_A 1291141418 3800 0 0
com_sel_ctl_2_rd_A 1291141418 3787 0 0
com_sel_ctl_3_rd_A 1291141418 3872 0 0
ec_rst_ctl_rd_A 1291141418 2118 0 0
intr_enable_rd_A 1291141418 1419 0 0
key_intr_ctl_rd_A 1291141418 2151 0 0
key_intr_debounce_ctl_rd_A 1291141418 910 0 0
key_invert_ctl_rd_A 1291141418 3464 0 0
pin_allowed_ctl_rd_A 1291141418 4587 0 0
pin_out_ctl_rd_A 1291141418 3543 0 0
pin_out_value_rd_A 1291141418 3703 0 0
regwen_rd_A 1291141418 973 0 0
ulp_ac_debounce_ctl_rd_A 1291141418 1024 0 0
ulp_ctl_rd_A 1291141418 1100 0 0
ulp_lid_debounce_ctl_rd_A 1291141418 1064 0 0
ulp_pwrb_debounce_ctl_rd_A 1291141418 1057 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 10240 0 0
T3 157072 12 0 0
T5 156468 0 0 0
T6 189786 18 0 0
T7 884595 0 0 0
T11 0 4 0 0
T13 210997 0 0 0
T14 258115 0 0 0
T15 379107 0 0 0
T20 22657 0 0 0
T29 0 24 0 0
T39 0 24 0 0
T48 0 11 0 0
T52 183453 0 0 0
T53 106006 0 0 0
T90 0 16 0 0
T94 0 12 0 0
T112 0 9 0 0
T246 0 3 0 0

auto_block_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 1202 0 0
T8 64901 0 0 0
T9 120541 0 0 0
T10 63979 0 0 0
T21 245337 0 0 0
T22 76337 7 0 0
T54 336295 0 0 0
T79 0 19 0 0
T82 105669 0 0 0
T83 195273 0 0 0
T84 48564 0 0 0
T85 108103 0 0 0
T90 0 36 0 0
T94 0 38 0 0
T108 0 10 0 0
T112 0 29 0 0
T114 0 29 0 0
T180 0 7 0 0
T298 0 12 0 0
T299 0 3 0 0

auto_block_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 1694 0 0
T8 64901 0 0 0
T9 120541 0 0 0
T10 63979 0 0 0
T21 245337 0 0 0
T22 76337 13 0 0
T54 336295 0 0 0
T79 0 13 0 0
T82 105669 0 0 0
T83 195273 0 0 0
T84 48564 0 0 0
T85 108103 0 0 0
T90 0 19 0 0
T94 0 44 0 0
T108 0 18 0 0
T112 0 36 0 0
T114 0 43 0 0
T180 0 7 0 0
T298 0 22 0 0
T299 0 6 0 0

com_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 3348 0 0
T23 191571 43 0 0
T27 277530 0 0 0
T30 75836 0 0 0
T41 131176 0 0 0
T58 56784 0 0 0
T63 120929 0 0 0
T64 317453 0 0 0
T65 0 32 0 0
T90 0 33 0 0
T94 0 51 0 0
T103 0 54 0 0
T104 443598 0 0 0
T105 17594 0 0 0
T106 156349 0 0 0
T112 0 6 0 0
T242 0 39 0 0
T243 0 85 0 0
T244 0 45 0 0
T260 0 30 0 0

com_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 3427 0 0
T23 191571 41 0 0
T27 277530 0 0 0
T30 75836 0 0 0
T41 131176 0 0 0
T58 56784 0 0 0
T63 120929 0 0 0
T64 317453 0 0 0
T65 0 34 0 0
T90 0 28 0 0
T94 0 41 0 0
T103 0 41 0 0
T104 443598 0 0 0
T105 17594 0 0 0
T106 156349 0 0 0
T112 0 20 0 0
T242 0 42 0 0
T243 0 62 0 0
T244 0 61 0 0
T260 0 24 0 0

com_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 3505 0 0
T23 191571 50 0 0
T27 277530 0 0 0
T30 75836 0 0 0
T41 131176 0 0 0
T58 56784 0 0 0
T63 120929 0 0 0
T64 317453 0 0 0
T65 0 28 0 0
T90 0 26 0 0
T94 0 45 0 0
T103 0 66 0 0
T104 443598 0 0 0
T105 17594 0 0 0
T106 156349 0 0 0
T112 0 23 0 0
T242 0 29 0 0
T243 0 76 0 0
T244 0 58 0 0
T260 0 27 0 0

com_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 3429 0 0
T23 191571 61 0 0
T27 277530 0 0 0
T30 75836 0 0 0
T41 131176 0 0 0
T58 56784 0 0 0
T63 120929 0 0 0
T64 317453 0 0 0
T65 0 28 0 0
T90 0 27 0 0
T94 0 38 0 0
T103 0 44 0 0
T104 443598 0 0 0
T105 17594 0 0 0
T106 156349 0 0 0
T112 0 19 0 0
T242 0 31 0 0
T243 0 66 0 0
T244 0 37 0 0
T260 0 35 0 0

com_out_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 3782 0 0
T23 191571 60 0 0
T27 277530 0 0 0
T30 75836 0 0 0
T41 131176 0 0 0
T58 56784 0 0 0
T63 120929 0 0 0
T64 317453 0 0 0
T65 0 41 0 0
T90 0 24 0 0
T94 0 61 0 0
T103 0 44 0 0
T104 443598 0 0 0
T105 17594 0 0 0
T106 156349 0 0 0
T112 0 27 0 0
T242 0 43 0 0
T243 0 85 0 0
T244 0 54 0 0
T260 0 23 0 0

com_out_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 3898 0 0
T23 191571 71 0 0
T27 277530 0 0 0
T30 75836 0 0 0
T41 131176 0 0 0
T58 56784 0 0 0
T63 120929 0 0 0
T64 317453 0 0 0
T65 0 41 0 0
T90 0 11 0 0
T94 0 39 0 0
T103 0 59 0 0
T104 443598 0 0 0
T105 17594 0 0 0
T106 156349 0 0 0
T112 0 31 0 0
T242 0 30 0 0
T243 0 65 0 0
T244 0 33 0 0
T260 0 20 0 0

com_out_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 3688 0 0
T23 191571 65 0 0
T27 277530 0 0 0
T30 75836 0 0 0
T41 131176 0 0 0
T58 56784 0 0 0
T63 120929 0 0 0
T64 317453 0 0 0
T65 0 29 0 0
T90 0 32 0 0
T94 0 65 0 0
T103 0 28 0 0
T104 443598 0 0 0
T105 17594 0 0 0
T106 156349 0 0 0
T112 0 23 0 0
T242 0 30 0 0
T243 0 53 0 0
T244 0 31 0 0
T260 0 24 0 0

com_out_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 3798 0 0
T23 191571 51 0 0
T27 277530 0 0 0
T30 75836 0 0 0
T41 131176 0 0 0
T58 56784 0 0 0
T63 120929 0 0 0
T64 317453 0 0 0
T65 0 34 0 0
T90 0 32 0 0
T94 0 60 0 0
T103 0 37 0 0
T104 443598 0 0 0
T105 17594 0 0 0
T106 156349 0 0 0
T112 0 14 0 0
T242 0 38 0 0
T243 0 70 0 0
T244 0 46 0 0
T260 0 25 0 0

com_pre_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 953 0 0
T79 0 19 0 0
T88 569091 0 0 0
T89 182786 0 0 0
T90 176979 16 0 0
T94 0 24 0 0
T98 0 14 0 0
T99 59610 0 0 0
T100 63733 0 0 0
T101 63026 0 0 0
T112 231230 7 0 0
T114 0 36 0 0
T163 0 17 0 0
T198 0 14 0 0
T200 0 17 0 0
T254 98902 0 0 0
T255 38705 0 0 0
T256 140253 0 0 0
T300 0 18 0 0

com_pre_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 909 0 0
T79 0 11 0 0
T88 569091 0 0 0
T89 182786 0 0 0
T90 176979 10 0 0
T94 0 26 0 0
T98 0 13 0 0
T99 59610 0 0 0
T100 63733 0 0 0
T101 63026 0 0 0
T112 231230 19 0 0
T114 0 23 0 0
T163 0 7 0 0
T198 0 12 0 0
T200 0 13 0 0
T254 98902 0 0 0
T255 38705 0 0 0
T256 140253 0 0 0
T300 0 11 0 0

com_pre_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 896 0 0
T79 0 22 0 0
T88 569091 0 0 0
T89 182786 0 0 0
T90 176979 24 0 0
T94 0 28 0 0
T98 0 1 0 0
T99 59610 0 0 0
T100 63733 0 0 0
T101 63026 0 0 0
T112 231230 24 0 0
T114 0 13 0 0
T163 0 17 0 0
T198 0 22 0 0
T200 0 12 0 0
T254 98902 0 0 0
T255 38705 0 0 0
T256 140253 0 0 0
T300 0 11 0 0

com_pre_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 1013 0 0
T79 0 17 0 0
T88 569091 0 0 0
T89 182786 0 0 0
T90 176979 25 0 0
T94 0 33 0 0
T98 0 7 0 0
T99 59610 0 0 0
T100 63733 0 0 0
T101 63026 0 0 0
T112 231230 25 0 0
T114 0 47 0 0
T163 0 10 0 0
T198 0 12 0 0
T200 0 12 0 0
T254 98902 0 0 0
T255 38705 0 0 0
T256 140253 0 0 0
T300 0 14 0 0

com_pre_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 3666 0 0
T23 191571 63 0 0
T27 277530 0 0 0
T30 75836 0 0 0
T41 131176 0 0 0
T58 56784 0 0 0
T63 120929 0 0 0
T64 317453 0 0 0
T65 0 34 0 0
T90 0 22 0 0
T94 0 57 0 0
T103 0 35 0 0
T104 443598 0 0 0
T105 17594 0 0 0
T106 156349 0 0 0
T112 0 17 0 0
T242 0 14 0 0
T243 0 67 0 0
T244 0 49 0 0
T260 0 39 0 0

com_pre_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 3754 0 0
T23 191571 43 0 0
T27 277530 0 0 0
T30 75836 0 0 0
T41 131176 0 0 0
T58 56784 0 0 0
T63 120929 0 0 0
T64 317453 0 0 0
T65 0 45 0 0
T90 0 20 0 0
T94 0 41 0 0
T103 0 45 0 0
T104 443598 0 0 0
T105 17594 0 0 0
T106 156349 0 0 0
T112 0 20 0 0
T242 0 38 0 0
T243 0 69 0 0
T244 0 49 0 0
T260 0 27 0 0

com_pre_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 3829 0 0
T23 191571 46 0 0
T27 277530 0 0 0
T30 75836 0 0 0
T41 131176 0 0 0
T58 56784 0 0 0
T63 120929 0 0 0
T64 317453 0 0 0
T65 0 16 0 0
T90 0 28 0 0
T94 0 50 0 0
T103 0 34 0 0
T104 443598 0 0 0
T105 17594 0 0 0
T106 156349 0 0 0
T112 0 18 0 0
T242 0 43 0 0
T243 0 79 0 0
T244 0 41 0 0
T260 0 23 0 0

com_pre_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 3717 0 0
T23 191571 52 0 0
T27 277530 0 0 0
T30 75836 0 0 0
T41 131176 0 0 0
T58 56784 0 0 0
T63 120929 0 0 0
T64 317453 0 0 0
T65 0 27 0 0
T90 0 19 0 0
T94 0 58 0 0
T103 0 43 0 0
T104 443598 0 0 0
T105 17594 0 0 0
T106 156349 0 0 0
T112 0 24 0 0
T242 0 33 0 0
T243 0 82 0 0
T244 0 41 0 0
T260 0 15 0 0

com_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 3869 0 0
T23 191571 64 0 0
T27 277530 0 0 0
T30 75836 0 0 0
T41 131176 0 0 0
T58 56784 0 0 0
T63 120929 0 0 0
T64 317453 0 0 0
T65 0 46 0 0
T90 0 36 0 0
T94 0 38 0 0
T103 0 50 0 0
T104 443598 0 0 0
T105 17594 0 0 0
T106 156349 0 0 0
T112 0 16 0 0
T242 0 32 0 0
T243 0 75 0 0
T244 0 51 0 0
T260 0 33 0 0

com_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 3800 0 0
T23 191571 52 0 0
T27 277530 0 0 0
T30 75836 0 0 0
T41 131176 0 0 0
T58 56784 0 0 0
T63 120929 0 0 0
T64 317453 0 0 0
T65 0 34 0 0
T90 0 22 0 0
T94 0 50 0 0
T103 0 61 0 0
T104 443598 0 0 0
T105 17594 0 0 0
T106 156349 0 0 0
T112 0 29 0 0
T242 0 42 0 0
T243 0 39 0 0
T244 0 39 0 0
T260 0 40 0 0

com_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 3787 0 0
T23 191571 54 0 0
T27 277530 0 0 0
T30 75836 0 0 0
T41 131176 0 0 0
T58 56784 0 0 0
T63 120929 0 0 0
T64 317453 0 0 0
T65 0 27 0 0
T90 0 21 0 0
T94 0 49 0 0
T103 0 39 0 0
T104 443598 0 0 0
T105 17594 0 0 0
T106 156349 0 0 0
T112 0 31 0 0
T242 0 42 0 0
T243 0 61 0 0
T244 0 22 0 0
T260 0 32 0 0

com_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 3872 0 0
T23 191571 58 0 0
T27 277530 0 0 0
T30 75836 0 0 0
T41 131176 0 0 0
T58 56784 0 0 0
T63 120929 0 0 0
T64 317453 0 0 0
T65 0 31 0 0
T90 0 44 0 0
T94 0 55 0 0
T103 0 43 0 0
T104 443598 0 0 0
T105 17594 0 0 0
T106 156349 0 0 0
T112 0 24 0 0
T242 0 29 0 0
T243 0 46 0 0
T244 0 30 0 0
T260 0 33 0 0

ec_rst_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 2118 0 0
T23 191571 3 0 0
T27 277530 0 0 0
T30 75836 0 0 0
T37 0 2 0 0
T38 0 3 0 0
T41 131176 0 0 0
T58 56784 0 0 0
T63 120929 0 0 0
T64 317453 0 0 0
T65 0 10 0 0
T103 0 7 0 0
T104 443598 2 0 0
T105 17594 0 0 0
T106 156349 0 0 0
T181 0 3 0 0
T242 0 7 0 0
T243 0 34 0 0
T244 0 9 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 1419 0 0
T5 156468 0 0 0
T6 189786 0 0 0
T7 884595 0 0 0
T8 64901 0 0 0
T14 258115 52 0 0
T15 379107 0 0 0
T20 22657 0 0 0
T22 76337 0 0 0
T37 0 24 0 0
T52 183453 0 0 0
T53 106006 0 0 0
T64 0 19 0 0
T79 0 48 0 0
T90 0 11 0 0
T94 0 105 0 0
T112 0 22 0 0
T114 0 19 0 0
T163 0 7 0 0
T198 0 39 0 0

key_intr_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 2151 0 0
T33 211467 0 0 0
T37 0 4 0 0
T66 265114 0 0 0
T67 250542 0 0 0
T72 499139 5 0 0
T79 0 14 0 0
T90 0 18 0 0
T94 0 24 0 0
T102 875222 0 0 0
T108 374538 0 0 0
T112 0 26 0 0
T114 0 44 0 0
T152 0 1 0 0
T167 0 3 0 0
T170 51339 0 0 0
T171 55450 0 0 0
T172 96727 0 0 0
T173 19499 0 0 0
T199 0 6 0 0

key_intr_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 910 0 0
T79 0 17 0 0
T88 569091 0 0 0
T89 182786 0 0 0
T90 176979 15 0 0
T94 0 23 0 0
T98 0 6 0 0
T99 59610 0 0 0
T100 63733 0 0 0
T101 63026 0 0 0
T112 231230 17 0 0
T114 0 26 0 0
T163 0 9 0 0
T198 0 2 0 0
T200 0 4 0 0
T254 98902 0 0 0
T255 38705 0 0 0
T256 140253 0 0 0
T300 0 22 0 0

key_invert_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 3464 0 0
T7 884595 0 0 0
T8 64901 0 0 0
T9 120541 0 0 0
T10 63979 0 0 0
T20 22657 16 0 0
T21 245337 0 0 0
T22 76337 0 0 0
T52 183453 0 0 0
T53 106006 0 0 0
T79 0 15 0 0
T82 105669 0 0 0
T90 0 13 0 0
T94 0 38 0 0
T99 0 49 0 0
T112 0 137 0 0
T114 0 112 0 0
T167 0 63 0 0
T301 0 89 0 0
T302 0 76 0 0

pin_allowed_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 4587 0 0
T23 191571 0 0 0
T26 817323 0 0 0
T27 277530 0 0 0
T28 638193 0 0 0
T29 519496 0 0 0
T30 75836 0 0 0
T37 0 53 0 0
T38 0 57 0 0
T47 381734 0 0 0
T62 60664 80 0 0
T63 0 67 0 0
T90 0 9 0 0
T112 0 96 0 0
T146 348441 0 0 0
T147 199257 0 0 0
T273 0 50 0 0
T274 0 70 0 0
T303 0 43 0 0
T304 0 73 0 0

pin_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 3543 0 0
T23 191571 0 0 0
T26 817323 0 0 0
T27 277530 0 0 0
T28 638193 0 0 0
T29 519496 0 0 0
T30 75836 0 0 0
T37 0 66 0 0
T38 0 61 0 0
T47 381734 0 0 0
T62 60664 81 0 0
T63 0 68 0 0
T90 0 30 0 0
T112 0 67 0 0
T146 348441 0 0 0
T147 199257 0 0 0
T273 0 62 0 0
T274 0 44 0 0
T303 0 28 0 0
T304 0 76 0 0

pin_out_value_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 3703 0 0
T23 191571 0 0 0
T26 817323 0 0 0
T27 277530 0 0 0
T28 638193 0 0 0
T29 519496 0 0 0
T30 75836 0 0 0
T37 0 67 0 0
T38 0 62 0 0
T47 381734 0 0 0
T62 60664 77 0 0
T63 0 74 0 0
T90 0 20 0 0
T112 0 78 0 0
T146 348441 0 0 0
T147 199257 0 0 0
T273 0 41 0 0
T274 0 81 0 0
T303 0 35 0 0
T304 0 55 0 0

regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 973 0 0
T79 0 6 0 0
T88 569091 0 0 0
T89 182786 0 0 0
T90 176979 17 0 0
T94 0 32 0 0
T98 0 9 0 0
T99 59610 0 0 0
T100 63733 0 0 0
T101 63026 0 0 0
T112 231230 7 0 0
T114 0 47 0 0
T163 0 20 0 0
T198 0 16 0 0
T200 0 14 0 0
T254 98902 0 0 0
T255 38705 0 0 0
T256 140253 0 0 0
T300 0 16 0 0

ulp_ac_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 1024 0 0
T35 156532 0 0 0
T42 876084 0 0 0
T55 174944 12 0 0
T56 104859 0 0 0
T60 61838 0 0 0
T61 662090 0 0 0
T79 0 12 0 0
T90 0 22 0 0
T94 0 39 0 0
T112 0 18 0 0
T114 0 41 0 0
T119 0 16 0 0
T127 125828 0 0 0
T128 250480 0 0 0
T129 248458 0 0 0
T130 133620 0 0 0
T202 0 9 0 0
T206 0 2 0 0
T305 0 14 0 0

ulp_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 1100 0 0
T35 156532 0 0 0
T42 876084 0 0 0
T55 174944 1 0 0
T56 104859 0 0 0
T60 61838 0 0 0
T61 662090 0 0 0
T79 0 20 0 0
T90 0 12 0 0
T94 0 34 0 0
T112 0 35 0 0
T114 0 41 0 0
T119 0 5 0 0
T127 125828 0 0 0
T128 250480 0 0 0
T129 248458 0 0 0
T130 133620 0 0 0
T202 0 10 0 0
T206 0 3 0 0
T305 0 4 0 0

ulp_lid_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 1064 0 0
T35 156532 0 0 0
T42 876084 0 0 0
T55 174944 18 0 0
T56 104859 0 0 0
T60 61838 0 0 0
T61 662090 0 0 0
T79 0 18 0 0
T90 0 23 0 0
T94 0 26 0 0
T112 0 35 0 0
T114 0 29 0 0
T119 0 17 0 0
T127 125828 0 0 0
T128 250480 0 0 0
T129 248458 0 0 0
T130 133620 0 0 0
T202 0 2 0 0
T206 0 7 0 0
T305 0 10 0 0

ulp_pwrb_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1291141418 1057 0 0
T35 156532 0 0 0
T42 876084 0 0 0
T55 174944 11 0 0
T56 104859 0 0 0
T60 61838 0 0 0
T61 662090 0 0 0
T79 0 10 0 0
T90 0 8 0 0
T94 0 25 0 0
T112 0 31 0 0
T114 0 41 0 0
T119 0 10 0 0
T127 125828 0 0 0
T128 250480 0 0 0
T129 248458 0 0 0
T130 133620 0 0 0
T202 0 19 0 0
T206 0 4 0 0
T305 0 8 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%