Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
778 |
1 |
|
|
T12 |
13 |
|
T4 |
14 |
|
T6 |
6 |
| auto[1] |
862 |
1 |
|
|
T12 |
7 |
|
T4 |
6 |
|
T6 |
14 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
812 |
1 |
|
|
T12 |
5 |
|
T4 |
9 |
|
T6 |
10 |
| auto[1] |
828 |
1 |
|
|
T12 |
15 |
|
T4 |
11 |
|
T6 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
818 |
1 |
|
|
T12 |
11 |
|
T4 |
10 |
|
T6 |
10 |
| auto[1] |
822 |
1 |
|
|
T12 |
9 |
|
T4 |
10 |
|
T6 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
813 |
1 |
|
|
T12 |
10 |
|
T4 |
5 |
|
T6 |
11 |
| auto[1] |
827 |
1 |
|
|
T12 |
10 |
|
T4 |
15 |
|
T6 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
836 |
1 |
|
|
T12 |
7 |
|
T4 |
9 |
|
T6 |
11 |
| auto[1] |
804 |
1 |
|
|
T12 |
13 |
|
T4 |
11 |
|
T6 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
821 |
1 |
|
|
T12 |
8 |
|
T4 |
8 |
|
T6 |
12 |
| auto[1] |
819 |
1 |
|
|
T12 |
12 |
|
T4 |
12 |
|
T6 |
8 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
805 |
1 |
|
|
T12 |
7 |
|
T4 |
12 |
|
T6 |
6 |
| auto[1] |
835 |
1 |
|
|
T12 |
13 |
|
T4 |
8 |
|
T6 |
14 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
828 |
1 |
|
|
T12 |
11 |
|
T4 |
9 |
|
T6 |
10 |
| auto[1] |
812 |
1 |
|
|
T12 |
9 |
|
T4 |
11 |
|
T6 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
789 |
1 |
|
|
T12 |
10 |
|
T4 |
10 |
|
T6 |
9 |
| auto[1] |
851 |
1 |
|
|
T12 |
10 |
|
T4 |
10 |
|
T6 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
839 |
1 |
|
|
T12 |
9 |
|
T4 |
10 |
|
T6 |
8 |
| auto[1] |
801 |
1 |
|
|
T12 |
11 |
|
T4 |
10 |
|
T6 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
826 |
1 |
|
|
T12 |
13 |
|
T4 |
12 |
|
T6 |
8 |
| auto[1] |
814 |
1 |
|
|
T12 |
7 |
|
T4 |
8 |
|
T6 |
12 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
825 |
1 |
|
|
T12 |
11 |
|
T4 |
9 |
|
T6 |
8 |
| auto[1] |
815 |
1 |
|
|
T12 |
9 |
|
T4 |
11 |
|
T6 |
12 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
826 |
1 |
|
|
T12 |
11 |
|
T4 |
6 |
|
T6 |
9 |
| auto[1] |
814 |
1 |
|
|
T12 |
9 |
|
T4 |
14 |
|
T6 |
11 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
812 |
1 |
|
|
T12 |
5 |
|
T4 |
9 |
|
T6 |
10 |
| auto[1] |
828 |
1 |
|
|
T12 |
15 |
|
T4 |
11 |
|
T6 |
10 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
821 |
1 |
|
|
T12 |
12 |
|
T4 |
11 |
|
T6 |
9 |
| auto[1] |
819 |
1 |
|
|
T12 |
8 |
|
T4 |
9 |
|
T6 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
836 |
1 |
|
|
T12 |
11 |
|
T4 |
12 |
|
T6 |
8 |
| auto[1] |
804 |
1 |
|
|
T12 |
9 |
|
T4 |
8 |
|
T6 |
12 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
831 |
1 |
|
|
T12 |
11 |
|
T4 |
11 |
|
T6 |
6 |
| auto[1] |
809 |
1 |
|
|
T12 |
9 |
|
T4 |
9 |
|
T6 |
14 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
860 |
1 |
|
|
T12 |
12 |
|
T4 |
12 |
|
T6 |
9 |
| auto[1] |
780 |
1 |
|
|
T12 |
8 |
|
T4 |
8 |
|
T6 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
851 |
1 |
|
|
T12 |
7 |
|
T4 |
9 |
|
T6 |
8 |
| auto[1] |
789 |
1 |
|
|
T12 |
13 |
|
T4 |
11 |
|
T6 |
12 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
798 |
1 |
|
|
T12 |
13 |
|
T4 |
8 |
|
T6 |
10 |
| auto[1] |
842 |
1 |
|
|
T12 |
7 |
|
T4 |
12 |
|
T6 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
833 |
1 |
|
|
T12 |
11 |
|
T4 |
12 |
|
T6 |
9 |
| auto[1] |
807 |
1 |
|
|
T12 |
9 |
|
T4 |
8 |
|
T6 |
11 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
809 |
1 |
|
|
T12 |
7 |
|
T4 |
12 |
|
T6 |
9 |
| auto[1] |
831 |
1 |
|
|
T12 |
13 |
|
T4 |
8 |
|
T6 |
11 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
844 |
1 |
|
|
T12 |
11 |
|
T4 |
8 |
|
T6 |
7 |
| auto[1] |
796 |
1 |
|
|
T12 |
9 |
|
T4 |
12 |
|
T6 |
13 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
825 |
1 |
|
|
T12 |
11 |
|
T4 |
9 |
|
T6 |
8 |
| auto[1] |
815 |
1 |
|
|
T12 |
9 |
|
T4 |
11 |
|
T6 |
12 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
406 |
1 |
|
|
T12 |
6 |
|
T4 |
6 |
|
T6 |
5 |
| auto[0] |
auto[1] |
415 |
1 |
|
|
T12 |
6 |
|
T4 |
5 |
|
T6 |
4 |
| auto[1] |
auto[0] |
412 |
1 |
|
|
T12 |
5 |
|
T4 |
4 |
|
T6 |
5 |
| auto[1] |
auto[1] |
407 |
1 |
|
|
T12 |
3 |
|
T4 |
5 |
|
T6 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
411 |
1 |
|
|
T12 |
5 |
|
T4 |
4 |
|
T6 |
5 |
| auto[0] |
auto[1] |
425 |
1 |
|
|
T12 |
6 |
|
T4 |
8 |
|
T6 |
3 |
| auto[1] |
auto[0] |
402 |
1 |
|
|
T12 |
5 |
|
T4 |
1 |
|
T6 |
6 |
| auto[1] |
auto[1] |
402 |
1 |
|
|
T12 |
4 |
|
T4 |
7 |
|
T6 |
6 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
427 |
1 |
|
|
T12 |
3 |
|
T4 |
4 |
|
T6 |
2 |
| auto[0] |
auto[1] |
404 |
1 |
|
|
T12 |
8 |
|
T4 |
7 |
|
T6 |
4 |
| auto[1] |
auto[0] |
409 |
1 |
|
|
T12 |
4 |
|
T4 |
5 |
|
T6 |
9 |
| auto[1] |
auto[1] |
400 |
1 |
|
|
T12 |
5 |
|
T4 |
4 |
|
T6 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
434 |
1 |
|
|
T12 |
4 |
|
T4 |
4 |
|
T6 |
4 |
| auto[0] |
auto[1] |
426 |
1 |
|
|
T12 |
8 |
|
T4 |
8 |
|
T6 |
5 |
| auto[1] |
auto[0] |
387 |
1 |
|
|
T12 |
4 |
|
T4 |
4 |
|
T6 |
8 |
| auto[1] |
auto[1] |
393 |
1 |
|
|
T12 |
4 |
|
T4 |
4 |
|
T6 |
3 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
409 |
1 |
|
|
T12 |
2 |
|
T4 |
6 |
|
T6 |
1 |
| auto[0] |
auto[1] |
442 |
1 |
|
|
T12 |
5 |
|
T4 |
3 |
|
T6 |
7 |
| auto[1] |
auto[0] |
396 |
1 |
|
|
T12 |
5 |
|
T4 |
6 |
|
T6 |
5 |
| auto[1] |
auto[1] |
393 |
1 |
|
|
T12 |
8 |
|
T4 |
5 |
|
T6 |
7 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
394 |
1 |
|
|
T12 |
7 |
|
T4 |
4 |
|
T6 |
4 |
| auto[0] |
auto[1] |
404 |
1 |
|
|
T12 |
6 |
|
T4 |
4 |
|
T6 |
6 |
| auto[1] |
auto[0] |
434 |
1 |
|
|
T12 |
4 |
|
T4 |
5 |
|
T6 |
6 |
| auto[1] |
auto[1] |
408 |
1 |
|
|
T12 |
3 |
|
T4 |
7 |
|
T6 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
428 |
1 |
|
|
T12 |
4 |
|
T4 |
6 |
|
T6 |
5 |
| auto[0] |
auto[1] |
381 |
1 |
|
|
T12 |
3 |
|
T4 |
6 |
|
T6 |
4 |
| auto[1] |
auto[0] |
411 |
1 |
|
|
T12 |
5 |
|
T4 |
4 |
|
T6 |
3 |
| auto[1] |
auto[1] |
420 |
1 |
|
|
T12 |
8 |
|
T4 |
4 |
|
T6 |
8 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
439 |
1 |
|
|
T12 |
8 |
|
T4 |
5 |
|
T6 |
4 |
| auto[0] |
auto[1] |
405 |
1 |
|
|
T12 |
3 |
|
T4 |
3 |
|
T6 |
3 |
| auto[1] |
auto[0] |
387 |
1 |
|
|
T12 |
5 |
|
T4 |
7 |
|
T6 |
4 |
| auto[1] |
auto[1] |
409 |
1 |
|
|
T12 |
4 |
|
T4 |
5 |
|
T6 |
9 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
412 |
1 |
|
|
T12 |
7 |
|
T4 |
6 |
|
T6 |
2 |
| auto[0] |
auto[1] |
414 |
1 |
|
|
T12 |
4 |
|
T6 |
7 |
|
T7 |
6 |
| auto[1] |
auto[0] |
366 |
1 |
|
|
T12 |
6 |
|
T4 |
8 |
|
T6 |
4 |
| auto[1] |
auto[1] |
448 |
1 |
|
|
T12 |
3 |
|
T4 |
6 |
|
T6 |
7 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
812 |
1 |
|
|
T12 |
5 |
|
T4 |
9 |
|
T6 |
10 |
| auto[1] |
auto[1] |
828 |
1 |
|
|
T12 |
15 |
|
T4 |
11 |
|
T6 |
10 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
383 |
1 |
|
|
T12 |
4 |
|
T4 |
5 |
|
T6 |
3 |
| auto[0] |
auto[1] |
450 |
1 |
|
|
T12 |
7 |
|
T4 |
7 |
|
T6 |
6 |
| auto[1] |
auto[0] |
406 |
1 |
|
|
T12 |
6 |
|
T4 |
5 |
|
T6 |
6 |
| auto[1] |
auto[1] |
401 |
1 |
|
|
T12 |
3 |
|
T4 |
3 |
|
T6 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
825 |
1 |
|
|
T12 |
11 |
|
T4 |
9 |
|
T6 |
8 |
| auto[1] |
auto[1] |
815 |
1 |
|
|
T12 |
9 |
|
T4 |
11 |
|
T6 |
12 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
92 |
1 |
|
|
T7 |
12 |
|
T66 |
13 |
|
T167 |
8 |
| auto[1] |
108 |
1 |
|
|
T7 |
8 |
|
T66 |
7 |
|
T167 |
12 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
101 |
1 |
|
|
T7 |
9 |
|
T66 |
12 |
|
T167 |
11 |
| auto[1] |
99 |
1 |
|
|
T7 |
11 |
|
T66 |
8 |
|
T167 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
100 |
1 |
|
|
T7 |
11 |
|
T66 |
9 |
|
T167 |
13 |
| auto[1] |
100 |
1 |
|
|
T7 |
9 |
|
T66 |
11 |
|
T167 |
7 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
113 |
1 |
|
|
T7 |
10 |
|
T66 |
8 |
|
T167 |
11 |
| auto[1] |
87 |
1 |
|
|
T7 |
10 |
|
T66 |
12 |
|
T167 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
104 |
1 |
|
|
T7 |
9 |
|
T66 |
12 |
|
T167 |
9 |
| auto[1] |
96 |
1 |
|
|
T7 |
11 |
|
T66 |
8 |
|
T167 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
94 |
1 |
|
|
T7 |
9 |
|
T66 |
9 |
|
T167 |
9 |
| auto[1] |
106 |
1 |
|
|
T7 |
11 |
|
T66 |
11 |
|
T167 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
103 |
1 |
|
|
T7 |
12 |
|
T66 |
12 |
|
T167 |
8 |
| auto[1] |
97 |
1 |
|
|
T7 |
8 |
|
T66 |
8 |
|
T167 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
104 |
1 |
|
|
T7 |
7 |
|
T66 |
14 |
|
T167 |
11 |
| auto[1] |
96 |
1 |
|
|
T7 |
13 |
|
T66 |
6 |
|
T167 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
95 |
1 |
|
|
T7 |
9 |
|
T66 |
13 |
|
T167 |
7 |
| auto[1] |
105 |
1 |
|
|
T7 |
11 |
|
T66 |
7 |
|
T167 |
13 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
101 |
1 |
|
|
T7 |
11 |
|
T66 |
9 |
|
T167 |
9 |
| auto[1] |
99 |
1 |
|
|
T7 |
9 |
|
T66 |
11 |
|
T167 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
85 |
1 |
|
|
T7 |
9 |
|
T66 |
10 |
|
T167 |
7 |
| auto[1] |
115 |
1 |
|
|
T7 |
11 |
|
T66 |
10 |
|
T167 |
13 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
96 |
1 |
|
|
T7 |
12 |
|
T66 |
8 |
|
T167 |
13 |
| auto[1] |
104 |
1 |
|
|
T7 |
8 |
|
T66 |
12 |
|
T167 |
7 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
122 |
1 |
|
|
T7 |
11 |
|
T66 |
14 |
|
T167 |
11 |
| auto[1] |
78 |
1 |
|
|
T7 |
9 |
|
T66 |
6 |
|
T167 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
101 |
1 |
|
|
T7 |
9 |
|
T66 |
12 |
|
T167 |
11 |
| auto[1] |
99 |
1 |
|
|
T7 |
11 |
|
T66 |
8 |
|
T167 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
104 |
1 |
|
|
T7 |
7 |
|
T66 |
12 |
|
T167 |
9 |
| auto[1] |
96 |
1 |
|
|
T7 |
13 |
|
T66 |
8 |
|
T167 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
99 |
1 |
|
|
T7 |
10 |
|
T66 |
9 |
|
T167 |
13 |
| auto[1] |
101 |
1 |
|
|
T7 |
10 |
|
T66 |
11 |
|
T167 |
7 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
87 |
1 |
|
|
T7 |
10 |
|
T66 |
11 |
|
T167 |
8 |
| auto[1] |
113 |
1 |
|
|
T7 |
10 |
|
T66 |
9 |
|
T167 |
12 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
111 |
1 |
|
|
T7 |
12 |
|
T66 |
10 |
|
T167 |
10 |
| auto[1] |
89 |
1 |
|
|
T7 |
8 |
|
T66 |
10 |
|
T167 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
100 |
1 |
|
|
T7 |
9 |
|
T66 |
11 |
|
T167 |
10 |
| auto[1] |
100 |
1 |
|
|
T7 |
11 |
|
T66 |
9 |
|
T167 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
95 |
1 |
|
|
T7 |
12 |
|
T66 |
7 |
|
T167 |
9 |
| auto[1] |
105 |
1 |
|
|
T7 |
8 |
|
T66 |
13 |
|
T167 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
99 |
1 |
|
|
T7 |
9 |
|
T66 |
12 |
|
T167 |
8 |
| auto[1] |
101 |
1 |
|
|
T7 |
11 |
|
T66 |
8 |
|
T167 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
99 |
1 |
|
|
T7 |
9 |
|
T66 |
10 |
|
T167 |
10 |
| auto[1] |
101 |
1 |
|
|
T7 |
11 |
|
T66 |
10 |
|
T167 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
111 |
1 |
|
|
T7 |
11 |
|
T66 |
11 |
|
T167 |
10 |
| auto[1] |
89 |
1 |
|
|
T7 |
9 |
|
T66 |
9 |
|
T167 |
10 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
96 |
1 |
|
|
T7 |
12 |
|
T66 |
8 |
|
T167 |
13 |
| auto[1] |
104 |
1 |
|
|
T7 |
8 |
|
T66 |
12 |
|
T167 |
7 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
52 |
1 |
|
|
T7 |
3 |
|
T66 |
7 |
|
T167 |
8 |
| auto[0] |
auto[1] |
52 |
1 |
|
|
T7 |
4 |
|
T66 |
5 |
|
T167 |
1 |
| auto[1] |
auto[0] |
48 |
1 |
|
|
T7 |
8 |
|
T66 |
2 |
|
T167 |
5 |
| auto[1] |
auto[1] |
48 |
1 |
|
|
T7 |
5 |
|
T66 |
6 |
|
T167 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
56 |
1 |
|
|
T7 |
4 |
|
T66 |
5 |
|
T167 |
9 |
| auto[0] |
auto[1] |
43 |
1 |
|
|
T7 |
6 |
|
T66 |
4 |
|
T167 |
4 |
| auto[1] |
auto[0] |
57 |
1 |
|
|
T7 |
6 |
|
T66 |
3 |
|
T167 |
2 |
| auto[1] |
auto[1] |
44 |
1 |
|
|
T7 |
4 |
|
T66 |
8 |
|
T167 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
42 |
1 |
|
|
T7 |
5 |
|
T66 |
6 |
|
T167 |
5 |
| auto[0] |
auto[1] |
45 |
1 |
|
|
T7 |
5 |
|
T66 |
5 |
|
T167 |
3 |
| auto[1] |
auto[0] |
62 |
1 |
|
|
T7 |
4 |
|
T66 |
6 |
|
T167 |
4 |
| auto[1] |
auto[1] |
51 |
1 |
|
|
T7 |
6 |
|
T66 |
3 |
|
T167 |
8 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
49 |
1 |
|
|
T7 |
6 |
|
T66 |
4 |
|
T167 |
6 |
| auto[0] |
auto[1] |
62 |
1 |
|
|
T7 |
6 |
|
T66 |
6 |
|
T167 |
4 |
| auto[1] |
auto[0] |
45 |
1 |
|
|
T7 |
3 |
|
T66 |
5 |
|
T167 |
3 |
| auto[1] |
auto[1] |
44 |
1 |
|
|
T7 |
5 |
|
T66 |
5 |
|
T167 |
7 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
50 |
1 |
|
|
T7 |
5 |
|
T66 |
6 |
|
T167 |
4 |
| auto[0] |
auto[1] |
50 |
1 |
|
|
T7 |
4 |
|
T66 |
5 |
|
T167 |
6 |
| auto[1] |
auto[0] |
53 |
1 |
|
|
T7 |
7 |
|
T66 |
6 |
|
T167 |
4 |
| auto[1] |
auto[1] |
47 |
1 |
|
|
T7 |
4 |
|
T66 |
3 |
|
T167 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
48 |
1 |
|
|
T7 |
4 |
|
T66 |
5 |
|
T167 |
5 |
| auto[0] |
auto[1] |
47 |
1 |
|
|
T7 |
8 |
|
T66 |
2 |
|
T167 |
4 |
| auto[1] |
auto[0] |
56 |
1 |
|
|
T7 |
3 |
|
T66 |
9 |
|
T167 |
6 |
| auto[1] |
auto[1] |
49 |
1 |
|
|
T7 |
5 |
|
T66 |
4 |
|
T167 |
5 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
55 |
1 |
|
|
T7 |
4 |
|
T66 |
4 |
|
T167 |
5 |
| auto[0] |
auto[1] |
44 |
1 |
|
|
T7 |
5 |
|
T66 |
6 |
|
T167 |
5 |
| auto[1] |
auto[0] |
46 |
1 |
|
|
T7 |
7 |
|
T66 |
5 |
|
T167 |
4 |
| auto[1] |
auto[1] |
55 |
1 |
|
|
T7 |
4 |
|
T66 |
5 |
|
T167 |
6 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
53 |
1 |
|
|
T7 |
4 |
|
T66 |
5 |
|
T167 |
4 |
| auto[0] |
auto[1] |
58 |
1 |
|
|
T7 |
7 |
|
T66 |
6 |
|
T167 |
6 |
| auto[1] |
auto[0] |
32 |
1 |
|
|
T7 |
5 |
|
T66 |
5 |
|
T167 |
3 |
| auto[1] |
auto[1] |
57 |
1 |
|
|
T7 |
4 |
|
T66 |
4 |
|
T167 |
7 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
54 |
1 |
|
|
T7 |
7 |
|
T66 |
9 |
|
T167 |
5 |
| auto[0] |
auto[1] |
68 |
1 |
|
|
T7 |
4 |
|
T66 |
5 |
|
T167 |
6 |
| auto[1] |
auto[0] |
38 |
1 |
|
|
T7 |
5 |
|
T66 |
4 |
|
T167 |
3 |
| auto[1] |
auto[1] |
40 |
1 |
|
|
T7 |
4 |
|
T66 |
2 |
|
T167 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
101 |
1 |
|
|
T7 |
9 |
|
T66 |
12 |
|
T167 |
11 |
| auto[1] |
auto[1] |
99 |
1 |
|
|
T7 |
11 |
|
T66 |
8 |
|
T167 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
51 |
1 |
|
|
T7 |
6 |
|
T66 |
6 |
|
T167 |
4 |
| auto[0] |
auto[1] |
48 |
1 |
|
|
T7 |
3 |
|
T66 |
6 |
|
T167 |
4 |
| auto[1] |
auto[0] |
44 |
1 |
|
|
T7 |
3 |
|
T66 |
7 |
|
T167 |
3 |
| auto[1] |
auto[1] |
57 |
1 |
|
|
T7 |
8 |
|
T66 |
1 |
|
T167 |
9 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
96 |
1 |
|
|
T7 |
12 |
|
T66 |
8 |
|
T167 |
13 |
| auto[1] |
auto[1] |
104 |
1 |
|
|
T7 |
8 |
|
T66 |
12 |
|
T167 |
7 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
26 |
1 |
|
|
T168 |
10 |
|
T118 |
9 |
|
T288 |
7 |
| auto[1] |
34 |
1 |
|
|
T168 |
10 |
|
T118 |
11 |
|
T288 |
13 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
28 |
1 |
|
|
T168 |
6 |
|
T118 |
12 |
|
T288 |
10 |
| auto[1] |
32 |
1 |
|
|
T168 |
14 |
|
T118 |
8 |
|
T288 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
31 |
1 |
|
|
T168 |
13 |
|
T118 |
10 |
|
T288 |
8 |
| auto[1] |
29 |
1 |
|
|
T168 |
7 |
|
T118 |
10 |
|
T288 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
38 |
1 |
|
|
T168 |
14 |
|
T118 |
14 |
|
T288 |
10 |
| auto[1] |
22 |
1 |
|
|
T168 |
6 |
|
T118 |
6 |
|
T288 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
26 |
1 |
|
|
T168 |
10 |
|
T118 |
8 |
|
T288 |
8 |
| auto[1] |
34 |
1 |
|
|
T168 |
10 |
|
T118 |
12 |
|
T288 |
12 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
35 |
1 |
|
|
T168 |
13 |
|
T118 |
9 |
|
T288 |
13 |
| auto[1] |
25 |
1 |
|
|
T168 |
7 |
|
T118 |
11 |
|
T288 |
7 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
29 |
1 |
|
|
T168 |
7 |
|
T118 |
9 |
|
T288 |
13 |
| auto[1] |
31 |
1 |
|
|
T168 |
13 |
|
T118 |
11 |
|
T288 |
7 |