Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.ac_present
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key0_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key0_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key1_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key1_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key2_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key2_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.lid_open
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_ac_present
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_bat_disable
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key0_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key0_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key1_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key1_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key2_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key2_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_lid_open
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_pwrb_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_pwrb_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_z3_wakeup
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key0_inXval
Uncovered bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key0_outXval
Uncovered bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key1_inXval
Uncovered bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key1_outXval
Uncovered bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key2_inXval
Uncovered bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key2_outXval
Uncovered bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for pwrb_inXval
Uncovered bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for pwrb_outXval
Uncovered bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for ac_presentXval
Uncovered bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
2 |
0 |
0.00 |
2 |
| Automatically Generated Cross Bins |
2 |
2 |
0 |
0.00 |
2 |
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Uncovered bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0]] |
[auto[0]] |
0 |
1 |
1 |
|
| [auto[1]] |
[auto[1]] |
0 |
1 |
1 |
|
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for lid_openXval
Uncovered bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
2 |
0 |
0.00 |
2 |
| Automatically Generated Cross Bins |
2 |
2 |
0 |
0.00 |
2 |
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Uncovered bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0]] |
[auto[0]] |
0 |
1 |
1 |
|
| [auto[1]] |
[auto[1]] |
0 |
1 |
1 |
|
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
894 |
1 |
|
|
T21 |
8 |
|
T22 |
11 |
|
T20 |
7 |
| auto[1] |
906 |
1 |
|
|
T21 |
12 |
|
T22 |
9 |
|
T20 |
13 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
923 |
1 |
|
|
T21 |
12 |
|
T22 |
11 |
|
T20 |
15 |
| auto[1] |
877 |
1 |
|
|
T21 |
8 |
|
T22 |
9 |
|
T20 |
5 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
905 |
1 |
|
|
T21 |
7 |
|
T22 |
9 |
|
T20 |
7 |
| auto[1] |
895 |
1 |
|
|
T21 |
13 |
|
T22 |
11 |
|
T20 |
13 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
905 |
1 |
|
|
T21 |
8 |
|
T22 |
8 |
|
T20 |
10 |
| auto[1] |
895 |
1 |
|
|
T21 |
12 |
|
T22 |
12 |
|
T20 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
858 |
1 |
|
|
T21 |
12 |
|
T22 |
8 |
|
T20 |
12 |
| auto[1] |
942 |
1 |
|
|
T21 |
8 |
|
T22 |
12 |
|
T20 |
8 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
923 |
1 |
|
|
T21 |
10 |
|
T22 |
11 |
|
T20 |
9 |
| auto[1] |
877 |
1 |
|
|
T21 |
10 |
|
T22 |
9 |
|
T20 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
923 |
1 |
|
|
T21 |
7 |
|
T22 |
14 |
|
T20 |
11 |
| auto[1] |
877 |
1 |
|
|
T21 |
13 |
|
T22 |
6 |
|
T20 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
890 |
1 |
|
|
T21 |
9 |
|
T22 |
10 |
|
T20 |
9 |
| auto[1] |
910 |
1 |
|
|
T21 |
11 |
|
T22 |
10 |
|
T20 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
895 |
1 |
|
|
T21 |
10 |
|
T22 |
13 |
|
T20 |
6 |
| auto[1] |
905 |
1 |
|
|
T21 |
10 |
|
T22 |
7 |
|
T20 |
14 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
901 |
1 |
|
|
T21 |
8 |
|
T22 |
7 |
|
T20 |
7 |
| auto[1] |
899 |
1 |
|
|
T21 |
12 |
|
T22 |
13 |
|
T20 |
13 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
881 |
1 |
|
|
T21 |
13 |
|
T22 |
13 |
|
T20 |
11 |
| auto[1] |
919 |
1 |
|
|
T21 |
7 |
|
T22 |
7 |
|
T20 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
913 |
1 |
|
|
T21 |
8 |
|
T22 |
9 |
|
T20 |
13 |
| auto[1] |
887 |
1 |
|
|
T21 |
12 |
|
T22 |
11 |
|
T20 |
7 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
928 |
1 |
|
|
T21 |
11 |
|
T22 |
14 |
|
T20 |
8 |
| auto[1] |
872 |
1 |
|
|
T21 |
9 |
|
T22 |
6 |
|
T20 |
12 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
923 |
1 |
|
|
T21 |
12 |
|
T22 |
11 |
|
T20 |
15 |
| auto[1] |
877 |
1 |
|
|
T21 |
8 |
|
T22 |
9 |
|
T20 |
5 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
893 |
1 |
|
|
T21 |
13 |
|
T22 |
12 |
|
T20 |
13 |
| auto[1] |
907 |
1 |
|
|
T21 |
7 |
|
T22 |
8 |
|
T20 |
7 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
909 |
1 |
|
|
T21 |
12 |
|
T22 |
11 |
|
T20 |
6 |
| auto[1] |
891 |
1 |
|
|
T21 |
8 |
|
T22 |
9 |
|
T20 |
14 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
867 |
1 |
|
|
T21 |
9 |
|
T22 |
8 |
|
T20 |
12 |
| auto[1] |
933 |
1 |
|
|
T21 |
11 |
|
T22 |
12 |
|
T20 |
8 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
868 |
1 |
|
|
T21 |
11 |
|
T22 |
9 |
|
T20 |
9 |
| auto[1] |
932 |
1 |
|
|
T21 |
9 |
|
T22 |
11 |
|
T20 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
880 |
1 |
|
|
T21 |
10 |
|
T22 |
10 |
|
T20 |
13 |
| auto[1] |
920 |
1 |
|
|
T21 |
10 |
|
T22 |
10 |
|
T20 |
7 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
875 |
1 |
|
|
T21 |
8 |
|
T22 |
10 |
|
T20 |
9 |
| auto[1] |
925 |
1 |
|
|
T21 |
12 |
|
T22 |
10 |
|
T20 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
887 |
1 |
|
|
T21 |
9 |
|
T22 |
7 |
|
T20 |
8 |
| auto[1] |
913 |
1 |
|
|
T21 |
11 |
|
T22 |
13 |
|
T20 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
889 |
1 |
|
|
T21 |
16 |
|
T22 |
11 |
|
T20 |
6 |
| auto[1] |
911 |
1 |
|
|
T21 |
4 |
|
T22 |
9 |
|
T20 |
14 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
895 |
1 |
|
|
T21 |
11 |
|
T22 |
11 |
|
T20 |
14 |
| auto[1] |
905 |
1 |
|
|
T21 |
9 |
|
T22 |
9 |
|
T20 |
6 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
913 |
1 |
|
|
T21 |
8 |
|
T22 |
9 |
|
T20 |
13 |
| auto[1] |
887 |
1 |
|
|
T21 |
12 |
|
T22 |
11 |
|
T20 |
7 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
450 |
1 |
|
|
T21 |
4 |
|
T22 |
6 |
|
T20 |
5 |
| auto[0] |
auto[1] |
443 |
1 |
|
|
T21 |
9 |
|
T22 |
6 |
|
T20 |
8 |
| auto[1] |
auto[0] |
455 |
1 |
|
|
T21 |
3 |
|
T22 |
3 |
|
T20 |
2 |
| auto[1] |
auto[1] |
452 |
1 |
|
|
T21 |
4 |
|
T22 |
5 |
|
T20 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
458 |
1 |
|
|
T21 |
4 |
|
T22 |
5 |
|
T20 |
3 |
| auto[0] |
auto[1] |
451 |
1 |
|
|
T21 |
8 |
|
T22 |
6 |
|
T20 |
3 |
| auto[1] |
auto[0] |
447 |
1 |
|
|
T21 |
4 |
|
T22 |
3 |
|
T20 |
7 |
| auto[1] |
auto[1] |
444 |
1 |
|
|
T21 |
4 |
|
T22 |
6 |
|
T20 |
7 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
435 |
1 |
|
|
T21 |
8 |
|
T22 |
4 |
|
T20 |
8 |
| auto[0] |
auto[1] |
432 |
1 |
|
|
T21 |
1 |
|
T22 |
4 |
|
T20 |
4 |
| auto[1] |
auto[0] |
423 |
1 |
|
|
T21 |
4 |
|
T22 |
4 |
|
T20 |
4 |
| auto[1] |
auto[1] |
510 |
1 |
|
|
T21 |
7 |
|
T22 |
8 |
|
T20 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
468 |
1 |
|
|
T21 |
8 |
|
T22 |
6 |
|
T20 |
5 |
| auto[0] |
auto[1] |
400 |
1 |
|
|
T21 |
3 |
|
T22 |
3 |
|
T20 |
4 |
| auto[1] |
auto[0] |
455 |
1 |
|
|
T21 |
2 |
|
T22 |
5 |
|
T20 |
4 |
| auto[1] |
auto[1] |
477 |
1 |
|
|
T21 |
7 |
|
T22 |
6 |
|
T20 |
7 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
465 |
1 |
|
|
T21 |
5 |
|
T22 |
6 |
|
T20 |
7 |
| auto[0] |
auto[1] |
415 |
1 |
|
|
T21 |
5 |
|
T22 |
4 |
|
T20 |
6 |
| auto[1] |
auto[0] |
458 |
1 |
|
|
T21 |
2 |
|
T22 |
8 |
|
T20 |
4 |
| auto[1] |
auto[1] |
462 |
1 |
|
|
T21 |
8 |
|
T22 |
2 |
|
T20 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
446 |
1 |
|
|
T21 |
5 |
|
T22 |
4 |
|
T20 |
4 |
| auto[0] |
auto[1] |
429 |
1 |
|
|
T21 |
3 |
|
T22 |
6 |
|
T20 |
5 |
| auto[1] |
auto[0] |
444 |
1 |
|
|
T21 |
4 |
|
T22 |
6 |
|
T20 |
5 |
| auto[1] |
auto[1] |
481 |
1 |
|
|
T21 |
8 |
|
T22 |
4 |
|
T20 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
441 |
1 |
|
|
T21 |
8 |
|
T22 |
2 |
|
T20 |
2 |
| auto[0] |
auto[1] |
448 |
1 |
|
|
T21 |
8 |
|
T22 |
9 |
|
T20 |
4 |
| auto[1] |
auto[0] |
460 |
1 |
|
|
T22 |
5 |
|
T20 |
5 |
|
T10 |
3 |
| auto[1] |
auto[1] |
451 |
1 |
|
|
T21 |
4 |
|
T22 |
4 |
|
T20 |
9 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
434 |
1 |
|
|
T21 |
8 |
|
T22 |
5 |
|
T20 |
8 |
| auto[0] |
auto[1] |
461 |
1 |
|
|
T21 |
3 |
|
T22 |
6 |
|
T20 |
6 |
| auto[1] |
auto[0] |
447 |
1 |
|
|
T21 |
5 |
|
T22 |
8 |
|
T20 |
3 |
| auto[1] |
auto[1] |
458 |
1 |
|
|
T21 |
4 |
|
T22 |
1 |
|
T20 |
3 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
435 |
1 |
|
|
T21 |
3 |
|
T22 |
8 |
|
T20 |
2 |
| auto[0] |
auto[1] |
493 |
1 |
|
|
T21 |
8 |
|
T22 |
6 |
|
T20 |
6 |
| auto[1] |
auto[0] |
459 |
1 |
|
|
T21 |
5 |
|
T22 |
3 |
|
T20 |
5 |
| auto[1] |
auto[1] |
413 |
1 |
|
|
T21 |
4 |
|
T22 |
3 |
|
T20 |
7 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
923 |
1 |
|
|
T21 |
12 |
|
T22 |
11 |
|
T20 |
15 |
| auto[1] |
auto[1] |
877 |
1 |
|
|
T21 |
8 |
|
T22 |
9 |
|
T20 |
5 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
437 |
1 |
|
|
T21 |
2 |
|
T22 |
4 |
|
T20 |
3 |
| auto[0] |
auto[1] |
450 |
1 |
|
|
T21 |
7 |
|
T22 |
3 |
|
T20 |
5 |
| auto[1] |
auto[0] |
458 |
1 |
|
|
T21 |
8 |
|
T22 |
9 |
|
T20 |
3 |
| auto[1] |
auto[1] |
455 |
1 |
|
|
T21 |
3 |
|
T22 |
4 |
|
T20 |
9 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
913 |
1 |
|
|
T21 |
8 |
|
T22 |
9 |
|
T20 |
13 |
| auto[1] |
auto[1] |
887 |
1 |
|
|
T21 |
12 |
|
T22 |
11 |
|
T20 |
7 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
167 |
1 |
|
|
T12 |
10 |
|
T183 |
12 |
|
T114 |
11 |
| auto[1] |
153 |
1 |
|
|
T12 |
10 |
|
T183 |
8 |
|
T114 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
165 |
1 |
|
|
T12 |
8 |
|
T183 |
10 |
|
T114 |
10 |
| auto[1] |
155 |
1 |
|
|
T12 |
12 |
|
T183 |
10 |
|
T114 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
164 |
1 |
|
|
T12 |
12 |
|
T183 |
11 |
|
T114 |
7 |
| auto[1] |
156 |
1 |
|
|
T12 |
8 |
|
T183 |
9 |
|
T114 |
13 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
150 |
1 |
|
|
T12 |
12 |
|
T183 |
10 |
|
T114 |
13 |
| auto[1] |
170 |
1 |
|
|
T12 |
8 |
|
T183 |
10 |
|
T114 |
7 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
160 |
1 |
|
|
T12 |
12 |
|
T183 |
11 |
|
T114 |
14 |
| auto[1] |
160 |
1 |
|
|
T12 |
8 |
|
T183 |
9 |
|
T114 |
6 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
151 |
1 |
|
|
T12 |
15 |
|
T183 |
7 |
|
T114 |
8 |
| auto[1] |
169 |
1 |
|
|
T12 |
5 |
|
T183 |
13 |
|
T114 |
12 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
163 |
1 |
|
|
T12 |
13 |
|
T183 |
9 |
|
T114 |
13 |
| auto[1] |
157 |
1 |
|
|
T12 |
7 |
|
T183 |
11 |
|
T114 |
7 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
162 |
1 |
|
|
T12 |
11 |
|
T183 |
9 |
|
T114 |
13 |
| auto[1] |
158 |
1 |
|
|
T12 |
9 |
|
T183 |
11 |
|
T114 |
7 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
168 |
1 |
|
|
T12 |
12 |
|
T183 |
10 |
|
T114 |
10 |
| auto[1] |
152 |
1 |
|
|
T12 |
8 |
|
T183 |
10 |
|
T114 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
165 |
1 |
|
|
T12 |
13 |
|
T183 |
11 |
|
T114 |
10 |
| auto[1] |
155 |
1 |
|
|
T12 |
7 |
|
T183 |
9 |
|
T114 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
155 |
1 |
|
|
T12 |
9 |
|
T183 |
15 |
|
T114 |
9 |
| auto[1] |
165 |
1 |
|
|
T12 |
11 |
|
T183 |
5 |
|
T114 |
11 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
156 |
1 |
|
|
T12 |
10 |
|
T183 |
9 |
|
T114 |
9 |
| auto[1] |
164 |
1 |
|
|
T12 |
10 |
|
T183 |
11 |
|
T114 |
11 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
150 |
1 |
|
|
T12 |
10 |
|
T183 |
10 |
|
T114 |
6 |
| auto[1] |
170 |
1 |
|
|
T12 |
10 |
|
T183 |
10 |
|
T114 |
14 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
165 |
1 |
|
|
T12 |
8 |
|
T183 |
10 |
|
T114 |
10 |
| auto[1] |
155 |
1 |
|
|
T12 |
12 |
|
T183 |
10 |
|
T114 |
10 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
184 |
1 |
|
|
T12 |
9 |
|
T183 |
11 |
|
T114 |
13 |
| auto[1] |
136 |
1 |
|
|
T12 |
11 |
|
T183 |
9 |
|
T114 |
7 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
176 |
1 |
|
|
T12 |
9 |
|
T183 |
6 |
|
T114 |
11 |
| auto[1] |
144 |
1 |
|
|
T12 |
11 |
|
T183 |
14 |
|
T114 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
168 |
1 |
|
|
T12 |
12 |
|
T183 |
6 |
|
T114 |
10 |
| auto[1] |
152 |
1 |
|
|
T12 |
8 |
|
T183 |
14 |
|
T114 |
10 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
167 |
1 |
|
|
T12 |
9 |
|
T183 |
12 |
|
T114 |
10 |
| auto[1] |
153 |
1 |
|
|
T12 |
11 |
|
T183 |
8 |
|
T114 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
158 |
1 |
|
|
T12 |
11 |
|
T183 |
8 |
|
T114 |
12 |
| auto[1] |
162 |
1 |
|
|
T12 |
9 |
|
T183 |
12 |
|
T114 |
8 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
169 |
1 |
|
|
T12 |
11 |
|
T183 |
16 |
|
T114 |
10 |
| auto[1] |
151 |
1 |
|
|
T12 |
9 |
|
T183 |
4 |
|
T114 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
156 |
1 |
|
|
T12 |
5 |
|
T183 |
7 |
|
T114 |
9 |
| auto[1] |
164 |
1 |
|
|
T12 |
15 |
|
T183 |
13 |
|
T114 |
11 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T12 |
10 |
|
T183 |
10 |
|
T114 |
10 |
| auto[1] |
173 |
1 |
|
|
T12 |
10 |
|
T183 |
10 |
|
T114 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
165 |
1 |
|
|
T12 |
12 |
|
T183 |
12 |
|
T114 |
9 |
| auto[1] |
155 |
1 |
|
|
T12 |
8 |
|
T183 |
8 |
|
T114 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
156 |
1 |
|
|
T12 |
10 |
|
T183 |
9 |
|
T114 |
9 |
| auto[1] |
164 |
1 |
|
|
T12 |
10 |
|
T183 |
11 |
|
T114 |
11 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
92 |
1 |
|
|
T12 |
6 |
|
T183 |
5 |
|
T114 |
4 |
| auto[0] |
auto[1] |
92 |
1 |
|
|
T12 |
3 |
|
T183 |
6 |
|
T114 |
9 |
| auto[1] |
auto[0] |
72 |
1 |
|
|
T12 |
6 |
|
T183 |
6 |
|
T114 |
3 |
| auto[1] |
auto[1] |
64 |
1 |
|
|
T12 |
5 |
|
T183 |
3 |
|
T114 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
81 |
1 |
|
|
T12 |
6 |
|
T183 |
2 |
|
T114 |
6 |
| auto[0] |
auto[1] |
95 |
1 |
|
|
T12 |
3 |
|
T183 |
4 |
|
T114 |
5 |
| auto[1] |
auto[0] |
69 |
1 |
|
|
T12 |
6 |
|
T183 |
8 |
|
T114 |
7 |
| auto[1] |
auto[1] |
75 |
1 |
|
|
T12 |
5 |
|
T183 |
6 |
|
T114 |
2 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
85 |
1 |
|
|
T12 |
6 |
|
T183 |
4 |
|
T114 |
7 |
| auto[0] |
auto[1] |
83 |
1 |
|
|
T12 |
6 |
|
T183 |
2 |
|
T114 |
3 |
| auto[1] |
auto[0] |
75 |
1 |
|
|
T12 |
6 |
|
T183 |
7 |
|
T114 |
7 |
| auto[1] |
auto[1] |
77 |
1 |
|
|
T12 |
2 |
|
T183 |
7 |
|
T114 |
3 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
80 |
1 |
|
|
T12 |
6 |
|
T183 |
5 |
|
T114 |
4 |
| auto[0] |
auto[1] |
87 |
1 |
|
|
T12 |
3 |
|
T183 |
7 |
|
T114 |
6 |
| auto[1] |
auto[0] |
71 |
1 |
|
|
T12 |
9 |
|
T183 |
2 |
|
T114 |
4 |
| auto[1] |
auto[1] |
82 |
1 |
|
|
T12 |
2 |
|
T183 |
6 |
|
T114 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
77 |
1 |
|
|
T12 |
7 |
|
T183 |
3 |
|
T114 |
8 |
| auto[0] |
auto[1] |
81 |
1 |
|
|
T12 |
4 |
|
T183 |
5 |
|
T114 |
4 |
| auto[1] |
auto[0] |
86 |
1 |
|
|
T12 |
6 |
|
T183 |
6 |
|
T114 |
5 |
| auto[1] |
auto[1] |
76 |
1 |
|
|
T12 |
3 |
|
T183 |
6 |
|
T114 |
3 |