Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.77 98.81 96.78 100.00 95.51 98.26 99.52 88.50


Total tests in report: 914
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
54.81 54.81 72.33 72.33 59.28 59.28 90.30 90.30 10.26 10.26 74.16 74.16 60.40 60.40 16.96 16.96 /workspace/coverage/default/46.sysrst_ctrl_combo_detect.224613101
68.97 14.15 82.72 10.39 72.50 13.22 93.72 3.42 36.54 26.28 83.96 9.80 74.66 14.26 38.66 21.70 /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.3569370720
76.70 7.73 86.32 3.60 75.86 3.36 93.95 0.23 62.18 25.64 87.10 3.14 86.71 12.04 44.77 6.11 /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.816463952
83.38 6.68 93.04 6.72 84.93 9.07 95.78 1.83 72.44 10.26 92.57 5.47 95.18 8.48 49.73 4.96 /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.2057395652
86.54 3.16 96.68 3.64 90.47 5.54 97.49 1.71 72.44 0.00 96.19 3.62 96.53 1.35 56.00 6.27 /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.2300134060
88.41 1.87 96.79 0.11 90.72 0.25 97.49 0.00 74.36 1.92 96.38 0.18 96.72 0.19 66.41 10.41 /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.1241617710
89.70 1.28 96.81 0.02 91.89 1.16 98.17 0.68 74.36 0.00 96.41 0.04 96.72 0.00 73.50 7.09 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.439467742
90.70 1.00 97.37 0.56 93.86 1.97 98.17 0.00 78.21 3.85 97.04 0.63 96.72 0.00 73.50 0.00 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.1938547467
91.32 0.62 97.65 0.28 94.08 0.23 98.17 0.00 80.13 1.92 97.15 0.11 97.11 0.39 74.92 1.42 /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.2650005189
91.84 0.52 97.70 0.06 94.29 0.20 98.17 0.00 80.13 0.00 97.15 0.00 97.11 0.00 78.30 3.38 /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.1658132772
92.29 0.46 97.84 0.13 94.36 0.08 98.17 0.00 82.69 2.56 97.30 0.15 97.40 0.29 78.30 0.00 /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.700942255
92.66 0.36 97.87 0.04 94.36 0.00 98.17 0.00 83.97 1.28 97.38 0.07 97.40 0.00 79.44 1.15 /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.481042502
93.02 0.36 97.95 0.07 94.51 0.15 98.17 0.00 85.26 1.28 97.45 0.07 97.59 0.19 80.21 0.76 /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.1512970481
93.37 0.35 98.06 0.11 94.57 0.05 98.17 0.00 87.18 1.92 97.60 0.15 97.78 0.19 80.21 0.00 /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2576815827
93.65 0.28 98.06 0.00 94.59 0.03 99.77 1.60 87.18 0.00 97.60 0.00 97.88 0.10 80.48 0.27 /workspace/coverage/default/4.sysrst_ctrl_sec_cm.2038479805
93.91 0.26 98.12 0.06 94.92 0.33 99.77 0.00 88.46 1.28 97.67 0.07 97.98 0.10 80.48 0.00 /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.1947275295
94.16 0.25 98.19 0.07 94.97 0.05 99.77 0.00 89.74 1.28 97.74 0.07 98.17 0.19 80.53 0.05 /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.1801390890
94.39 0.23 98.26 0.07 94.99 0.03 99.77 0.00 90.38 0.64 97.78 0.04 98.27 0.10 81.30 0.76 /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.1286390327
94.59 0.20 98.30 0.04 94.99 0.00 99.77 0.00 91.67 1.28 97.86 0.07 98.27 0.00 81.30 0.00 /workspace/coverage/default/37.sysrst_ctrl_edge_detect.3958101975
94.77 0.17 98.40 0.09 95.30 0.30 99.77 0.00 91.67 0.00 98.00 0.15 98.94 0.67 81.30 0.00 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2425859035
94.93 0.17 98.43 0.04 95.32 0.03 99.77 0.00 92.31 0.64 98.04 0.04 99.04 0.10 81.62 0.33 /workspace/coverage/default/16.sysrst_ctrl_stress_all.1849707146
95.08 0.14 98.49 0.06 95.37 0.05 99.77 0.00 92.95 0.64 98.08 0.04 99.13 0.10 81.73 0.11 /workspace/coverage/default/3.sysrst_ctrl_edge_detect.2815646842
95.20 0.13 98.54 0.06 95.40 0.03 99.77 0.00 92.95 0.00 98.08 0.00 99.13 0.00 82.55 0.82 /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.3830509982
95.33 0.12 98.54 0.00 96.21 0.81 99.77 0.00 92.95 0.00 98.08 0.00 99.13 0.00 82.61 0.05 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3422945185
95.45 0.12 98.58 0.04 96.31 0.10 99.77 0.00 92.95 0.00 98.08 0.00 99.13 0.00 83.32 0.71 /workspace/coverage/default/18.sysrst_ctrl_stress_all.2982276063
95.57 0.12 98.62 0.04 96.33 0.03 99.77 0.00 93.59 0.64 98.11 0.04 99.23 0.10 83.32 0.00 /workspace/coverage/default/24.sysrst_ctrl_edge_detect.3713016803
95.67 0.10 98.62 0.00 96.33 0.00 99.77 0.00 93.59 0.00 98.11 0.00 99.23 0.00 84.02 0.71 /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3136655658
95.77 0.10 98.64 0.02 96.33 0.00 99.77 0.00 94.23 0.64 98.15 0.04 99.23 0.00 84.02 0.00 /workspace/coverage/default/16.sysrst_ctrl_edge_detect.809791662
95.87 0.10 98.66 0.02 96.33 0.00 99.77 0.00 94.87 0.64 98.19 0.04 99.23 0.00 84.02 0.00 /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3570375605
95.97 0.10 98.68 0.02 96.33 0.00 99.77 0.00 95.51 0.64 98.23 0.04 99.23 0.00 84.02 0.00 /workspace/coverage/default/34.sysrst_ctrl_edge_detect.1923016383
96.05 0.08 98.71 0.04 96.33 0.00 99.77 0.00 95.51 0.00 98.23 0.00 99.23 0.00 84.57 0.55 /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2429864714
96.13 0.08 98.73 0.02 96.33 0.00 99.77 0.00 95.51 0.00 98.26 0.04 99.23 0.00 85.06 0.49 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3823710560
96.19 0.06 98.73 0.00 96.36 0.03 99.77 0.00 95.51 0.00 98.26 0.00 99.33 0.10 85.39 0.33 /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.4038112187
96.26 0.06 98.73 0.00 96.36 0.00 99.77 0.00 95.51 0.00 98.26 0.00 99.33 0.00 85.82 0.44 /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.4078408505
96.31 0.05 98.79 0.06 96.44 0.08 100.00 0.23 95.51 0.00 98.26 0.00 99.33 0.00 85.82 0.00 /workspace/coverage/default/1.sysrst_ctrl_alert_test.1221523625
96.35 0.05 98.79 0.00 96.44 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.33 0.00 86.15 0.33 /workspace/coverage/default/9.sysrst_ctrl_stress_all.1465061275
96.39 0.04 98.79 0.00 96.49 0.05 100.00 0.00 95.51 0.00 98.26 0.00 99.42 0.10 86.26 0.11 /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2365858160
96.42 0.03 98.79 0.00 96.51 0.03 100.00 0.00 95.51 0.00 98.26 0.00 99.42 0.00 86.48 0.22 /workspace/coverage/default/49.sysrst_ctrl_combo_detect.1549687704
96.45 0.02 98.79 0.00 96.51 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.42 0.00 86.64 0.16 /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2186393421
96.47 0.02 98.79 0.00 96.51 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.42 0.00 86.80 0.16 /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.3560986534
96.49 0.02 98.79 0.00 96.51 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.42 0.00 86.97 0.16 /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.3573987835
96.52 0.02 98.79 0.00 96.51 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.10 87.02 0.05 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1276263522
96.53 0.02 98.79 0.00 96.64 0.13 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 87.02 0.00 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1979580855
96.55 0.02 98.79 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 87.13 0.11 /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.4155651736
96.57 0.02 98.79 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 87.24 0.11 /workspace/coverage/default/24.sysrst_ctrl_combo_detect.1330835431
96.58 0.02 98.79 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 87.35 0.11 /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2559986300
96.60 0.02 98.79 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 87.46 0.11 /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3311651541
96.61 0.02 98.79 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 87.57 0.11 /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.4273647802
96.62 0.01 98.79 0.00 96.71 0.08 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 87.57 0.00 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.4120236892
96.63 0.01 98.81 0.02 96.71 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 87.62 0.05 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3329586012
96.64 0.01 98.81 0.00 96.71 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 87.68 0.05 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.816292868
96.65 0.01 98.81 0.00 96.71 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 87.73 0.05 /workspace/coverage/default/13.sysrst_ctrl_stress_all.3105679804
96.66 0.01 98.81 0.00 96.71 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 87.79 0.05 /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.638248060
96.66 0.01 98.81 0.00 96.71 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 87.84 0.05 /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.1211099985
96.67 0.01 98.81 0.00 96.71 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 87.90 0.05 /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2581566284
96.68 0.01 98.81 0.00 96.71 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 87.95 0.05 /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.2126243308
96.69 0.01 98.81 0.00 96.71 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 88.00 0.05 /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.2831605572
96.70 0.01 98.81 0.00 96.71 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 88.06 0.05 /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.654208771
96.70 0.01 98.81 0.00 96.71 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 88.11 0.05 /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.153780765
96.71 0.01 98.81 0.00 96.71 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 88.17 0.05 /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.4132854001
96.72 0.01 98.81 0.00 96.71 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 88.22 0.05 /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.2424821597
96.73 0.01 98.81 0.00 96.71 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 88.28 0.05 /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2757478174
96.73 0.01 98.81 0.00 96.71 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 88.33 0.05 /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2069196987
96.74 0.01 98.81 0.00 96.71 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 88.39 0.05 /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3957240066
96.75 0.01 98.81 0.00 96.71 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 88.44 0.05 /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.3700336803
96.76 0.01 98.81 0.00 96.71 0.00 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 88.50 0.05 /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.339816107
96.77 0.01 98.81 0.00 96.76 0.05 100.00 0.00 95.51 0.00 98.26 0.00 99.52 0.00 88.50 0.00 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1737780262

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1747640585
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.164154088
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.139299917
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1816659824
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1468199952
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2963253396
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3905421717
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.125633818
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3141372480
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.237316601
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3333521708
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2937123999
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1057718199
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3507466866
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.4073793662
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2988428512
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3985545122
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1556893630
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.64978536
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.698895013
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2019998384
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.155125806
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1793782929
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1680369484
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1697184561
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.4291064336
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.88146024
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3116022562
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1456026298
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3659803325
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3026674030
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2788081212
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.283693995
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1930448281
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3005495255
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1944925463
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.4203646780
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2032240647
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.135059451
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.4104640060
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.926653360
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.4155248395
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.792069787
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.521654580
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1902961978
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3124567356
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3947153254
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1956721462
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2422738571
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.4024969144
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.4186986223
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2386383887
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2023359003
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.1089790565
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2424431734
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.991801635
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3417420894
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.118308009
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1708244568
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.880901575
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3550516197
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.564055613
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2256037085
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2532694603
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2936505499
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3244307680
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2941020978
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.2600418495
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1975668648
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2636567605
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.770638697
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3430865817
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2666526613
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3390154266
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.514921887
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.4149144559
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1539803294
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3610805339
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3812768234
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1681150683
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.3004691484
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1160429592
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/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.1280186883
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.1069604146
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2350754531
/workspace/coverage/default/41.sysrst_ctrl_smoke.1965529065
/workspace/coverage/default/41.sysrst_ctrl_stress_all.2729182336
/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1509767611
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1812281335
/workspace/coverage/default/42.sysrst_ctrl_alert_test.4031120294
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2895087842
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.3114050008
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3972138601
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.872797850
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3051490678
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2791962176
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.4154587416
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.210928234
/workspace/coverage/default/42.sysrst_ctrl_smoke.3713549057
/workspace/coverage/default/42.sysrst_ctrl_stress_all.1984585752
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1432313114
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3733257055
/workspace/coverage/default/43.sysrst_ctrl_alert_test.2098412867
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.2045999398
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.2862371087
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3565331728
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.3896591513
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1377930963
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3607763949
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1320261977
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1868490664
/workspace/coverage/default/43.sysrst_ctrl_smoke.1382600938
/workspace/coverage/default/43.sysrst_ctrl_stress_all.3151043237
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3837659254
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3114763528
/workspace/coverage/default/44.sysrst_ctrl_alert_test.3148265119
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1574574772
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.1892299438
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2357253816
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3855277260
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.2516828685
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1773927373
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.1446148684
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.269198250
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.406448837
/workspace/coverage/default/44.sysrst_ctrl_smoke.2398567951
/workspace/coverage/default/44.sysrst_ctrl_stress_all.2843069928
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2358631247
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.1956440483
/workspace/coverage/default/45.sysrst_ctrl_alert_test.3314069010
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1072975873
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.3195762405
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.956746360
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3220438171
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.4104717428
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3872583292
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.4066541210
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.3264187917
/workspace/coverage/default/45.sysrst_ctrl_smoke.867269149
/workspace/coverage/default/45.sysrst_ctrl_stress_all.384680829
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.689216484
/workspace/coverage/default/46.sysrst_ctrl_alert_test.2414194895
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.294917592
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.2831167907
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3257814258
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.4179805671
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1517894812
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.1547582834
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1952142508
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1000475433
/workspace/coverage/default/46.sysrst_ctrl_smoke.1222796332
/workspace/coverage/default/46.sysrst_ctrl_stress_all.538202384
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1154730461
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3559566748
/workspace/coverage/default/47.sysrst_ctrl_alert_test.1873386666
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2014959533
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.4217059810
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2272784508
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3694014804
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.3805350787
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2163504725
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2933903360
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.2077804804
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1841157431
/workspace/coverage/default/47.sysrst_ctrl_smoke.1179775130
/workspace/coverage/default/47.sysrst_ctrl_stress_all.1182444802
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.394951544
/workspace/coverage/default/48.sysrst_ctrl_alert_test.3548113101
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.589374746
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.3003017222
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2604529507
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.262246858
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.368159594
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3866907526
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.1008200611
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.277948813
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.2436446122
/workspace/coverage/default/48.sysrst_ctrl_smoke.3330181846
/workspace/coverage/default/48.sysrst_ctrl_stress_all.2112249516
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1132105786
/workspace/coverage/default/49.sysrst_ctrl_alert_test.1876584164
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2324462521
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3862142168
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.835425655
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.2487856878
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3327929612
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.89435089
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3434097206
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.675992298
/workspace/coverage/default/49.sysrst_ctrl_smoke.548171902
/workspace/coverage/default/49.sysrst_ctrl_stress_all.149665335
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.1182554919
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3845658074
/workspace/coverage/default/5.sysrst_ctrl_alert_test.1373813577
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.66862425
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.298060087
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.226015506
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.514628553
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.3557857104
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1393101920
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.2999514365
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.1592255015
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.2616158622
/workspace/coverage/default/5.sysrst_ctrl_smoke.1911247738
/workspace/coverage/default/5.sysrst_ctrl_stress_all.261701839
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.4284052254
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.2185366954
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1396998596
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.139189259
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.4064033196
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.3873449626
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3864323514
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1268126514
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.22263078
/workspace/coverage/default/6.sysrst_ctrl_alert_test.85317061
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1410777083
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.2040074460
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1847296464
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.1044176035
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2472303147
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1816618482
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.3863546429
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1917483561
/workspace/coverage/default/6.sysrst_ctrl_smoke.3636852535
/workspace/coverage/default/6.sysrst_ctrl_stress_all.3242375629
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3733590473
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.558603660
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.861793170
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.4073805270
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.276125676
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.2459927767
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3850874043
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2841383657
/workspace/coverage/default/7.sysrst_ctrl_alert_test.1269815791
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.557725582
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.3377823214
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.1607966496
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2393043825
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.2412162823
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1267160086
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2678574546
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.388444971
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.2383571770
/workspace/coverage/default/7.sysrst_ctrl_smoke.3545785497
/workspace/coverage/default/7.sysrst_ctrl_stress_all.4082903519
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.862471750
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3803182999
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1890893993
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3737461368
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2634471371
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2737531795
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3217111015
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.4176411665
/workspace/coverage/default/8.sysrst_ctrl_alert_test.421014753
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1260921754
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.3303965391
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.4204550674
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.2016817793
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1369277850
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.3004560583
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3676456082
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.447544276
/workspace/coverage/default/8.sysrst_ctrl_smoke.2020581336
/workspace/coverage/default/8.sysrst_ctrl_stress_all.1297118719
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1020574812
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1737785564
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.3566705750
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.193635072
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1965104840
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.3517323339
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1532829392
/workspace/coverage/default/9.sysrst_ctrl_alert_test.1283852998
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.442152325
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.1673318026
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.2636545875
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.3949204683
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.3259644724
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.460874314
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.4078005318
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.1273085317
/workspace/coverage/default/9.sysrst_ctrl_smoke.2707006289
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.562075608
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.792764100
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.4179243178
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2603882168
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3133468697
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.1892315486
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.2203499842
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.924277589
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.931991629
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.148881276



Total test records in report: 914
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3565331728 Jun 24 06:34:43 PM PDT 24 Jun 24 06:34:52 PM PDT 24 2778572404 ps
T5 /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.3915992504 Jun 24 06:34:03 PM PDT 24 Jun 24 06:34:06 PM PDT 24 2050043630 ps
T6 /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.601876087 Jun 24 06:32:35 PM PDT 24 Jun 24 06:32:44 PM PDT 24 2513922513 ps
T21 /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.1446148684 Jun 24 06:34:47 PM PDT 24 Jun 24 06:34:49 PM PDT 24 2497902401 ps
T22 /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.3506159063 Jun 24 06:33:47 PM PDT 24 Jun 24 06:33:56 PM PDT 24 2451543629 ps
T23 /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.4035939986 Jun 24 06:32:50 PM PDT 24 Jun 24 06:32:54 PM PDT 24 2522435890 ps
T24 /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.3074442052 Jun 24 06:33:58 PM PDT 24 Jun 24 06:34:04 PM PDT 24 3252641996 ps
T1 /workspace/coverage/default/46.sysrst_ctrl_combo_detect.224613101 Jun 24 06:34:50 PM PDT 24 Jun 24 06:37:37 PM PDT 24 127491398975 ps
T14 /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.3239634874 Jun 24 06:33:06 PM PDT 24 Jun 24 06:33:13 PM PDT 24 25514220825 ps
T15 /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.2300134060 Jun 24 06:34:46 PM PDT 24 Jun 24 06:34:54 PM PDT 24 2510024940 ps
T16 /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.3793885306 Jun 24 06:33:38 PM PDT 24 Jun 24 06:33:45 PM PDT 24 2121804513 ps
T17 /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.2436446122 Jun 24 06:34:57 PM PDT 24 Jun 24 06:35:01 PM PDT 24 2538988989 ps
T18 /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.557725582 Jun 24 06:32:40 PM PDT 24 Jun 24 06:41:22 PM PDT 24 203520292859 ps
T19 /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.3020958829 Jun 24 06:33:08 PM PDT 24 Jun 24 06:33:14 PM PDT 24 2035124157 ps
T2 /workspace/coverage/default/22.sysrst_ctrl_stress_all.4094395659 Jun 24 06:33:33 PM PDT 24 Jun 24 06:34:46 PM PDT 24 123904476300 ps
T20 /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.3293543933 Jun 24 06:33:23 PM PDT 24 Jun 24 06:33:30 PM PDT 24 2466202918 ps
T3 /workspace/coverage/default/3.sysrst_ctrl_edge_detect.2815646842 Jun 24 06:32:39 PM PDT 24 Jun 24 06:32:43 PM PDT 24 3930764812 ps
T7 /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.3666217884 Jun 24 06:33:37 PM PDT 24 Jun 24 06:34:41 PM PDT 24 222899736204 ps
T30 /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.3057562634 Jun 24 06:34:22 PM PDT 24 Jun 24 06:34:37 PM PDT 24 3669759485 ps
T8 /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.2275354808 Jun 24 06:34:20 PM PDT 24 Jun 24 06:34:40 PM PDT 24 33249572302 ps
T50 /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1254747777 Jun 24 06:32:33 PM PDT 24 Jun 24 06:32:43 PM PDT 24 3406149709 ps
T55 /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.505391812 Jun 24 06:33:41 PM PDT 24 Jun 24 06:33:44 PM PDT 24 2635696100 ps
T9 /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.685252874 Jun 24 06:34:10 PM PDT 24 Jun 24 06:38:36 PM PDT 24 105031442545 ps
T68 /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1010691344 Jun 24 06:34:11 PM PDT 24 Jun 24 06:34:20 PM PDT 24 2612321258 ps
T58 /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.2530267165 Jun 24 06:33:45 PM PDT 24 Jun 24 06:33:49 PM PDT 24 2724605099 ps
T69 /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.556923483 Jun 24 06:33:32 PM PDT 24 Jun 24 06:33:36 PM PDT 24 2635596244 ps
T34 /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3733257055 Jun 24 06:34:41 PM PDT 24 Jun 24 06:34:44 PM PDT 24 11164006415 ps
T112 /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.4078005318 Jun 24 06:32:49 PM PDT 24 Jun 24 06:32:53 PM PDT 24 2080634691 ps
T10 /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.1658132772 Jun 24 06:32:50 PM PDT 24 Jun 24 06:34:38 PM PDT 24 187953772765 ps
T210 /workspace/coverage/default/8.sysrst_ctrl_smoke.2020581336 Jun 24 06:32:47 PM PDT 24 Jun 24 06:32:53 PM PDT 24 2109333269 ps
T70 /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2134734280 Jun 24 06:33:58 PM PDT 24 Jun 24 06:34:04 PM PDT 24 2610391111 ps
T60 /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.1964568301 Jun 24 06:33:19 PM PDT 24 Jun 24 06:33:27 PM PDT 24 2473739351 ps
T211 /workspace/coverage/default/18.sysrst_ctrl_smoke.2071218608 Jun 24 06:33:19 PM PDT 24 Jun 24 06:33:23 PM PDT 24 2123106724 ps
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T59 /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2393043825 Jun 24 06:32:40 PM PDT 24 Jun 24 06:32:52 PM PDT 24 3948582901 ps
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T48 /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.193635072 Jun 24 06:35:14 PM PDT 24 Jun 24 06:36:24 PM PDT 24 108946197327 ps
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T44 /workspace/coverage/default/20.sysrst_ctrl_edge_detect.1442440803 Jun 24 06:33:19 PM PDT 24 Jun 24 06:33:28 PM PDT 24 2845747110 ps
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T51 /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1072975873 Jun 24 06:34:53 PM PDT 24 Jun 24 06:35:02 PM PDT 24 3362068819 ps
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T63 /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.1496086262 Jun 24 06:34:22 PM PDT 24 Jun 24 06:34:29 PM PDT 24 3227073252 ps
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T75 /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.475321806 Jun 24 06:33:28 PM PDT 24 Jun 24 06:33:33 PM PDT 24 9597288361 ps
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T312 /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.1861931363 Jun 24 06:34:11 PM PDT 24 Jun 24 06:34:15 PM PDT 24 2627039681 ps
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T77 /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.4284052254 Jun 24 06:32:36 PM PDT 24 Jun 24 06:32:39 PM PDT 24 7198122804 ps
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T79 /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3114763528 Jun 24 06:34:38 PM PDT 24 Jun 24 06:34:43 PM PDT 24 6793330438 ps
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T379 /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.128997585 Jun 24 06:34:23 PM PDT 24 Jun 24 06:34:35 PM PDT 24 3522589803 ps
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T381 /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.3592124994 Jun 24 06:33:07 PM PDT 24 Jun 24 06:33:10 PM PDT 24 2254173335 ps
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T276 /workspace/coverage/default/4.sysrst_ctrl_sec_cm.2038479805 Jun 24 06:32:34 PM PDT 24 Jun 24 06:33:26 PM PDT 24 42108387587 ps
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T300 /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.89435089 Jun 24 06:34:59 PM PDT 24 Jun 24 06:35:03 PM PDT 24 2471241954 ps
T124 /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.4281109794 Jun 24 06:33:38 PM PDT 24 Jun 24 06:33:42 PM PDT 24 3613649783 ps
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T301 /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.2616158622 Jun 24 06:32:37 PM PDT 24 Jun 24 06:32:40 PM PDT 24 2584311595 ps
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T81 /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.4155651736 Jun 24 06:33:17 PM PDT 24 Jun 24 06:36:32 PM PDT 24 1519243319774 ps
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T384 /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.1870972537 Jun 24 06:33:54 PM PDT 24 Jun 24 06:34:04 PM PDT 24 3275390883 ps
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T389 /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3872583292 Jun 24 06:34:49 PM PDT 24 Jun 24 06:34:58 PM PDT 24 2612959621 ps
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T249 /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.2185366954 Jun 24 06:34:59 PM PDT 24 Jun 24 06:36:31 PM PDT 24 39939883958 ps
T395 /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3559566748 Jun 24 06:34:48 PM PDT 24 Jun 24 06:34:55 PM PDT 24 8121083457 ps
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T397 /workspace/coverage/default/23.sysrst_ctrl_smoke.3270012873 Jun 24 06:33:30 PM PDT 24 Jun 24 06:33:38 PM PDT 24 2110320742 ps
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T398 /workspace/coverage/default/11.sysrst_ctrl_smoke.3605195225 Jun 24 06:32:52 PM PDT 24 Jun 24 06:32:58 PM PDT 24 2118056222 ps
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T100 /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3803182999 Jun 24 06:35:15 PM PDT 24 Jun 24 06:39:35 PM PDT 24 99411158592 ps
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T314 /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.1511629679 Jun 24 06:33:28 PM PDT 24 Jun 24 06:33:33 PM PDT 24 2525649558 ps
T401 /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.1990468854 Jun 24 06:34:20 PM PDT 24 Jun 24 06:34:26 PM PDT 24 2482900531 ps
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T258 /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.4161050609 Jun 24 06:34:29 PM PDT 24 Jun 24 06:34:34 PM PDT 24 2137867821 ps
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T303 /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.1036160675 Jun 24 06:32:49 PM PDT 24 Jun 24 06:32:53 PM PDT 24 3604410599 ps
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T409 /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.1077465400 Jun 24 06:33:56 PM PDT 24 Jun 24 06:34:01 PM PDT 24 4071446061 ps
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T411 /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2853077007 Jun 24 06:33:36 PM PDT 24 Jun 24 06:33:46 PM PDT 24 3429913687 ps
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T159 /workspace/coverage/default/10.sysrst_ctrl_edge_detect.679488141 Jun 24 06:32:53 PM PDT 24 Jun 24 06:33:01 PM PDT 24 3555155241 ps
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T421 /workspace/coverage/default/7.sysrst_ctrl_stress_all.4082903519 Jun 24 06:32:41 PM PDT 24 Jun 24 06:32:52 PM PDT 24 7236606677 ps
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T423 /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3894925408 Jun 24 06:33:36 PM PDT 24 Jun 24 06:33:44 PM PDT 24 2611947712 ps
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T104 /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.589374746 Jun 24 06:34:59 PM PDT 24 Jun 24 06:35:04 PM PDT 24 2991416364 ps
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T136 /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.61394602 Jun 24 06:32:16 PM PDT 24 Jun 24 06:32:20 PM PDT 24 8475766824 ps
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T429 /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.211772782 Jun 24 06:33:47 PM PDT 24 Jun 24 06:33:55 PM PDT 24 2115693981 ps
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T430 /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.562075608 Jun 24 06:32:51 PM PDT 24 Jun 24 06:33:56 PM PDT 24 23318567631 ps
T431 /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1456470978 Jun 24 06:34:31 PM PDT 24 Jun 24 06:34:35 PM PDT 24 2622846298 ps
T432 /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.878316755 Jun 24 06:32:18 PM PDT 24 Jun 24 06:32:23 PM PDT 24 3325829956 ps
T433 /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.2604412668 Jun 24 06:33:53 PM PDT 24 Jun 24 06:33:59 PM PDT 24 2460313409 ps
T86 /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.291171538 Jun 24 06:33:38 PM PDT 24 Jun 24 06:36:11 PM PDT 24 61029195738 ps
T92 /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.1512970481 Jun 24 06:34:01 PM PDT 24 Jun 24 06:35:35 PM PDT 24 141586285933 ps
T434 /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.3348020747 Jun 24 06:34:30 PM PDT 24 Jun 24 06:34:35 PM PDT 24 4168932501 ps
T309 /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.3004560583 Jun 24 06:32:41 PM PDT 24 Jun 24 06:32:45 PM PDT 24 2456124346 ps
T146 /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.481042502 Jun 24 06:32:37 PM PDT 24 Jun 24 06:33:23 PM PDT 24 512086357376 ps
T435 /workspace/coverage/default/5.sysrst_ctrl_smoke.1911247738 Jun 24 06:32:40 PM PDT 24 Jun 24 06:32:45 PM PDT 24 2112897064 ps
T436 /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.1377379840 Jun 24 06:33:35 PM PDT 24 Jun 24 06:33:38 PM PDT 24 2486253409 ps
T160 /workspace/coverage/default/44.sysrst_ctrl_edge_detect.2516828685 Jun 24 06:34:50 PM PDT 24 Jun 24 06:34:58 PM PDT 24 4448893989 ps
T187 /workspace/coverage/default/8.sysrst_ctrl_edge_detect.2016817793 Jun 24 06:32:43 PM PDT 24 Jun 24 06:32:47 PM PDT 24 3006371401 ps
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