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Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_l2h
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_l2h
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_h2l
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_h2l
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_l2h
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_l2h
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_h2l
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_h2l
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_l2h
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_l2h
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_h2l
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_h2l
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_l2h
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_l2h
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_h2l
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_h2l
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_l2h
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_l2h
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_debounce_ctl.debounce_timer
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_debounce_ctl.debounce_timer

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_debounce_ctl.debounce_timer
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.ac_present
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.ac_present

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.ac_present
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.bat_disable
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.bat_disable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.bat_disable
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_in
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_in
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_out
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_out
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_in
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_in
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_out
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_out
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_in
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_in
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_out
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_out
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.lid_open
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.lid_open

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.lid_open
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_in
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_in
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_out
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_out
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.z3_wakeup
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.z3_wakeup

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.z3_wakeup
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_ac_debounce_ctl.ulp_ac_debounce_timer
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_ac_debounce_ctl.ulp_ac_debounce_timer

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_ac_debounce_ctl.ulp_ac_debounce_timer
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_lid_debounce_ctl.ulp_lid_debounce_timer
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_lid_debounce_ctl.ulp_lid_debounce_timer

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_lid_debounce_ctl.ulp_lid_debounce_timer
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_pwrb_debounce_ctl.ulp_pwrb_debounce_timer
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_pwrb_debounce_ctl.ulp_pwrb_debounce_timer

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_pwrb_debounce_ctl.ulp_pwrb_debounce_timer
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2

Go back
Group Instances:
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_l2h
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_h2l
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_l2h
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_h2l
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_l2h
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_h2l
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_l2h
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_h2l
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_l2h
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_debounce_ctl.debounce_timer
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.ac_present
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.bat_disable
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_in
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_out
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_in
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_out
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_in
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_out
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.lid_open
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_in
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_out
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.z3_wakeup
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_1
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_ac_debounce_ctl.ulp_ac_debounce_timer
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_lid_debounce_ctl.ulp_lid_debounce_timer
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_pwrb_debounce_ctl.ulp_pwrb_debounce_timer

Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 227 1 T279 3 T292 3 T327 2
auto[1] 388 1 T3 1 T10 1 T11 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 310 1 T33 1 T284 1 T279 3
auto[1] 336 1 T10 1 T44 1 T73 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 298 1 T33 1 T284 1 T279 2
auto[1] 467 1 T10 1 T44 1 T46 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 292 1 T279 2 T292 2 T293 1
auto[1] 414 1 T10 1 T11 1 T12 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 268 1 T33 1 T284 1 T279 3
auto[1] 423 1 T10 1 T11 1 T12 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 277 1 T279 3 T327 2 T293 2
auto[1] 480 1 T12 1 T44 1 T40 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 260 1 T279 3 T292 1 T327 1
auto[1] 306 1 T3 1 T11 1 T42 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 337 1 T33 1 T279 6 T292 2
auto[1] 420 1 T3 1 T11 1 T12 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 273 1 T33 1 T279 4 T292 1
auto[1] 471 1 T11 1 T44 1 T73 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 415 1 T33 1 T284 1 T285 1
auto[1] 458 1 T31 1 T33 4 T283 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 315 1 T33 1 T284 1 T279 4
auto[1] 2414 1 T21 19 T22 17 T20 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 270 1 T279 2 T327 2 T329 72
auto[1] 2426 1 T21 20 T22 18 T20 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 369 1 T284 1 T279 3 T280 1
auto[1] 2443 1 T21 19 T22 20 T20 15


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 357 1 T284 1 T279 2 T280 1
auto[1] 2428 1 T21 18 T22 20 T20 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 356 1 T284 1 T279 3 T292 1
auto[1] 2455 1 T21 17 T22 19 T20 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 291 1 T285 1 T279 2 T327 2
auto[1] 2487 1 T21 20 T22 20 T20 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 294 1 T284 1 T285 1 T279 4
auto[1] 2429 1 T21 20 T22 20 T20 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 323 1 T279 3 T327 1 T329 54
auto[1] 2355 1 T21 19 T22 20 T20 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 328 1 T285 1 T279 3 T328 6
auto[1] 2438 1 T21 19 T22 20 T20 18


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 342 1 T284 1 T285 1 T279 4
auto[1] 2332 1 T21 20 T22 18 T20 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 323 1 T33 1 T284 1 T285 1
auto[1] 2378 1 T21 18 T22 20 T20 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 323 1 T284 1 T285 1 T279 3
auto[1] 2317 1 T21 20 T22 19 T20 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 330 1 T279 4 T280 1 T293 1
auto[1] 2314 1 T6 20 T23 15 T15 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 282 1 T285 1 T279 4 T280 1
auto[1] 2347 1 T6 19 T23 20 T15 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 302 1 T279 1 T292 1 T327 1
auto[1] 2386 1 T6 18 T23 19 T15 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 274 1 T285 1 T279 5 T292 2
auto[1] 2291 1 T6 18 T23 18 T15 18


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 289 1 T285 1 T279 4 T280 1
auto[1] 2272 1 T6 18 T23 20 T15 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 236 1 T285 1 T279 6 T280 1
auto[1] 2168 1 T6 19 T23 20 T15 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 299 1 T285 1 T279 4 T280 1
auto[1] 2289 1 T6 17 T23 20 T15 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 248 1 T280 1 T292 1 T327 2
auto[1] 2311 1 T6 20 T23 20 T15 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 287 1 T279 4 T292 1 T293 1
auto[1] 2335 1 T6 18 T23 20 T15 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 253 1 T285 1 T279 5 T292 2
auto[1] 2328 1 T6 20 T23 20 T15 18


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 298 1 T285 1 T279 6 T293 1
auto[1] 2199 1 T6 15 T23 19 T15 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 229 1 T279 6 T280 1 T327 1
auto[1] 2358 1 T6 18 T23 18 T15 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 301 1 T279 1 T292 1 T327 1
auto[1] 2271 1 T6 19 T23 20 T15 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 249 1 T285 1 T279 5 T292 1
auto[1] 2294 1 T6 19 T23 19 T15 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 280 1 T279 6 T292 1 T329 52
auto[1] 2282 1 T6 20 T23 20 T15 18


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 235 1 T279 4 T292 2 T327 2
auto[1] 2297 1 T6 14 T23 20 T15 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 416 1 T33 2 T284 1 T285 1
auto[1] 596 1 T24 1 T7 2 T34 3


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 417 1 T33 1 T284 1 T285 1
auto[1] 537 1 T24 1 T7 2 T34 3


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 475 1 T33 1 T285 1 T279 8
auto[1] 553 1 T24 1 T7 2 T34 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%