Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
941 |
1 |
|
|
T6 |
6 |
|
T24 |
9 |
|
T25 |
13 |
| auto[1] |
939 |
1 |
|
|
T6 |
14 |
|
T24 |
11 |
|
T25 |
7 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
924 |
1 |
|
|
T6 |
14 |
|
T24 |
7 |
|
T25 |
13 |
| auto[1] |
956 |
1 |
|
|
T6 |
6 |
|
T24 |
13 |
|
T25 |
7 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
946 |
1 |
|
|
T6 |
9 |
|
T24 |
9 |
|
T25 |
13 |
| auto[1] |
934 |
1 |
|
|
T6 |
11 |
|
T24 |
11 |
|
T25 |
7 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
894 |
1 |
|
|
T6 |
8 |
|
T24 |
5 |
|
T25 |
9 |
| auto[1] |
986 |
1 |
|
|
T6 |
12 |
|
T24 |
15 |
|
T25 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
961 |
1 |
|
|
T6 |
12 |
|
T24 |
11 |
|
T25 |
13 |
| auto[1] |
919 |
1 |
|
|
T6 |
8 |
|
T24 |
9 |
|
T25 |
7 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
941 |
1 |
|
|
T6 |
10 |
|
T24 |
8 |
|
T25 |
7 |
| auto[1] |
939 |
1 |
|
|
T6 |
10 |
|
T24 |
12 |
|
T25 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
933 |
1 |
|
|
T6 |
15 |
|
T24 |
12 |
|
T25 |
15 |
| auto[1] |
947 |
1 |
|
|
T6 |
5 |
|
T24 |
8 |
|
T25 |
5 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
917 |
1 |
|
|
T6 |
13 |
|
T24 |
7 |
|
T25 |
11 |
| auto[1] |
963 |
1 |
|
|
T6 |
7 |
|
T24 |
13 |
|
T25 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
935 |
1 |
|
|
T6 |
11 |
|
T24 |
9 |
|
T25 |
12 |
| auto[1] |
945 |
1 |
|
|
T6 |
9 |
|
T24 |
11 |
|
T25 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
950 |
1 |
|
|
T6 |
9 |
|
T24 |
12 |
|
T25 |
9 |
| auto[1] |
930 |
1 |
|
|
T6 |
11 |
|
T24 |
8 |
|
T25 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
956 |
1 |
|
|
T6 |
7 |
|
T24 |
9 |
|
T25 |
13 |
| auto[1] |
924 |
1 |
|
|
T6 |
13 |
|
T24 |
11 |
|
T25 |
7 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
968 |
1 |
|
|
T6 |
11 |
|
T24 |
9 |
|
T25 |
8 |
| auto[1] |
912 |
1 |
|
|
T6 |
9 |
|
T24 |
11 |
|
T25 |
12 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
944 |
1 |
|
|
T6 |
10 |
|
T24 |
9 |
|
T25 |
10 |
| auto[1] |
936 |
1 |
|
|
T6 |
10 |
|
T24 |
11 |
|
T25 |
10 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
924 |
1 |
|
|
T6 |
14 |
|
T24 |
7 |
|
T25 |
13 |
| auto[1] |
956 |
1 |
|
|
T6 |
6 |
|
T24 |
13 |
|
T25 |
7 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
916 |
1 |
|
|
T6 |
10 |
|
T24 |
7 |
|
T25 |
10 |
| auto[1] |
964 |
1 |
|
|
T6 |
10 |
|
T24 |
13 |
|
T25 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
934 |
1 |
|
|
T6 |
11 |
|
T24 |
9 |
|
T25 |
10 |
| auto[1] |
946 |
1 |
|
|
T6 |
9 |
|
T24 |
11 |
|
T25 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
964 |
1 |
|
|
T6 |
12 |
|
T24 |
9 |
|
T25 |
9 |
| auto[1] |
916 |
1 |
|
|
T6 |
8 |
|
T24 |
11 |
|
T25 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
920 |
1 |
|
|
T6 |
6 |
|
T24 |
12 |
|
T25 |
5 |
| auto[1] |
960 |
1 |
|
|
T6 |
14 |
|
T24 |
8 |
|
T25 |
15 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
948 |
1 |
|
|
T6 |
11 |
|
T24 |
8 |
|
T25 |
10 |
| auto[1] |
932 |
1 |
|
|
T6 |
9 |
|
T24 |
12 |
|
T25 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
966 |
1 |
|
|
T6 |
9 |
|
T24 |
7 |
|
T25 |
12 |
| auto[1] |
914 |
1 |
|
|
T6 |
11 |
|
T24 |
13 |
|
T25 |
8 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
984 |
1 |
|
|
T6 |
10 |
|
T24 |
9 |
|
T25 |
14 |
| auto[1] |
896 |
1 |
|
|
T6 |
10 |
|
T24 |
11 |
|
T25 |
6 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
903 |
1 |
|
|
T6 |
7 |
|
T24 |
14 |
|
T25 |
8 |
| auto[1] |
977 |
1 |
|
|
T6 |
13 |
|
T24 |
6 |
|
T25 |
12 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
935 |
1 |
|
|
T6 |
9 |
|
T24 |
9 |
|
T25 |
8 |
| auto[1] |
945 |
1 |
|
|
T6 |
11 |
|
T24 |
11 |
|
T25 |
12 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
968 |
1 |
|
|
T6 |
11 |
|
T24 |
9 |
|
T25 |
8 |
| auto[1] |
912 |
1 |
|
|
T6 |
9 |
|
T24 |
11 |
|
T25 |
12 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
458 |
1 |
|
|
T6 |
5 |
|
T24 |
3 |
|
T25 |
8 |
| auto[0] |
auto[1] |
458 |
1 |
|
|
T6 |
5 |
|
T24 |
4 |
|
T25 |
2 |
| auto[1] |
auto[0] |
488 |
1 |
|
|
T6 |
4 |
|
T24 |
6 |
|
T25 |
5 |
| auto[1] |
auto[1] |
476 |
1 |
|
|
T6 |
6 |
|
T24 |
7 |
|
T25 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
441 |
1 |
|
|
T6 |
5 |
|
T24 |
2 |
|
T25 |
6 |
| auto[0] |
auto[1] |
493 |
1 |
|
|
T6 |
6 |
|
T24 |
7 |
|
T25 |
4 |
| auto[1] |
auto[0] |
453 |
1 |
|
|
T6 |
3 |
|
T24 |
3 |
|
T25 |
3 |
| auto[1] |
auto[1] |
493 |
1 |
|
|
T6 |
6 |
|
T24 |
8 |
|
T25 |
7 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
491 |
1 |
|
|
T6 |
7 |
|
T24 |
7 |
|
T25 |
6 |
| auto[0] |
auto[1] |
473 |
1 |
|
|
T6 |
5 |
|
T24 |
2 |
|
T25 |
3 |
| auto[1] |
auto[0] |
470 |
1 |
|
|
T6 |
5 |
|
T24 |
4 |
|
T25 |
7 |
| auto[1] |
auto[1] |
446 |
1 |
|
|
T6 |
3 |
|
T24 |
7 |
|
T25 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
459 |
1 |
|
|
T6 |
3 |
|
T24 |
7 |
|
T25 |
1 |
| auto[0] |
auto[1] |
461 |
1 |
|
|
T6 |
3 |
|
T24 |
5 |
|
T25 |
4 |
| auto[1] |
auto[0] |
482 |
1 |
|
|
T6 |
7 |
|
T24 |
1 |
|
T25 |
6 |
| auto[1] |
auto[1] |
478 |
1 |
|
|
T6 |
7 |
|
T24 |
7 |
|
T25 |
9 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
488 |
1 |
|
|
T6 |
8 |
|
T24 |
5 |
|
T25 |
7 |
| auto[0] |
auto[1] |
460 |
1 |
|
|
T6 |
3 |
|
T24 |
3 |
|
T25 |
3 |
| auto[1] |
auto[0] |
445 |
1 |
|
|
T6 |
7 |
|
T24 |
7 |
|
T25 |
8 |
| auto[1] |
auto[1] |
487 |
1 |
|
|
T6 |
2 |
|
T24 |
5 |
|
T25 |
2 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
489 |
1 |
|
|
T6 |
6 |
|
T24 |
2 |
|
T25 |
6 |
| auto[0] |
auto[1] |
477 |
1 |
|
|
T6 |
3 |
|
T24 |
5 |
|
T25 |
6 |
| auto[1] |
auto[0] |
428 |
1 |
|
|
T6 |
7 |
|
T24 |
5 |
|
T25 |
5 |
| auto[1] |
auto[1] |
486 |
1 |
|
|
T6 |
4 |
|
T24 |
8 |
|
T25 |
3 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
446 |
1 |
|
|
T6 |
4 |
|
T24 |
8 |
|
T25 |
5 |
| auto[0] |
auto[1] |
457 |
1 |
|
|
T6 |
3 |
|
T24 |
6 |
|
T25 |
3 |
| auto[1] |
auto[0] |
504 |
1 |
|
|
T6 |
5 |
|
T24 |
4 |
|
T25 |
4 |
| auto[1] |
auto[1] |
473 |
1 |
|
|
T6 |
8 |
|
T24 |
2 |
|
T25 |
8 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
465 |
1 |
|
|
T6 |
4 |
|
T24 |
4 |
|
T25 |
7 |
| auto[0] |
auto[1] |
470 |
1 |
|
|
T6 |
5 |
|
T24 |
5 |
|
T25 |
1 |
| auto[1] |
auto[0] |
491 |
1 |
|
|
T6 |
3 |
|
T24 |
5 |
|
T25 |
6 |
| auto[1] |
auto[1] |
454 |
1 |
|
|
T6 |
8 |
|
T24 |
6 |
|
T25 |
6 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
462 |
1 |
|
|
T6 |
2 |
|
T24 |
5 |
|
T25 |
6 |
| auto[0] |
auto[1] |
482 |
1 |
|
|
T6 |
8 |
|
T24 |
4 |
|
T25 |
4 |
| auto[1] |
auto[0] |
479 |
1 |
|
|
T6 |
4 |
|
T24 |
4 |
|
T25 |
7 |
| auto[1] |
auto[1] |
457 |
1 |
|
|
T6 |
6 |
|
T24 |
7 |
|
T25 |
3 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
924 |
1 |
|
|
T6 |
14 |
|
T24 |
7 |
|
T25 |
13 |
| auto[1] |
auto[1] |
956 |
1 |
|
|
T6 |
6 |
|
T24 |
13 |
|
T25 |
7 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
487 |
1 |
|
|
T6 |
6 |
|
T24 |
4 |
|
T25 |
7 |
| auto[0] |
auto[1] |
497 |
1 |
|
|
T6 |
4 |
|
T24 |
5 |
|
T25 |
7 |
| auto[1] |
auto[0] |
448 |
1 |
|
|
T6 |
5 |
|
T24 |
5 |
|
T25 |
5 |
| auto[1] |
auto[1] |
448 |
1 |
|
|
T6 |
5 |
|
T24 |
6 |
|
T25 |
1 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
968 |
1 |
|
|
T6 |
11 |
|
T24 |
9 |
|
T25 |
8 |
| auto[1] |
auto[1] |
912 |
1 |
|
|
T6 |
9 |
|
T24 |
11 |
|
T25 |
12 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
169 |
1 |
|
|
T26 |
9 |
|
T67 |
12 |
|
T130 |
10 |
| auto[1] |
171 |
1 |
|
|
T26 |
11 |
|
T67 |
8 |
|
T130 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
172 |
1 |
|
|
T26 |
12 |
|
T67 |
10 |
|
T130 |
8 |
| auto[1] |
168 |
1 |
|
|
T26 |
8 |
|
T67 |
10 |
|
T130 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
182 |
1 |
|
|
T26 |
7 |
|
T67 |
10 |
|
T130 |
12 |
| auto[1] |
158 |
1 |
|
|
T26 |
13 |
|
T67 |
10 |
|
T130 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
163 |
1 |
|
|
T26 |
12 |
|
T67 |
11 |
|
T130 |
6 |
| auto[1] |
177 |
1 |
|
|
T26 |
8 |
|
T67 |
9 |
|
T130 |
14 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
178 |
1 |
|
|
T26 |
13 |
|
T67 |
11 |
|
T130 |
9 |
| auto[1] |
162 |
1 |
|
|
T26 |
7 |
|
T67 |
9 |
|
T130 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
162 |
1 |
|
|
T26 |
9 |
|
T67 |
9 |
|
T130 |
9 |
| auto[1] |
178 |
1 |
|
|
T26 |
11 |
|
T67 |
11 |
|
T130 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
177 |
1 |
|
|
T26 |
11 |
|
T67 |
11 |
|
T130 |
7 |
| auto[1] |
163 |
1 |
|
|
T26 |
9 |
|
T67 |
9 |
|
T130 |
13 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
173 |
1 |
|
|
T26 |
7 |
|
T67 |
12 |
|
T130 |
11 |
| auto[1] |
167 |
1 |
|
|
T26 |
13 |
|
T67 |
8 |
|
T130 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
182 |
1 |
|
|
T26 |
14 |
|
T67 |
8 |
|
T130 |
14 |
| auto[1] |
158 |
1 |
|
|
T26 |
6 |
|
T67 |
12 |
|
T130 |
6 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
159 |
1 |
|
|
T26 |
9 |
|
T67 |
9 |
|
T130 |
8 |
| auto[1] |
181 |
1 |
|
|
T26 |
11 |
|
T67 |
11 |
|
T130 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
169 |
1 |
|
|
T26 |
8 |
|
T67 |
13 |
|
T130 |
7 |
| auto[1] |
171 |
1 |
|
|
T26 |
12 |
|
T67 |
7 |
|
T130 |
13 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
158 |
1 |
|
|
T26 |
12 |
|
T67 |
10 |
|
T130 |
11 |
| auto[1] |
182 |
1 |
|
|
T26 |
8 |
|
T67 |
10 |
|
T130 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
170 |
1 |
|
|
T26 |
12 |
|
T67 |
5 |
|
T130 |
15 |
| auto[1] |
170 |
1 |
|
|
T26 |
8 |
|
T67 |
15 |
|
T130 |
5 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
172 |
1 |
|
|
T26 |
12 |
|
T67 |
10 |
|
T130 |
8 |
| auto[1] |
168 |
1 |
|
|
T26 |
8 |
|
T67 |
10 |
|
T130 |
12 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
178 |
1 |
|
|
T26 |
13 |
|
T67 |
8 |
|
T130 |
9 |
| auto[1] |
162 |
1 |
|
|
T26 |
7 |
|
T67 |
12 |
|
T130 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
179 |
1 |
|
|
T26 |
6 |
|
T67 |
7 |
|
T130 |
11 |
| auto[1] |
161 |
1 |
|
|
T26 |
14 |
|
T67 |
13 |
|
T130 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
163 |
1 |
|
|
T26 |
12 |
|
T67 |
8 |
|
T130 |
13 |
| auto[1] |
177 |
1 |
|
|
T26 |
8 |
|
T67 |
12 |
|
T130 |
7 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
175 |
1 |
|
|
T26 |
12 |
|
T67 |
8 |
|
T130 |
9 |
| auto[1] |
165 |
1 |
|
|
T26 |
8 |
|
T67 |
12 |
|
T130 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
160 |
1 |
|
|
T26 |
10 |
|
T67 |
13 |
|
T130 |
8 |
| auto[1] |
180 |
1 |
|
|
T26 |
10 |
|
T67 |
7 |
|
T130 |
12 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
178 |
1 |
|
|
T26 |
6 |
|
T67 |
10 |
|
T130 |
10 |
| auto[1] |
162 |
1 |
|
|
T26 |
14 |
|
T67 |
10 |
|
T130 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
177 |
1 |
|
|
T26 |
13 |
|
T67 |
11 |
|
T130 |
10 |
| auto[1] |
163 |
1 |
|
|
T26 |
7 |
|
T67 |
9 |
|
T130 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
189 |
1 |
|
|
T26 |
11 |
|
T67 |
7 |
|
T130 |
10 |
| auto[1] |
151 |
1 |
|
|
T26 |
9 |
|
T67 |
13 |
|
T130 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
183 |
1 |
|
|
T26 |
12 |
|
T67 |
11 |
|
T130 |
9 |
| auto[1] |
157 |
1 |
|
|
T26 |
8 |
|
T67 |
9 |
|
T130 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
158 |
1 |
|
|
T26 |
12 |
|
T67 |
10 |
|
T130 |
11 |
| auto[1] |
182 |
1 |
|
|
T26 |
8 |
|
T67 |
10 |
|
T130 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
93 |
1 |
|
|
T26 |
3 |
|
T67 |
3 |
|
T130 |
7 |
| auto[0] |
auto[1] |
85 |
1 |
|
|
T26 |
10 |
|
T67 |
5 |
|
T130 |
2 |
| auto[1] |
auto[0] |
89 |
1 |
|
|
T26 |
4 |
|
T67 |
7 |
|
T130 |
5 |
| auto[1] |
auto[1] |
73 |
1 |
|
|
T26 |
3 |
|
T67 |
5 |
|
T130 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
84 |
1 |
|
|
T26 |
2 |
|
T67 |
3 |
|
T130 |
5 |
| auto[0] |
auto[1] |
95 |
1 |
|
|
T26 |
4 |
|
T67 |
4 |
|
T130 |
6 |
| auto[1] |
auto[0] |
79 |
1 |
|
|
T26 |
10 |
|
T67 |
8 |
|
T130 |
1 |
| auto[1] |
auto[1] |
82 |
1 |
|
|
T26 |
4 |
|
T67 |
5 |
|
T130 |
8 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
78 |
1 |
|
|
T26 |
9 |
|
T67 |
3 |
|
T130 |
6 |
| auto[0] |
auto[1] |
85 |
1 |
|
|
T26 |
3 |
|
T67 |
5 |
|
T130 |
7 |
| auto[1] |
auto[0] |
100 |
1 |
|
|
T26 |
4 |
|
T67 |
8 |
|
T130 |
3 |
| auto[1] |
auto[1] |
77 |
1 |
|
|
T26 |
4 |
|
T67 |
4 |
|
T130 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
76 |
1 |
|
|
T26 |
7 |
|
T67 |
2 |
|
T130 |
4 |
| auto[0] |
auto[1] |
99 |
1 |
|
|
T26 |
5 |
|
T67 |
6 |
|
T130 |
5 |
| auto[1] |
auto[0] |
86 |
1 |
|
|
T26 |
2 |
|
T67 |
7 |
|
T130 |
5 |
| auto[1] |
auto[1] |
79 |
1 |
|
|
T26 |
6 |
|
T67 |
5 |
|
T130 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
88 |
1 |
|
|
T26 |
6 |
|
T67 |
6 |
|
T130 |
4 |
| auto[0] |
auto[1] |
72 |
1 |
|
|
T26 |
4 |
|
T67 |
7 |
|
T130 |
4 |
| auto[1] |
auto[0] |
89 |
1 |
|
|
T26 |
5 |
|
T67 |
5 |
|
T130 |
3 |
| auto[1] |
auto[1] |
91 |
1 |
|
|
T26 |
5 |
|
T67 |
2 |
|
T130 |
9 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
95 |
1 |
|
|
T26 |
2 |
|
T67 |
5 |
|
T130 |
7 |
| auto[0] |
auto[1] |
83 |
1 |
|
|
T26 |
4 |
|
T67 |
5 |
|
T130 |
3 |
| auto[1] |
auto[0] |
78 |
1 |
|
|
T26 |
5 |
|
T67 |
7 |
|
T130 |
4 |
| auto[1] |
auto[1] |
84 |
1 |
|
|
T26 |
9 |
|
T67 |
3 |
|
T130 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
84 |
1 |
|
|
T26 |
5 |
|
T67 |
2 |
|
T130 |
4 |
| auto[0] |
auto[1] |
105 |
1 |
|
|
T26 |
6 |
|
T67 |
5 |
|
T130 |
6 |
| auto[1] |
auto[0] |
75 |
1 |
|
|
T26 |
4 |
|
T67 |
7 |
|
T130 |
4 |
| auto[1] |
auto[1] |
76 |
1 |
|
|
T26 |
5 |
|
T67 |
6 |
|
T130 |
6 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
86 |
1 |
|
|
T26 |
5 |
|
T67 |
6 |
|
T130 |
3 |
| auto[0] |
auto[1] |
97 |
1 |
|
|
T26 |
7 |
|
T67 |
5 |
|
T130 |
6 |
| auto[1] |
auto[0] |
83 |
1 |
|
|
T26 |
3 |
|
T67 |
7 |
|
T130 |
4 |
| auto[1] |
auto[1] |
74 |
1 |
|
|
T26 |
5 |
|
T67 |
2 |
|
T130 |
7 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
80 |
1 |
|
|
T26 |
6 |
|
T67 |
1 |
|
T130 |
9 |
| auto[0] |
auto[1] |
90 |
1 |
|
|
T26 |
6 |
|
T67 |
4 |
|
T130 |
6 |
| auto[1] |
auto[0] |
89 |
1 |
|
|
T26 |
3 |
|
T67 |
11 |
|
T130 |
1 |
| auto[1] |
auto[1] |
81 |
1 |
|
|
T26 |
5 |
|
T67 |
4 |
|
T130 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
172 |
1 |
|
|
T26 |
12 |
|
T67 |
10 |
|
T130 |
8 |
| auto[1] |
auto[1] |
168 |
1 |
|
|
T26 |
8 |
|
T67 |
10 |
|
T130 |
12 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
94 |
1 |
|
|
T26 |
8 |
|
T67 |
5 |
|
T130 |
7 |
| auto[0] |
auto[1] |
83 |
1 |
|
|
T26 |
5 |
|
T67 |
6 |
|
T130 |
3 |
| auto[1] |
auto[0] |
88 |
1 |
|
|
T26 |
6 |
|
T67 |
3 |
|
T130 |
7 |
| auto[1] |
auto[1] |
75 |
1 |
|
|
T26 |
1 |
|
T67 |
6 |
|
T130 |
3 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
158 |
1 |
|
|
T26 |
12 |
|
T67 |
10 |
|
T130 |
11 |
| auto[1] |
auto[1] |
182 |
1 |
|
|
T26 |
8 |
|
T67 |
10 |
|
T130 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
59 |
1 |
|
|
T130 |
14 |
|
T179 |
14 |
|
T201 |
11 |
| auto[1] |
41 |
1 |
|
|
T130 |
6 |
|
T179 |
6 |
|
T201 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
51 |
1 |
|
|
T130 |
10 |
|
T179 |
5 |
|
T201 |
16 |
| auto[1] |
49 |
1 |
|
|
T130 |
10 |
|
T179 |
15 |
|
T201 |
4 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
56 |
1 |
|
|
T130 |
14 |
|
T179 |
10 |
|
T201 |
12 |
| auto[1] |
44 |
1 |
|
|
T130 |
6 |
|
T179 |
10 |
|
T201 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
48 |
1 |
|
|
T130 |
13 |
|
T179 |
9 |
|
T201 |
10 |
| auto[1] |
52 |
1 |
|
|
T130 |
7 |
|
T179 |
11 |
|
T201 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
46 |
1 |
|
|
T130 |
7 |
|
T179 |
8 |
|
T201 |
11 |
| auto[1] |
54 |
1 |
|
|
T130 |
13 |
|
T179 |
12 |
|
T201 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
46 |
1 |
|
|
T130 |
10 |
|
T179 |
10 |
|
T201 |
6 |
| auto[1] |
54 |
1 |
|
|
T130 |
10 |
|
T179 |
10 |
|
T201 |
14 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
54 |
1 |
|
|
T130 |
9 |
|
T179 |
12 |
|
T201 |
11 |
| auto[1] |
46 |
1 |
|
|
T130 |
11 |
|
T179 |
8 |
|
T201 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
51 |
1 |
|
|
T130 |
10 |
|
T179 |
14 |
|
T201 |
9 |
| auto[1] |
49 |
1 |
|
|
T130 |
10 |
|
T179 |
6 |
|
T201 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
41 |
1 |
|
|
T130 |
7 |
|
T179 |
9 |
|
T201 |
7 |
| auto[1] |
59 |
1 |
|
|
T130 |
13 |
|
T179 |
11 |
|
T201 |
13 |