Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	1	30	96.77	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1990

1

T4

10

T6

11

T9

3

auto[1]

620

1

T4

7

T2

3

T6

1

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1988

1

T4

10

T6

9

T9

4

auto[1]

622

1

T4

7

T2

3

T6

3

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1927

1

T4

7

T2

2

T6

9

auto[1]

683

1

T4

10

T2

1

T6

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2006

1

T4

17

T2

1

T6

10

auto[1]

604

1

T2

2

T6

2

T10

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2296

1

T4

17

T2

3

T6

11

auto[1]

314

1

T6

1

T12

2

T36

7

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2384

1

T4

17

T2

3

T6

11

auto[1]

226

1

T6

1

T12

2

T36

6

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2411

1

T4

17

T2

3

T6

12

auto[1]

199

1

T71

3

T72

30

T74

4

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2429

1

T4

17

T2

3

T6

11

auto[1]

181

1

T6

1

T9

1

T36

6

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2400

1

T4

17

T2

3

T6

10

auto[1]

210

1

T6

2

T44

1

T72

20

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2010

1

T4

17

T6

11

T9

3

auto[1]

600

1

T2

3

T6

1

T9

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	[auto[1]]	[auto[1]]	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

895

1

T4

17

T2

3

T10

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

137

1

T6

1

T36

4

T71

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

62

1

T6

2

T44

1

T94

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

38

1

T186

9

T372

3

T357

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

65

1

T9

1

T115

9

T251

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T115

3

T253

1

T373

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

14

1

T73

2

T374

1

T231

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

32

1

T97

2

T364

1

T373

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T71

3

T72

10

T255

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

25

1

T72

11

T253

3

T375

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T376

12

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

20

1

T120

1

T181

2

T377

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T375

1

T378

1

T366

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

9

1

T373

1

T372

1

T379

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

70

1

T364

3

T181

5

T380

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

33

1

T12

2

T252

3

T97

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

23

1

T98

2

T254

3

T146

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T73

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

25

1

T6

1

T36

3

T255

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

2

1

T369

2

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

27

1

T115

7

T252

1

T366

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

3

1

T254

2

T368

1

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

14

1

T72

9

T380

1

T357

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

3

1

T74

2

T378

1

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T74

2

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	1	30	96.77	1
Automatically Generated Cross Bins	31	1	30	96.77	1
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Uncovered bins

cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

82

1

T199

13

T252

1

T354

12

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

65

1

T74

2

T375

1

T381

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

82

1

T6

1

T34

4

T35

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

134

1

T72

10

T73

1

T360

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

83

1

T72

9

T115

7

T260

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

65

1

T33

4

T51

6

T71

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

21

1

T97

2

T354

5

T356

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

132

1

T4

10

T255

7

T253

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

93

1

T255

1

T98

2

T354

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

85

1

T36

4

T72

15

T65

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

46

1

T9

1

T36

3

T51

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

54

1

T12

2

T34

4

T35

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T44

1

T261

4

T199

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

20

1

T116

3

T97

1

T264

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T261

1

T277

2

T100

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

120

1

T116

10

T260

12

T199

12

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

73

1

T4

7

T115

9

T120

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

83

1

T250

6

T263

5

T382

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T383

4

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

85

1

T10

2

T72

11

T364

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

15

1

T32

1

T375

3

T384

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

23

1

T35

2

T260

7

T382

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T2

2

T278

1

T385

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

76

1

T6

1

T241

2

T116

8

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T32

1

T73

2

T360

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

20

1

T33

4

T115

3

T360

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

19

1

T2

1

T34

2

T199

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

22

1

T6

2

T33

2

T94

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T386

1

T387

2

T358

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

8

1

T134

1

T367

1

T388

3

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded