Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1279

1

T13

7

T26

12

T55

5

auto[1]

1339

1

T13

13

T26

8

T55

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

636

1

T13

5

T26

4

T55

8

from_0to1

622

1

T13

4

T26

3

T55

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1301

1

T13

9

T26

8

T55

11

auto[1]

1317

1

T13

11

T26

12

T55

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1328

1

T13

11

T26

10

T55

8

auto[1]

1290

1

T13

9

T26

10

T55

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

88

1

T13

1

T26

1

T67

2

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T119

1

T51

1

T39

2

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T55

1

T67

1

T38

1

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T26

1

T55

1

T51

2

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T67

2

T39

2

T193

2

auto[0]

from_0to1

auto[0]

auto[1]

85

1

T55

1

T38

3

T51

1

auto[0]

from_0to1

auto[1]

auto[0]

83

1

T13

1

T26

1

T38

2

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T13

1

T55

1

T39

1

auto[1]

from_1to0

auto[0]

auto[0]

87

1

T13

2

T55

1

T67

1

auto[1]

from_1to0

auto[0]

auto[1]

82

1

T55

2

T67

1

T38

1

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T26

1

T55

2

T38

1

auto[1]

from_1to0

auto[1]

auto[1]

87

1

T13

2

T26

1

T55

1

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T26

1

T55

2

T39

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T13

1

T55

2

T67

4

auto[1]

from_0to1

auto[1]

auto[0]

87

1

T13

1

T26

1

T119

2

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T55

1

T51

2

T172

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1283

1

T13

10

T26

9

T55

11

auto[1]

1335

1

T13

10

T26

11

T55

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

621

1

T13

6

T26

3

T55

4

from_0to1

625

1

T13

6

T26

4

T55

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1293

1

T13

8

T26

8

T55

6

auto[1]

1325

1

T13

12

T26

12

T55

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1346

1

T13

9

T26

11

T55

15

auto[1]

1272

1

T13

11

T26

9

T55

5

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

77

1

T55

1

T172

1

T39

2

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T13

3

T55

1

T67

1

auto[0]

from_1to0

auto[1]

auto[0]

78

1

T55

2

T119

1

T38

1

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T119

2

T38

1

T51

2

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T26

1

T67

1

T119

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T67

1

T38

1

T51

1

auto[0]

from_0to1

auto[1]

auto[0]

78

1

T13

2

T55

1

T42

2

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T67

1

T119

1

T38

3

auto[1]

from_1to0

auto[0]

auto[0]

75

1

T13

1

T67

2

T119

2

auto[1]

from_1to0

auto[0]

auto[1]

79

1

T67

1

T119

1

T38

1

auto[1]

from_1to0

auto[1]

auto[0]

88

1

T26

2

T67

1

T38

1

auto[1]

from_1to0

auto[1]

auto[1]

84

1

T13

2

T26

1

T38

3

auto[1]

from_0to1

auto[0]

auto[0]

96

1

T67

1

T38

1

T39

1

auto[1]

from_0to1

auto[0]

auto[1]

80

1

T13

1

T26

1

T119

1

auto[1]

from_0to1

auto[1]

auto[0]

76

1

T13

1

T55

2

T67

1

auto[1]

from_0to1

auto[1]

auto[1]

90

1

T13

2

T26

2

T119

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1356

1

T13

12

T26

8

T55

11

auto[1]

1262

1

T13

8

T26

12

T55

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

628

1

T13

4

T26

5

T55

4

from_0to1

631

1

T13

5

T26

5

T55

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1322

1

T13

11

T26

9

T55

10

auto[1]

1296

1

T13

9

T26

11

T55

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1307

1

T13

13

T26

10

T55

6

auto[1]

1311

1

T13

7

T26

10

T55

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

92

1

T67

1

T38

1

T51

1

auto[0]

from_1to0

auto[0]

auto[1]

83

1

T13

2

T26

1

T119

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T55

1

T38

1

T39

2

auto[0]

from_1to0

auto[1]

auto[1]

92

1

T26

1

T55

1

T67

1

auto[0]

from_0to1

auto[0]

auto[0]

78

1

T13

2

T26

1

T38

2

auto[0]

from_0to1

auto[0]

auto[1]

100

1

T55

2

T51

1

T172

1

auto[0]

from_0to1

auto[1]

auto[0]

83

1

T13

2

T26

1

T119

1

auto[0]

from_0to1

auto[1]

auto[1]

82

1

T55

2

T67

1

T119

2

auto[1]

from_1to0

auto[0]

auto[0]

86

1

T13

1

T26

2

T38

2

auto[1]

from_1to0

auto[0]

auto[1]

76

1

T119

1

T38

3

T172

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T13

1

T26

1

T55

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T55

1

T119

1

T38

1

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T119

1

T38

2

T51

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T26

1

T119

1

T38

1

auto[1]

from_0to1

auto[1]

auto[0]

76

1

T26

1

T67

1

T172

1

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T13

1

T26

1

T67

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1327

1

T13

10

T26

9

T55

9

auto[1]

1291

1

T13

10

T26

11

T55

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

636

1

T13

4

T26

4

T55

6

from_0to1

639

1

T13

4

T26

5

T55

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1338

1

T13

14

T26

10

T55

9

auto[1]

1280

1

T13

6

T26

10

T55

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1330

1

T13

7

T26

12

T55

12

auto[1]

1288

1

T13

13

T26

8

T55

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

90

1

T26

1

T119

2

T172

1

auto[0]

from_1to0

auto[0]

auto[1]

88

1

T13

1

T55

1

T38

3

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T55

1

T67

2

T38

1

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T13

2

T55

1

T67

1

auto[0]

from_0to1

auto[0]

auto[0]

91

1

T55

1

T67

1

T119

1

auto[0]

from_0to1

auto[0]

auto[1]

85

1

T26

1

T38

1

T51

2

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T26

1

T55

1

T38

2

auto[0]

from_0to1

auto[1]

auto[1]

86

1

T13

1

T26

1

T55

1

auto[1]

from_1to0

auto[0]

auto[0]

86

1

T13

1

T26

1

T38

3

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T26

1

T55

1

T67

2

auto[1]

from_1to0

auto[1]

auto[0]

83

1

T55

1

T119

2

T51

2

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T26

1

T55

1

T38

1

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T38

1

T42

1

T112

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T13

3

T26

1

T119

1

auto[1]

from_0to1

auto[1]

auto[0]

89

1

T55

1

T67

2

T38

2

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T26

1

T55

1

T67

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1376

1

T13

15

T26

10

T55

9

auto[1]

1242

1

T13

5

T26

10

T55

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

607

1

T13

4

T26

5

T55

4

from_0to1

613

1

T13

4

T26

5

T55

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1275

1

T13

8

T26

14

T55

6

auto[1]

1343

1

T13

12

T26

6

T55

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1336

1

T13

12

T26

10

T55

7

auto[1]

1282

1

T13

8

T26

10

T55

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T13

1

T119

1

T38

1

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T26

1

T55

1

T38

1

auto[0]

from_1to0

auto[1]

auto[0]

99

1

T13

1

T119

1

T38

1

auto[0]

from_1to0

auto[1]

auto[1]

83

1

T13

1

T55

1

T38

1

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T13

1

T26

2

T119

2

auto[0]

from_0to1

auto[0]

auto[1]

79

1

T13

1

T26

1

T67

1

auto[0]

from_0to1

auto[1]

auto[0]

88

1

T13

2

T55

1

T38

2

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T55

1

T67

1

T38

1

auto[1]

from_1to0

auto[0]

auto[0]

76

1

T26

1

T55

1

T172

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T26

1

T67

2

T38

3

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T13

1

T26

1

T67

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T26

1

T55

1

T67

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T26

1

T67

1

T51

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T67

1

T119

1

T51

1

auto[1]

from_0to1

auto[1]

auto[0]

95

1

T119

1

T38

1

T51

1

auto[1]

from_0to1

auto[1]

auto[1]

89

1

T26

1

T55

2

T172

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1302

1

T13

9

T26

12

T55

9

auto[1]

1316

1

T13

11

T26

8

T55

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

637

1

T13

4

T26

6

T55

6

from_0to1

638

1

T13

5

T26

6

T55

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1314

1

T13

10

T26

10

T55

10

auto[1]

1304

1

T13

10

T26

10

T55

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1329

1

T13

11

T26

9

T55

11

auto[1]

1289

1

T13

9

T26

11

T55

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

80

1

T55

1

T67

2

T119

2

auto[0]

from_1to0

auto[0]

auto[1]

85

1

T13

1

T26

2

T55

1

auto[0]

from_1to0

auto[1]

auto[0]

80

1

T13

1

T26

1

T55

1

auto[0]

from_1to0

auto[1]

auto[1]

79

1

T26

1

T55

1

T38

1

auto[0]

from_0to1

auto[0]

auto[0]

80

1

T26

1

T55

1

T67

1

auto[0]

from_0to1

auto[0]

auto[1]

76

1

T26

1

T55

1

T67

1

auto[0]

from_0to1

auto[1]

auto[0]

78

1

T13

1

T26

1

T55

1

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T67

1

T119

1

T38

2

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T55

1

T39

1

T86

1

auto[1]

from_1to0

auto[0]

auto[1]

84

1

T26

1

T55

1

T67

1

auto[1]

from_1to0

auto[1]

auto[0]

83

1

T119

1

T38

3

T51

1

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T13

2

T26

1

T119

1

auto[1]

from_0to1

auto[0]

auto[0]

82

1

T55

2

T119

1

T38

3

auto[1]

from_0to1

auto[0]

auto[1]

83

1

T51

1

T39

2

T65

1

auto[1]

from_0to1

auto[1]

auto[0]

93

1

T13

3

T26

2

T119

1

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T13

1

T26

1

T67

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1338

1

T13

8

T26

8

T55

10

auto[1]

1280

1

T13

12

T26

12

T55

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

618

1

T13

4

T26

4

T55

3

from_0to1

616

1

T13

4

T26

5

T55

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1305

1

T13

6

T26

11

T55

12

auto[1]

1313

1

T13

14

T26

9

T55

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1328

1

T13

10

T26

10

T55

8

auto[1]

1290

1

T13

10

T26

10

T55

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

84

1

T26

1

T67

3

T119

2

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T55

2

T38

1

T51

1

auto[0]

from_1to0

auto[1]

auto[0]

87

1

T26

1

T67

1

T119

1

auto[0]

from_1to0

auto[1]

auto[1]

86

1

T13

1

T55

1

T119

1

auto[0]

from_0to1

auto[0]

auto[0]

76

1

T13

1

T26

1

T55

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T26

1

T67

2

T119

1

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T55

1

T119

1

T51

1

auto[0]

from_0to1

auto[1]

auto[1]

78

1

T26

1

T55

1

T119

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T119

1

T38

1

T112

2

auto[1]

from_1to0

auto[0]

auto[1]

81

1

T26

1

T67

1

T39

1

auto[1]

from_1to0

auto[1]

auto[0]

78

1

T13

2

T67

1

T119

1

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T13

1

T26

1

T39

1

auto[1]

from_0to1

auto[0]

auto[0]

85

1

T13

1

T26

1

T67

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T13

1

T172

2

T42

1

auto[1]

from_0to1

auto[1]

auto[0]

84

1

T26

1

T55

1

T67

2

auto[1]

from_0to1

auto[1]

auto[1]

76

1

T13

1

T38

2

T51

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1284

1

T13

11

T26

11

T55

9

auto[1]

1334

1

T13

9

T26

9

T55

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

657

1

T13

6

T26

5

T55

5

from_0to1

642

1

T13

6

T26

4

T55

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1307

1

T13

12

T26

9

T55

11

auto[1]

1311

1

T13

8

T26

11

T55

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1291

1

T13

10

T26

11

T55

8

auto[1]

1327

1

T13

10

T26

9

T55

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T26

1

T67

1

T38

1

auto[0]

from_1to0

auto[0]

auto[1]

79

1

T13

2

T55

2

T119

2

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T13

2

T26

1

T67

1

auto[0]

from_1to0

auto[1]

auto[1]

86

1

T55

1

T39

1

T42

1

auto[0]

from_0to1

auto[0]

auto[0]

96

1

T26

1

T67

1

T119

1

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T119

1

T172

1

T39

1

auto[0]

from_0to1

auto[1]

auto[0]

75

1

T13

1

T55

1

T67

2

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T13

1

T26

1

T55

2

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T55

1

T51

1

T172

1

auto[1]

from_1to0

auto[0]

auto[1]

86

1

T13

1

T26

1

T55

1

auto[1]

from_1to0

auto[1]

auto[0]

81

1

T13

1

T26

1

T38

1

auto[1]

from_1to0

auto[1]

auto[1]

105

1

T26

1

T67

1

T119

1

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T13

1

T55

1

T38

2

auto[1]

from_0to1

auto[0]

auto[1]

82

1

T13

2

T26

1

T38

2

auto[1]

from_0to1

auto[1]

auto[0]

88

1

T13

1

T26

1

T55

1

auto[1]

from_0to1

auto[1]

auto[1]

86

1

T38

2

T172

1

T39

2