Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	163411	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

123961

1

T4

304

T5

23

T1

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	148135	1			T4	396		T5	2		T1	6
values[0x0]	69033	1			T4	78		T5	36		T1	3
values[0x1]	70204	1			T4	133		T5	24		T1	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	132285	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

155087

1

T4

362

T5

26

T1

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1119	1			T4	3		T3	1		T9	2
valid_sources[0x01]	1865	1			T4	3		T9	4		T10	6
valid_sources[0x02]	841	1			T4	1		T26	1		T10	1
valid_sources[0x03]	866	1			T4	3		T16	1		T26	2
valid_sources[0x04]	1290	1			T4	4		T26	2		T10	3
valid_sources[0x05]	1025	1			T4	1		T8	2		T9	2
valid_sources[0x06]	2060	1			T4	2		T9	1		T10	6
valid_sources[0x07]	779	1			T4	4		T9	5		T10	1
valid_sources[0x08]	919	1			T4	3		T26	1		T9	5
valid_sources[0x09]	904	1			T4	3		T7	2		T58	1
valid_sources[0x0a]	1120	1			T4	2		T3	1		T9	7
valid_sources[0x0b]	1008	1			T4	1		T14	1		T9	3
valid_sources[0x0c]	936	1			T4	3		T9	5		T10	4
valid_sources[0x0d]	1590	1			T4	4		T3	1		T9	3
valid_sources[0x0e]	874	1			T14	1		T9	3		T10	4
valid_sources[0x0f]	930	1			T4	1		T26	1		T9	7
valid_sources[0x10]	937	1			T4	2		T9	5		T10	6
valid_sources[0x11]	1876	1			T4	4		T9	5		T10	3
valid_sources[0x12]	1414	1			T4	3		T9	1		T10	3
valid_sources[0x13]	986	1			T4	2		T7	2		T26	1
valid_sources[0x14]	809	1			T4	4		T7	5		T9	1
valid_sources[0x15]	2210	1			T1	1		T9	5		T10	5
valid_sources[0x16]	963	1			T4	3		T7	1		T9	1
valid_sources[0x17]	1167	1			T4	2		T9	3		T10	5
valid_sources[0x18]	898	1			T4	6		T7	1		T17	3
valid_sources[0x19]	869	1			T4	6		T7	1		T9	2
valid_sources[0x1a]	956	1			T4	5		T9	2		T10	6
valid_sources[0x1b]	858	1			T4	3		T9	1		T10	1
valid_sources[0x1c]	1726	1			T4	3		T9	2		T10	3
valid_sources[0x1d]	991	1			T4	3		T9	1		T10	2
valid_sources[0x1e]	1022	1			T4	3		T26	1		T9	6
valid_sources[0x1f]	874	1			T9	1		T10	8		T11	1
valid_sources[0x20]	2266	1			T4	2		T7	1		T10	3
valid_sources[0x21]	988	1			T4	3		T9	3		T34	5
valid_sources[0x22]	1309	1			T4	5		T9	2		T10	4
valid_sources[0x23]	821	1			T4	2		T26	2		T9	3
valid_sources[0x24]	1322	1			T4	2		T7	2		T26	1
valid_sources[0x25]	820	1			T4	2		T26	1		T9	4
valid_sources[0x26]	1430	1			T4	1		T1	1		T9	2
valid_sources[0x27]	738	1			T4	2		T9	2		T10	8
valid_sources[0x28]	2020	1			T4	1		T17	2		T9	3
valid_sources[0x29]	1229	1			T4	2		T9	4		T10	9
valid_sources[0x2a]	874	1			T4	5		T1	2		T16	1
valid_sources[0x2b]	1934	1			T4	1		T26	1		T9	3
valid_sources[0x2c]	903	1			T4	2		T16	2		T9	3
valid_sources[0x2d]	1017	1			T4	1		T14	3		T9	7
valid_sources[0x2e]	937	1			T7	2		T9	7		T10	2
valid_sources[0x2f]	1398	1			T4	6		T9	4		T10	1
valid_sources[0x30]	1546	1			T4	1		T14	1		T9	6
valid_sources[0x31]	979	1			T4	2		T26	1		T9	4
valid_sources[0x32]	1332	1			T4	2		T9	2		T10	5
valid_sources[0x33]	980	1			T4	1		T26	1		T9	2
valid_sources[0x34]	1094	1			T4	3		T26	1		T9	2
valid_sources[0x35]	806	1			T4	3		T26	1		T9	6
valid_sources[0x36]	1074	1			T4	2		T9	2		T27	1
valid_sources[0x37]	898	1			T4	1		T9	2		T10	3
valid_sources[0x38]	1573	1			T9	3		T10	5		T27	1
valid_sources[0x39]	751	1			T4	2		T7	1		T9	5
valid_sources[0x3a]	953	1			T4	3		T26	1		T9	6
valid_sources[0x3b]	874	1			T4	5		T9	4		T10	2
valid_sources[0x3c]	1401	1			T4	3		T9	6		T10	5
valid_sources[0x3d]	794	1			T4	3		T58	1		T26	1
valid_sources[0x3e]	951	1			T4	4		T17	1		T26	4
valid_sources[0x3f]	1127	1			T4	2		T61	2		T26	2
valid_sources[0x40]	755	1			T4	2		T26	3		T9	3
valid_sources[0x41]	886	1			T4	7		T9	6		T10	2
valid_sources[0x42]	924	1			T9	3		T10	3		T27	3
valid_sources[0x43]	999	1			T4	3		T26	2		T10	5
valid_sources[0x44]	1944	1			T4	1		T9	4		T10	3
valid_sources[0x45]	743	1			T4	2		T14	2		T9	7
valid_sources[0x46]	1275	1			T4	2		T14	2		T26	1
valid_sources[0x47]	1031	1			T4	4		T26	2		T9	4
valid_sources[0x48]	1319	1			T4	1		T9	6		T10	2
valid_sources[0x49]	975	1			T4	2		T26	2		T9	2
valid_sources[0x4a]	871	1			T4	2		T9	1		T10	5
valid_sources[0x4b]	900	1			T9	4		T10	2		T34	1
valid_sources[0x4c]	935	1			T7	4		T9	4		T10	3
valid_sources[0x4d]	1674	1			T10	4		T27	1		T55	1
valid_sources[0x4e]	921	1			T26	2		T9	5		T10	5
valid_sources[0x4f]	1109	1			T9	5		T10	1		T34	1
valid_sources[0x50]	2107	1			T9	7		T10	7		T34	1
valid_sources[0x51]	977	1			T4	3		T9	1		T10	3
valid_sources[0x52]	865	1			T4	5		T9	7		T10	4
valid_sources[0x53]	932	1			T4	2		T1	1		T58	1
valid_sources[0x54]	1431	1			T4	2		T15	7		T9	4
valid_sources[0x55]	793	1			T4	1		T26	1		T9	5
valid_sources[0x56]	990	1			T4	3		T9	2		T10	3
valid_sources[0x57]	1214	1			T4	4		T26	1		T9	6
valid_sources[0x58]	911	1			T4	8		T10	2		T36	1
valid_sources[0x59]	853	1			T4	4		T8	1		T9	5
valid_sources[0x5a]	936	1			T4	1		T7	1		T8	2
valid_sources[0x5b]	1682	1			T4	3		T26	1		T9	4
valid_sources[0x5c]	893	1			T4	3		T7	1		T58	1
valid_sources[0x5d]	846	1			T4	3		T3	1		T9	5
valid_sources[0x5e]	870	1			T4	1		T9	2		T10	6
valid_sources[0x5f]	943	1			T4	2		T9	3		T10	5
valid_sources[0x60]	1807	1			T4	2		T7	4		T58	1
valid_sources[0x61]	877	1			T4	5		T9	3		T10	4
valid_sources[0x62]	1165	1			T4	1		T13	123		T26	2
valid_sources[0x63]	1462	1			T3	5		T26	1		T9	1
valid_sources[0x64]	829	1			T26	1		T9	5		T10	2
valid_sources[0x65]	1677	1			T4	2		T9	2		T10	4
valid_sources[0x66]	881	1			T4	3		T26	3		T9	1
valid_sources[0x67]	930	1			T4	5		T9	4		T10	4
valid_sources[0x68]	1468	1			T4	4		T26	1		T9	4
valid_sources[0x69]	952	1			T4	2		T14	2		T9	4
valid_sources[0x6a]	1352	1			T4	4		T9	8		T10	2
valid_sources[0x6b]	1075	1			T4	7		T9	7		T10	5
valid_sources[0x6c]	1592	1			T1	1		T9	6		T10	5
valid_sources[0x6d]	1162	1			T4	3		T9	4		T10	7
valid_sources[0x6e]	1100	1			T7	1		T9	2		T10	4
valid_sources[0x6f]	851	1			T4	3		T9	5		T10	2
valid_sources[0x70]	950	1			T4	2		T26	1		T9	1
valid_sources[0x71]	1159	1			T4	3		T9	2		T10	6
valid_sources[0x72]	910	1			T4	1		T9	2		T10	3
valid_sources[0x73]	1084	1			T4	3		T1	1		T26	1
valid_sources[0x74]	844	1			T4	4		T7	2		T9	5
valid_sources[0x75]	981	1			T26	1		T9	9		T10	3
valid_sources[0x76]	813	1			T4	2		T7	2		T26	1
valid_sources[0x77]	998	1			T4	3		T9	7		T10	7
valid_sources[0x78]	2367	1			T9	3		T10	4		T27	3
valid_sources[0x79]	1016	1			T4	1		T58	1		T26	1
valid_sources[0x7a]	978	1			T4	4		T9	3		T10	6
valid_sources[0x7b]	1169	1			T4	3		T9	2		T10	1
valid_sources[0x7c]	1509	1			T4	2		T26	1		T9	4
valid_sources[0x7d]	917	1			T4	3		T9	4		T10	5
valid_sources[0x7e]	1224	1			T4	1		T9	4		T10	6
valid_sources[0x7f]	822	1			T4	1		T9	2		T10	5
valid_sources[0x80]	1205	1			T4	3		T9	5		T10	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

66640

1

T4

199

T5

1

T1

2

values[0x0]

all_enables

biggest_size

33508

1

T4

42

T5

19

T1

2

values[0x1]

all_enables

biggest_size

23813

1

T4

63

T5

3

T2

11