Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sysrst_ctrl_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sysrst_ctrl_csr_assert 100.00 100.00


Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.02 100.00 96.08 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 36 36 100.00 36 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 36 36 100.00 36 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 1288412574 9060 0 0
auto_block_debounce_ctl_rd_A 1288412574 1770 0 0
auto_block_out_ctl_rd_A 1288412574 2810 0 0
com_det_ctl_0_rd_A 1288412574 4165 0 0
com_det_ctl_1_rd_A 1288412574 4088 0 0
com_det_ctl_2_rd_A 1288412574 4206 0 0
com_det_ctl_3_rd_A 1288412574 4086 0 0
com_out_ctl_0_rd_A 1288412574 5003 0 0
com_out_ctl_1_rd_A 1288412574 4734 0 0
com_out_ctl_2_rd_A 1288412574 4898 0 0
com_out_ctl_3_rd_A 1288412574 4907 0 0
com_pre_det_ctl_0_rd_A 1288412574 1252 0 0
com_pre_det_ctl_1_rd_A 1288412574 1302 0 0
com_pre_det_ctl_2_rd_A 1288412574 1240 0 0
com_pre_det_ctl_3_rd_A 1288412574 1329 0 0
com_pre_sel_ctl_0_rd_A 1288412574 5052 0 0
com_pre_sel_ctl_1_rd_A 1288412574 5410 0 0
com_pre_sel_ctl_2_rd_A 1288412574 5037 0 0
com_pre_sel_ctl_3_rd_A 1288412574 5129 0 0
com_sel_ctl_0_rd_A 1288412574 5540 0 0
com_sel_ctl_1_rd_A 1288412574 5201 0 0
com_sel_ctl_2_rd_A 1288412574 5531 0 0
com_sel_ctl_3_rd_A 1288412574 5294 0 0
ec_rst_ctl_rd_A 1288412574 2299 0 0
intr_enable_rd_A 1288412574 1867 0 0
key_intr_ctl_rd_A 1288412574 4706 0 0
key_intr_debounce_ctl_rd_A 1288412574 1285 0 0
key_invert_ctl_rd_A 1288412574 6227 0 0
pin_allowed_ctl_rd_A 1288412574 6758 0 0
pin_out_ctl_rd_A 1288412574 5449 0 0
pin_out_value_rd_A 1288412574 5327 0 0
regwen_rd_A 1288412574 1618 0 0
ulp_ac_debounce_ctl_rd_A 1288412574 1330 0 0
ulp_ctl_rd_A 1288412574 1397 0 0
ulp_lid_debounce_ctl_rd_A 1288412574 1240 0 0
ulp_pwrb_debounce_ctl_rd_A 1288412574 1498 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 9060 0 0
T10 793027 12 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 9 0 0
T32 0 4 0 0
T34 509676 0 0 0
T38 0 7 0 0
T39 0 20 0 0
T41 0 9 0 0
T42 0 8 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 3 0 0
T86 0 11 0 0
T315 0 4 0 0

auto_block_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 1770 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 13 0 0
T34 509676 0 0 0
T36 904682 0 0 0
T47 0 18 0 0
T51 0 4 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 29 0 0
T88 0 4 0 0
T117 0 9 0 0
T154 0 10 0 0
T207 0 6 0 0
T315 0 6 0 0
T316 0 7 0 0

auto_block_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 2810 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 12 0 0
T34 509676 0 0 0
T36 904682 0 0 0
T47 0 14 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 38 0 0
T88 0 10 0 0
T117 0 6 0 0
T154 0 6 0 0
T207 0 16 0 0
T313 0 7 0 0
T315 0 2 0 0
T316 0 9 0 0

com_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 4165 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 18 0 0
T34 509676 0 0 0
T35 0 46 0 0
T36 904682 47 0 0
T45 0 21 0 0
T51 0 34 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 16 0 0
T71 0 51 0 0
T115 0 73 0 0
T120 0 40 0 0
T315 0 3 0 0

com_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 4088 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 5 0 0
T34 509676 0 0 0
T35 0 49 0 0
T36 904682 32 0 0
T45 0 25 0 0
T51 0 47 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 12 0 0
T71 0 51 0 0
T115 0 64 0 0
T120 0 40 0 0
T315 0 10 0 0

com_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 4206 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 6 0 0
T34 509676 0 0 0
T35 0 34 0 0
T36 904682 28 0 0
T45 0 37 0 0
T51 0 47 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 18 0 0
T71 0 45 0 0
T115 0 68 0 0
T120 0 28 0 0
T315 0 17 0 0

com_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 4086 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 13 0 0
T34 509676 0 0 0
T35 0 42 0 0
T36 904682 38 0 0
T45 0 32 0 0
T51 0 32 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 34 0 0
T71 0 39 0 0
T115 0 68 0 0
T120 0 27 0 0
T250 0 45 0 0

com_out_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 5003 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 5 0 0
T34 509676 0 0 0
T35 0 46 0 0
T36 904682 32 0 0
T45 0 45 0 0
T51 0 23 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 13 0 0
T71 0 63 0 0
T115 0 71 0 0
T120 0 25 0 0
T315 0 3 0 0

com_out_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 4734 0 0
T25 39718 0 0 0
T28 58600 0 0 0
T35 0 29 0 0
T36 904682 39 0 0
T41 181009 0 0 0
T45 0 42 0 0
T51 0 23 0 0
T62 59201 0 0 0
T63 62158 0 0 0
T65 0 15 0 0
T71 0 55 0 0
T115 0 68 0 0
T120 0 42 0 0
T196 202641 0 0 0
T250 0 40 0 0
T297 128882 0 0 0
T315 0 9 0 0
T317 99488 0 0 0
T318 52925 0 0 0

com_out_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 4898 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 9 0 0
T34 509676 0 0 0
T35 0 68 0 0
T36 904682 36 0 0
T45 0 51 0 0
T51 0 30 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 21 0 0
T71 0 40 0 0
T115 0 71 0 0
T120 0 40 0 0
T315 0 10 0 0

com_out_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 4907 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 7 0 0
T34 509676 0 0 0
T35 0 32 0 0
T36 904682 39 0 0
T45 0 18 0 0
T51 0 39 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 28 0 0
T71 0 67 0 0
T115 0 85 0 0
T120 0 21 0 0
T315 0 5 0 0

com_pre_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 1252 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 21 0 0
T34 509676 0 0 0
T36 904682 0 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 9 0 0
T83 0 17 0 0
T88 0 13 0 0
T154 0 21 0 0
T173 0 8 0 0
T256 0 9 0 0
T264 0 20 0 0
T315 0 4 0 0
T319 0 29 0 0

com_pre_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 1302 0 0
T29 0 6 0 0
T30 0 10 0 0
T57 0 8 0 0
T65 130165 16 0 0
T73 724626 0 0 0
T74 207107 0 0 0
T80 152762 0 0 0
T83 0 2 0 0
T114 48711 0 0 0
T115 236197 0 0 0
T154 0 2 0 0
T160 100677 0 0 0
T173 0 3 0 0
T192 48600 0 0 0
T193 18192 0 0 0
T240 102996 0 0 0
T256 0 12 0 0
T264 0 24 0 0
T319 0 29 0 0

com_pre_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 1240 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 15 0 0
T29 0 2 0 0
T34 509676 0 0 0
T36 904682 0 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 2 0 0
T83 0 12 0 0
T88 0 14 0 0
T154 0 15 0 0
T256 0 3 0 0
T264 0 22 0 0
T315 0 2 0 0
T319 0 24 0 0

com_pre_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 1329 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 4 0 0
T29 0 8 0 0
T30 0 2 0 0
T34 509676 0 0 0
T36 904682 0 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 17 0 0
T83 0 11 0 0
T88 0 14 0 0
T173 0 5 0 0
T256 0 8 0 0
T264 0 18 0 0
T319 0 21 0 0

com_pre_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 5052 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 4 0 0
T34 509676 0 0 0
T35 0 44 0 0
T36 904682 43 0 0
T45 0 43 0 0
T51 0 67 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 15 0 0
T71 0 69 0 0
T115 0 53 0 0
T120 0 31 0 0
T315 0 1 0 0

com_pre_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 5410 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 6 0 0
T34 509676 0 0 0
T35 0 42 0 0
T36 904682 32 0 0
T45 0 26 0 0
T51 0 38 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 13 0 0
T71 0 55 0 0
T115 0 87 0 0
T120 0 46 0 0
T315 0 5 0 0

com_pre_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 5037 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 13 0 0
T34 509676 0 0 0
T35 0 45 0 0
T36 904682 39 0 0
T45 0 37 0 0
T51 0 57 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 20 0 0
T71 0 58 0 0
T115 0 63 0 0
T120 0 31 0 0
T315 0 8 0 0

com_pre_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 5129 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 16 0 0
T34 509676 0 0 0
T35 0 48 0 0
T36 904682 38 0 0
T45 0 27 0 0
T51 0 43 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 17 0 0
T71 0 60 0 0
T115 0 78 0 0
T120 0 30 0 0
T315 0 3 0 0

com_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 5540 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 6 0 0
T34 509676 0 0 0
T35 0 53 0 0
T36 904682 41 0 0
T45 0 33 0 0
T51 0 38 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 28 0 0
T71 0 51 0 0
T115 0 83 0 0
T120 0 27 0 0
T250 0 45 0 0

com_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 5201 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 17 0 0
T34 509676 0 0 0
T35 0 45 0 0
T36 904682 29 0 0
T45 0 46 0 0
T51 0 43 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 13 0 0
T71 0 29 0 0
T115 0 51 0 0
T120 0 30 0 0
T315 0 5 0 0

com_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 5531 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 16 0 0
T34 509676 0 0 0
T35 0 51 0 0
T36 904682 26 0 0
T45 0 33 0 0
T51 0 72 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 28 0 0
T71 0 47 0 0
T115 0 57 0 0
T120 0 35 0 0
T315 0 1 0 0

com_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 5294 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 10 0 0
T34 509676 0 0 0
T35 0 28 0 0
T36 904682 41 0 0
T45 0 48 0 0
T51 0 32 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 20 0 0
T71 0 30 0 0
T115 0 62 0 0
T120 0 41 0 0
T315 0 2 0 0

ec_rst_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 2299 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 8 0 0
T34 509676 0 0 0
T35 0 35 0 0
T36 904682 6 0 0
T51 0 4 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 18 0 0
T71 0 17 0 0
T95 0 2 0 0
T115 0 15 0 0
T242 0 1 0 0
T315 0 18 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 1867 0 0
T65 130165 5 0 0
T73 724626 0 0 0
T74 207107 0 0 0
T80 152762 0 0 0
T83 0 51 0 0
T88 0 28 0 0
T114 48711 0 0 0
T115 236197 0 0 0
T154 0 14 0 0
T160 100677 0 0 0
T173 0 23 0 0
T192 48600 0 0 0
T193 18192 0 0 0
T240 102996 0 0 0
T256 0 24 0 0
T264 0 33 0 0
T278 0 14 0 0
T313 0 16 0 0
T315 0 2 0 0

key_intr_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 4706 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 2 0 0
T34 509676 0 0 0
T36 904682 0 0 0
T43 0 1 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 15 0 0
T88 0 11 0 0
T154 0 20 0 0
T173 0 14 0 0
T176 0 3 0 0
T264 0 31 0 0
T315 0 1 0 0
T320 0 8 0 0

key_intr_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 1285 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 10 0 0
T34 509676 0 0 0
T36 904682 0 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 5 0 0
T83 0 18 0 0
T88 0 4 0 0
T154 0 14 0 0
T173 0 1 0 0
T256 0 15 0 0
T264 0 25 0 0
T315 0 9 0 0
T319 0 14 0 0

key_invert_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 6227 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 62 0 0
T27 824624 7 0 0
T34 509676 0 0 0
T36 904682 0 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 131 0 0
T88 0 218 0 0
T154 0 4 0 0
T321 0 58 0 0
T322 0 69 0 0
T323 0 63 0 0
T324 0 56 0 0
T325 0 61 0 0

pin_allowed_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 6758 0 0
T3 227880 0 0 0
T6 712271 0 0 0
T7 224617 0 0 0
T13 251036 45 0 0
T14 77097 0 0 0
T15 59147 0 0 0
T16 198488 0 0 0
T17 22616 0 0 0
T27 0 14 0 0
T51 0 50 0 0
T58 48862 0 0 0
T61 175274 0 0 0
T65 0 143 0 0
T112 0 47 0 0
T119 0 58 0 0
T154 0 25 0 0
T205 0 58 0 0
T315 0 11 0 0
T326 0 71 0 0

pin_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 5449 0 0
T3 227880 0 0 0
T6 712271 0 0 0
T7 224617 0 0 0
T13 251036 67 0 0
T14 77097 0 0 0
T15 59147 0 0 0
T16 198488 0 0 0
T17 22616 0 0 0
T27 0 9 0 0
T51 0 52 0 0
T58 48862 0 0 0
T61 175274 0 0 0
T65 0 158 0 0
T112 0 29 0 0
T119 0 65 0 0
T154 0 7 0 0
T205 0 24 0 0
T315 0 7 0 0
T326 0 76 0 0

pin_out_value_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 5327 0 0
T3 227880 0 0 0
T6 712271 0 0 0
T7 224617 0 0 0
T13 251036 29 0 0
T14 77097 0 0 0
T15 59147 0 0 0
T16 198488 0 0 0
T17 22616 0 0 0
T27 0 10 0 0
T51 0 63 0 0
T58 48862 0 0 0
T61 175274 0 0 0
T65 0 137 0 0
T88 0 14 0 0
T112 0 44 0 0
T119 0 83 0 0
T154 0 15 0 0
T205 0 56 0 0
T326 0 61 0 0

regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 1618 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T24 62224 0 0 0
T27 824624 5 0 0
T34 509676 0 0 0
T36 904682 0 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T65 0 10 0 0
T83 0 5 0 0
T88 0 2 0 0
T154 0 14 0 0
T173 0 3 0 0
T256 0 12 0 0
T264 0 34 0 0
T315 0 7 0 0
T319 0 28 0 0

ulp_ac_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 1330 0 0
T3 227880 8 0 0
T6 712271 0 0 0
T7 224617 0 0 0
T8 234183 0 0 0
T15 59147 0 0 0
T16 198488 0 0 0
T17 22616 0 0 0
T23 0 9 0 0
T26 35529 0 0 0
T27 0 12 0 0
T58 48862 0 0 0
T59 0 10 0 0
T61 175274 0 0 0
T65 0 5 0 0
T76 0 1 0 0
T77 0 3 0 0
T88 0 24 0 0
T154 0 10 0 0
T315 0 7 0 0

ulp_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 1397 0 0
T11 118028 0 0 0
T12 750677 0 0 0
T23 0 8 0 0
T24 62224 0 0 0
T27 824624 9 0 0
T34 509676 0 0 0
T36 904682 0 0 0
T53 351363 0 0 0
T54 206905 0 0 0
T55 123471 0 0 0
T56 207151 0 0 0
T59 0 11 0 0
T65 0 17 0 0
T77 0 5 0 0
T88 0 10 0 0
T154 0 10 0 0
T173 0 3 0 0
T264 0 31 0 0
T315 0 7 0 0

ulp_lid_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 1240 0 0
T3 227880 9 0 0
T6 712271 0 0 0
T7 224617 0 0 0
T8 234183 0 0 0
T15 59147 0 0 0
T16 198488 0 0 0
T17 22616 0 0 0
T23 0 13 0 0
T26 35529 0 0 0
T27 0 1 0 0
T58 48862 0 0 0
T59 0 6 0 0
T60 0 3 0 0
T61 175274 0 0 0
T65 0 9 0 0
T76 0 1 0 0
T77 0 3 0 0
T154 0 10 0 0
T315 0 2 0 0

ulp_pwrb_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1288412574 1498 0 0
T3 227880 6 0 0
T6 712271 0 0 0
T7 224617 0 0 0
T8 234183 0 0 0
T15 59147 0 0 0
T16 198488 0 0 0
T17 22616 0 0 0
T23 0 16 0 0
T26 35529 0 0 0
T27 0 8 0 0
T58 48862 0 0 0
T59 0 13 0 0
T60 0 7 0 0
T61 175274 0 0 0
T65 0 10 0 0
T76 0 4 0 0
T77 0 10 0 0
T88 0 9 0 0
T154 0 18 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%