Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T3
1	0	Covered	T4,T2,T3
1	1	Covered	T3,T7,T59

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T3
1	0	Covered	T3,T7,T59
1	1	Covered	T4,T2,T3

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	241695	0	0
SrcPulseCheck_M	2147483647	243550	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	241695
T1	2101216	0
T2	2029520	48
T3	1830632	0
T4	3395368	224
T5	1881792	0
T6	6524399	51
T7	2031761	0
T9	0	34
T10	1978146	38
T11	717802	0
T12	1514408	17
T13	2012304	0
T14	620112	0
T15	536099	5
T16	198488	0
T24	125442	0
T27	1655170	16
T28	0	12
T32	0	46
T34	1060124	128
T36	0	17
T44	0	26
T45	0	1
T46	0	16
T47	0	16
T48	0	16
T49	0	14
T50	0	1
T51	0	14
T52	0	14
T53	1264908	0
T54	414654	0
T55	247948	0
T56	415164	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	243550
T1	2101216	0
T2	2029520	48
T3	1830632	0
T4	3395368	224
T5	1881792	0
T6	5826373	51
T7	1808420	0
T9	0	34
T10	1978146	38
T11	717802	0
T12	1514408	17
T13	2012304	0
T14	620112	0
T15	477424	5
T16	405	0
T24	125442	0
T27	1655170	16
T28	0	12
T32	0	46
T34	1060124	128
T36	0	17
T44	0	26
T45	0	1
T46	0	16
T47	0	16
T48	0	16
T49	0	14
T50	0	1
T51	0	14
T52	0	14
T53	1264908	0
T54	414654	0
T55	247948	0
T56	415164	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T15
1	0	Covered	T4,T2,T15
1	1	Covered	T30,T31,T291

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T15
1	0	Covered	T30,T31,T291
1	1	Covered	T4,T2,T15

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	2056	0	0
SrcPulseCheck_M	1288412574	2110	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	2056
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	3
T7	1276	0
T9	0	2
T10	0	5
T12	0	1
T13	502	0
T14	417	0
T15	472	1
T27	0	1
T34	0	8
T53	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	2110
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	3
T7	224617	0
T9	0	2
T10	0	5
T12	0	1
T13	251036	0
T14	77097	0
T15	59147	1
T27	0	1
T34	0	8
T53	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T15
1	0	Covered	T4,T2,T15
1	1	Covered	T30,T31,T291

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T15
1	0	Covered	T30,T31,T291
1	1	Covered	T4,T2,T15

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	2098	0	0
SrcPulseCheck_M	8975355	2098	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	2098
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	3
T7	224617	0
T9	0	2
T10	0	5
T12	0	1
T13	251036	0
T14	77097	0
T15	59147	1
T27	0	1
T34	0	8
T53	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	2098
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	3
T7	1276	0
T9	0	2
T10	0	5
T12	0	1
T13	502	0
T14	417	0
T15	472	1
T27	0	1
T34	0	8
T53	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T10
1	0	Covered	T3,T7,T10
1	1	Covered	T3,T7,T59

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T10
1	0	Covered	T3,T7,T59
1	1	Covered	T3,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	1091	0	0
SrcPulseCheck_M	1288412574	1145	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	1091
T3	949	2
T6	14245	0
T7	1276	3
T8	561	0
T10	0	1
T15	472	0
T16	405	0
T17	410	0
T23	0	3
T26	507	0
T27	0	1
T32	0	1
T38	0	2
T39	0	1
T58	407	0
T59	0	3
T60	0	1
T61	422	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	1145
T3	227880	2
T6	712271	0
T7	224617	3
T8	234183	0
T10	0	1
T15	59147	0
T16	198488	0
T17	22616	0
T23	0	3
T26	35529	0
T27	0	1
T32	0	1
T38	0	2
T39	0	1
T58	48862	0
T59	0	3
T60	0	1
T61	175274	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T10
1	0	Covered	T3,T7,T10
1	1	Covered	T3,T7,T59

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T10
1	0	Covered	T3,T7,T59
1	1	Covered	T3,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	1133	0	0
SrcPulseCheck_M	8975355	1133	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	1133
T3	227880	2
T6	712271	0
T7	224617	3
T8	234183	0
T10	0	1
T15	59147	0
T16	198488	0
T17	22616	0
T23	0	3
T26	35529	0
T27	0	1
T32	0	1
T38	0	2
T39	0	1
T58	48862	0
T59	0	3
T60	0	1
T61	175274	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	1133
T3	949	2
T6	14245	0
T7	1276	3
T8	561	0
T10	0	1
T15	472	0
T16	405	0
T17	410	0
T23	0	3
T26	507	0
T27	0	1
T32	0	1
T38	0	2
T39	0	1
T58	407	0
T59	0	3
T60	0	1
T61	422	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T10
1	0	Covered	T3,T7,T10
1	1	Covered	T3,T7,T59

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T10
1	0	Covered	T3,T7,T59
1	1	Covered	T3,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	1083	0	0
SrcPulseCheck_M	1288412574	1135	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	1083
T3	949	2
T6	14245	0
T7	1276	3
T8	561	0
T10	0	1
T15	472	0
T16	405	0
T17	410	0
T23	0	3
T26	507	0
T27	0	1
T32	0	1
T38	0	2
T39	0	1
T58	407	0
T59	0	3
T60	0	1
T61	422	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	1135
T3	227880	2
T6	712271	0
T7	224617	3
T8	234183	0
T10	0	1
T15	59147	0
T16	198488	0
T17	22616	0
T23	0	3
T26	35529	0
T27	0	1
T32	0	1
T38	0	2
T39	0	1
T58	48862	0
T59	0	3
T60	0	1
T61	175274	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T10
1	0	Covered	T3,T7,T10
1	1	Covered	T3,T7,T59

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T10
1	0	Covered	T3,T7,T59
1	1	Covered	T3,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	1127	0	0
SrcPulseCheck_M	8975355	1127	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	1127
T3	227880	2
T6	712271	0
T7	224617	3
T8	234183	0
T10	0	1
T15	59147	0
T16	198488	0
T17	22616	0
T23	0	3
T26	35529	0
T27	0	1
T32	0	1
T38	0	2
T39	0	1
T58	48862	0
T59	0	3
T60	0	1
T61	175274	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	1127
T3	949	2
T6	14245	0
T7	1276	3
T8	561	0
T10	0	1
T15	472	0
T16	405	0
T17	410	0
T23	0	3
T26	507	0
T27	0	1
T32	0	1
T38	0	2
T39	0	1
T58	407	0
T59	0	3
T60	0	1
T61	422	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T10
1	0	Covered	T3,T7,T10
1	1	Covered	T3,T7,T59

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T10
1	0	Covered	T3,T7,T59
1	1	Covered	T3,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	1089	0	0
SrcPulseCheck_M	1288412574	1142	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	1089
T3	949	2
T6	14245	0
T7	1276	3
T8	561	0
T10	0	1
T15	472	0
T16	405	0
T17	410	0
T23	0	3
T26	507	0
T27	0	1
T32	0	1
T38	0	2
T39	0	1
T58	407	0
T59	0	3
T60	0	1
T61	422	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	1142
T3	227880	2
T6	712271	0
T7	224617	3
T8	234183	0
T10	0	1
T15	59147	0
T16	198488	0
T17	22616	0
T23	0	3
T26	35529	0
T27	0	1
T32	0	1
T38	0	2
T39	0	1
T58	48862	0
T59	0	3
T60	0	1
T61	175274	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T10
1	0	Covered	T3,T7,T10
1	1	Covered	T3,T7,T59

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T10
1	0	Covered	T3,T7,T59
1	1	Covered	T3,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	1131	0	0
SrcPulseCheck_M	8975355	1131	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	1131
T3	227880	2
T6	712271	0
T7	224617	3
T8	234183	0
T10	0	1
T15	59147	0
T16	198488	0
T17	22616	0
T23	0	3
T26	35529	0
T27	0	1
T32	0	1
T38	0	2
T39	0	1
T58	48862	0
T59	0	3
T60	0	1
T61	175274	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	1131
T3	949	2
T6	14245	0
T7	1276	3
T8	561	0
T10	0	1
T15	472	0
T16	405	0
T17	410	0
T23	0	3
T26	507	0
T27	0	1
T32	0	1
T38	0	2
T39	0	1
T58	407	0
T59	0	3
T60	0	1
T61	422	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T23
1	0	Covered	T3,T7,T23
1	1	Covered	T3,T7,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T23
1	0	Covered	T3,T7,T23
1	1	Covered	T3,T7,T23

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	1082	0	0
SrcPulseCheck_M	1288412574	1137	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	1082
T3	949	2
T6	14245	0
T7	1276	6
T8	561	0
T15	472	0
T16	405	0
T17	410	0
T23	0	2
T26	507	0
T38	0	2
T42	0	2
T58	407	0
T60	0	2
T61	422	0
T65	0	2
T75	0	4
T76	0	2
T77	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	1137
T3	227880	2
T6	712271	0
T7	224617	6
T8	234183	0
T15	59147	0
T16	198488	0
T17	22616	0
T23	0	2
T26	35529	0
T38	0	2
T42	0	2
T58	48862	0
T60	0	2
T61	175274	0
T65	0	2
T75	0	4
T76	0	2
T77	0	4

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T23
1	0	Covered	T3,T7,T23
1	1	Covered	T3,T7,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T23
1	0	Covered	T3,T7,T23
1	1	Covered	T3,T7,T23

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	1125	0	0
SrcPulseCheck_M	8975355	1125	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	1125
T3	227880	2
T6	712271	0
T7	224617	6
T8	234183	0
T15	59147	0
T16	198488	0
T17	22616	0
T23	0	2
T26	35529	0
T38	0	2
T42	0	2
T58	48862	0
T60	0	2
T61	175274	0
T65	0	2
T75	0	4
T76	0	2
T77	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	1125
T3	949	2
T6	14245	0
T7	1276	6
T8	561	0
T15	472	0
T16	405	0
T17	410	0
T23	0	2
T26	507	0
T38	0	2
T42	0	2
T58	407	0
T60	0	2
T61	422	0
T65	0	2
T75	0	4
T76	0	2
T77	0	4

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T6,T7,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T3,T6
1	0	Covered	T6,T7,T12
1	1	Covered	T2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	1152	0	0
SrcPulseCheck_M	1288412574	1208	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	1152
T2	9573	2
T3	949	1
T6	14245	3
T7	1276	3
T9	0	1
T10	0	2
T12	0	2
T13	502	0
T14	417	0
T15	472	0
T16	405	0
T17	410	0
T32	0	1
T34	0	5
T36	0	4
T58	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	1208
T2	244117	2
T3	227880	1
T6	712271	3
T7	224617	3
T9	0	1
T10	0	2
T12	0	2
T13	251036	0
T14	77097	0
T15	59147	0
T16	198488	0
T17	22616	0
T32	0	1
T34	0	5
T36	0	4
T58	48862	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T10,T24,T25
1	0	Covered	T10,T24,T25
1	1	Covered	T10,T24,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T10,T24,T25
1	0	Covered	T10,T24,T25
1	1	Covered	T10,T24,T25

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	3180	0	0
SrcPulseCheck_M	1288412574	3234	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	3180
T10	196046	20
T11	240873	0
T12	6527	0
T24	497	20
T25	0	20
T27	2961	0
T34	20386	0
T38	0	20
T42	0	40
T53	281091	0
T54	422	0
T55	503	0
T56	431	0
T62	0	20
T63	0	20
T64	0	20
T65	0	40
T66	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	3234
T10	793027	20
T11	118028	0
T12	750677	0
T24	62224	20
T25	0	20
T27	824624	0
T34	509676	0
T38	0	20
T42	0	40
T53	351363	0
T54	206905	0
T55	123471	0
T56	207151	0
T62	0	20
T63	0	20
T64	0	20
T65	0	40
T66	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T10,T24,T25
1	0	Covered	T10,T24,T25
1	1	Covered	T10,T24,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T10,T24,T25
1	0	Covered	T10,T24,T25
1	1	Covered	T10,T24,T25

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	3227	0	0
SrcPulseCheck_M	8975355	3227	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	3227
T10	793027	20
T11	118028	0
T12	750677	0
T24	62224	20
T25	0	20
T27	824624	0
T34	509676	0
T38	0	20
T42	0	40
T53	351363	0
T54	206905	0
T55	123471	0
T56	207151	0
T62	0	20
T63	0	20
T64	0	20
T65	0	40
T66	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	3227
T10	196046	20
T11	240873	0
T12	6527	0
T24	497	20
T25	0	20
T27	2961	0
T34	20386	0
T38	0	20
T42	0	40
T53	281091	0
T54	422	0
T55	503	0
T56	431	0
T62	0	20
T63	0	20
T64	0	20
T65	0	40
T66	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T13,T26
1	0	Covered	T5,T13,T26
1	1	Covered	T5,T13,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T13,T26
1	0	Covered	T5,T13,T26
1	1	Covered	T5,T13,T26

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	7052	0	0
SrcPulseCheck_M	1288412574	7114	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	7052
T1	545	0
T2	9573	0
T3	949	0
T5	521	20
T6	14245	0
T7	1276	0
T10	0	61
T13	502	20
T14	417	0
T15	472	0
T16	405	0
T24	0	1
T25	0	1
T26	0	20
T41	0	20
T55	0	20
T62	0	1
T63	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	7114
T1	262107	0
T2	244117	0
T3	227880	0
T5	234703	20
T6	712271	0
T7	224617	0
T10	0	61
T13	251036	20
T14	77097	0
T15	59147	0
T16	198488	0
T24	0	1
T25	0	1
T26	0	20
T41	0	20
T55	0	20
T62	0	1
T63	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T13,T26
1	0	Covered	T5,T13,T26
1	1	Covered	T5,T13,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T13,T26
1	0	Covered	T5,T13,T26
1	1	Covered	T5,T13,T26

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	7098	0	0
SrcPulseCheck_M	8975355	7098	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	7098
T1	262107	0
T2	244117	0
T3	227880	0
T5	234703	20
T6	712271	0
T7	224617	0
T10	0	61
T13	251036	20
T14	77097	0
T15	59147	0
T16	198488	0
T24	0	1
T25	0	1
T26	0	20
T41	0	20
T55	0	20
T62	0	1
T63	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	7098
T1	545	0
T2	9573	0
T3	949	0
T5	521	20
T6	14245	0
T7	1276	0
T10	0	61
T13	502	20
T14	417	0
T15	472	0
T16	405	0
T24	0	1
T25	0	1
T26	0	20
T41	0	20
T55	0	20
T62	0	1
T63	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T5,T2
1	1	Covered	T5,T13,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T5,T2
1	0	Covered	T5,T13,T26
1	1	Covered	T4,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	8217	0	0
SrcPulseCheck_M	1288412574	8280	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	8217
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	20
T6	14245	3
T7	1276	0
T9	0	2
T10	0	67
T13	502	20
T14	417	0
T15	472	1
T26	0	20
T27	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	8280
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	20
T6	712271	3
T7	224617	0
T9	0	2
T10	0	67
T13	251036	20
T14	77097	0
T15	59147	1
T26	0	20
T27	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T5,T2
1	1	Covered	T5,T13,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T5,T2
1	0	Covered	T5,T13,T26
1	1	Covered	T4,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	8263	0	0
SrcPulseCheck_M	8975355	8263	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	8263
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	20
T6	712271	3
T7	224617	0
T9	0	2
T10	0	67
T13	251036	20
T14	77097	0
T15	59147	1
T26	0	20
T27	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	8263
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	20
T6	14245	3
T7	1276	0
T9	0	2
T10	0	67
T13	502	20
T14	417	0
T15	472	1
T26	0	20
T27	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T13,T26
1	0	Covered	T5,T13,T26
1	1	Covered	T5,T13,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T13,T26
1	0	Covered	T5,T13,T26
1	1	Covered	T5,T13,T26

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	6963	0	0
SrcPulseCheck_M	1288412574	7019	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	6963
T1	545	0
T2	9573	0
T3	949	0
T5	521	20
T6	14245	0
T7	1276	0
T10	0	60
T13	502	20
T14	417	0
T15	472	0
T16	405	0
T26	0	20
T41	0	20
T46	0	40
T55	0	20
T67	0	20
T68	0	20
T69	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	7019
T1	262107	0
T2	244117	0
T3	227880	0
T5	234703	20
T6	712271	0
T7	224617	0
T10	0	60
T13	251036	20
T14	77097	0
T15	59147	0
T16	198488	0
T26	0	20
T41	0	20
T46	0	40
T55	0	20
T67	0	20
T68	0	20
T69	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T13,T26
1	0	Covered	T5,T13,T26
1	1	Covered	T5,T13,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T13,T26
1	0	Covered	T5,T13,T26
1	1	Covered	T5,T13,T26

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	7004	0	0
SrcPulseCheck_M	8975355	7004	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	7004
T1	262107	0
T2	244117	0
T3	227880	0
T5	234703	20
T6	712271	0
T7	224617	0
T10	0	60
T13	251036	20
T14	77097	0
T15	59147	0
T16	198488	0
T26	0	20
T41	0	20
T46	0	40
T55	0	20
T67	0	20
T68	0	20
T69	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	7004
T1	545	0
T2	9573	0
T3	949	0
T5	521	20
T6	14245	0
T7	1276	0
T10	0	60
T13	502	20
T14	417	0
T15	472	0
T16	405	0
T26	0	20
T41	0	20
T46	0	40
T55	0	20
T67	0	20
T68	0	20
T69	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T8,T10
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T8,T10
1	0	Covered	T78,T79,T21
1	1	Covered	T1,T8,T10

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	1109	0	0
SrcPulseCheck_M	1288412574	1161	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	1109
T1	545	1
T2	9573	0
T3	949	0
T6	14245	0
T7	1276	0
T8	0	1
T10	0	1
T11	0	1
T13	502	0
T14	417	0
T15	472	0
T16	405	0
T17	410	0
T37	0	1
T38	0	3
T39	0	2
T41	0	2
T43	0	1
T70	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	1161
T1	262107	1
T2	244117	0
T3	227880	0
T6	712271	0
T7	224617	0
T8	0	1
T10	0	1
T11	0	1
T13	251036	0
T14	77097	0
T15	59147	0
T16	198488	0
T17	22616	0
T37	0	1
T38	0	3
T39	0	2
T41	0	2
T43	0	1
T70	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T8,T10
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T8,T10
1	0	Covered	T78,T79,T21
1	1	Covered	T1,T8,T10

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	1152	0	0
SrcPulseCheck_M	8975355	1152	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	1152
T1	262107	1
T2	244117	0
T3	227880	0
T6	712271	0
T7	224617	0
T8	0	1
T10	0	1
T11	0	1
T13	251036	0
T14	77097	0
T15	59147	0
T16	198488	0
T17	22616	0
T37	0	1
T38	0	3
T39	0	2
T41	0	2
T43	0	1
T70	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	1152
T1	545	1
T2	9573	0
T3	949	0
T6	14245	0
T7	1276	0
T8	0	1
T10	0	1
T11	0	1
T13	502	0
T14	417	0
T15	472	0
T16	405	0
T17	410	0
T37	0	1
T38	0	3
T39	0	2
T41	0	2
T43	0	1
T70	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T1,T2
1	0	Covered	T78,T79,T21
1	1	Covered	T4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	2052	0	0
SrcPulseCheck_M	1288412574	2106	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	2052
T1	545	1
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	3
T7	1276	0
T8	0	1
T9	0	2
T10	0	3
T11	0	1
T13	502	0
T14	417	0
T15	472	1
T27	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	2106
T1	262107	1
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	3
T7	224617	0
T8	0	1
T9	0	2
T10	0	3
T11	0	1
T13	251036	0
T14	77097	0
T15	59147	1
T27	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T1,T2
1	0	Covered	T78,T79,T21
1	1	Covered	T4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	2096	0	0
SrcPulseCheck_M	8975355	2096	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	2096
T1	262107	1
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	3
T7	224617	0
T8	0	1
T9	0	2
T10	0	3
T11	0	1
T13	251036	0
T14	77097	0
T15	59147	1
T27	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	2096
T1	545	1
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	3
T7	1276	0
T8	0	1
T9	0	2
T10	0	3
T11	0	1
T13	502	0
T14	417	0
T15	472	1
T27	0	1

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T10,T27,T28
1	0	Covered	T10,T27,T28
1	1	Covered	T10,T27,T28

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T10,T27,T28
1	0	Covered	T10,T27,T28
1	1	Covered	T10,T27,T28

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	1497	0	0
SrcPulseCheck_M	1288412574	1551	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	1497
T10	196046	2
T11	240873	0
T12	6527	0
T24	497	0
T27	2961	3
T28	0	3
T32	0	7
T34	20386	0
T46	0	5
T47	0	5
T48	0	5
T49	0	4
T51	0	4
T52	0	4
T53	281091	0
T54	422	0
T55	503	0
T56	431	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	1551
T10	793027	2
T11	118028	0
T12	750677	0
T24	62224	0
T27	824624	3
T28	0	3
T32	0	7
T34	509676	0
T46	0	5
T47	0	5
T48	0	5
T49	0	4
T51	0	4
T52	0	4
T53	351363	0
T54	206905	0
T55	123471	0
T56	207151	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T10,T27,T28
1	0	Covered	T10,T27,T28
1	1	Covered	T10,T27,T28

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T10,T27,T28
1	0	Covered	T10,T27,T28
1	1	Covered	T10,T27,T28

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	1543	0	0
SrcPulseCheck_M	8975355	1543	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	1543
T10	793027	2
T11	118028	0
T12	750677	0
T24	62224	0
T27	824624	3
T28	0	3
T32	0	7
T34	509676	0
T46	0	5
T47	0	5
T48	0	5
T49	0	4
T51	0	4
T52	0	4
T53	351363	0
T54	206905	0
T55	123471	0
T56	207151	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	1543
T10	196046	2
T11	240873	0
T12	6527	0
T24	497	0
T27	2961	3
T28	0	3
T32	0	7
T34	20386	0
T46	0	5
T47	0	5
T48	0	5
T49	0	4
T51	0	4
T52	0	4
T53	281091	0
T54	422	0
T55	503	0
T56	431	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T10,T27,T28
1	0	Covered	T10,T27,T28
1	1	Covered	T27,T28,T46

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T10,T27,T28
1	0	Covered	T27,T28,T46
1	1	Covered	T10,T27,T28

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	1260	0	0
SrcPulseCheck_M	1288412574	1314	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	1260
T10	196046	1
T11	240873	0
T12	6527	0
T24	497	0
T27	2961	3
T28	0	3
T32	0	4
T34	20386	0
T46	0	3
T47	0	3
T48	0	3
T49	0	3
T51	0	3
T52	0	3
T53	281091	0
T54	422	0
T55	503	0
T56	431	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	1314
T10	793027	1
T11	118028	0
T12	750677	0
T24	62224	0
T27	824624	3
T28	0	3
T32	0	4
T34	509676	0
T46	0	3
T47	0	3
T48	0	3
T49	0	3
T51	0	3
T52	0	3
T53	351363	0
T54	206905	0
T55	123471	0
T56	207151	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T10,T27,T28
1	0	Covered	T10,T27,T28
1	1	Covered	T27,T28,T46

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T10,T27,T28
1	0	Covered	T27,T28,T46
1	1	Covered	T10,T27,T28

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	1305	0	0
SrcPulseCheck_M	8975355	1305	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	1305
T10	793027	1
T11	118028	0
T12	750677	0
T24	62224	0
T27	824624	3
T28	0	3
T32	0	4
T34	509676	0
T46	0	3
T47	0	3
T48	0	3
T49	0	3
T51	0	3
T52	0	3
T53	351363	0
T54	206905	0
T55	123471	0
T56	207151	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	1305
T10	196046	1
T11	240873	0
T12	6527	0
T24	497	0
T27	2961	3
T28	0	3
T32	0	4
T34	20386	0
T46	0	3
T47	0	3
T48	0	3
T49	0	3
T51	0	3
T52	0	3
T53	281091	0
T54	422	0
T55	503	0
T56	431	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T15,T6,T9
1	0	Covered	T15,T6,T9
1	1	Covered	T6,T9,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T15,T6,T9
1	0	Covered	T6,T9,T12
1	1	Covered	T15,T6,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	7316	0	0
SrcPulseCheck_M	1288412574	7370	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	7316
T6	14245	66
T7	1276	0
T8	561	0
T9	9686	73
T12	0	67
T15	472	1
T16	405	0
T17	410	0
T26	507	0
T36	0	82
T44	0	69
T45	0	83
T50	0	1
T58	407	0
T61	422	0
T71	0	71
T72	0	83

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	7370
T6	712271	66
T7	224617	0
T8	234183	0
T9	474621	73
T12	0	67
T15	59147	1
T16	198488	0
T17	22616	0
T26	35529	0
T36	0	82
T44	0	69
T45	0	83
T50	0	1
T58	48862	0
T61	175274	0
T71	0	71
T72	0	83

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T15,T6,T9
1	0	Covered	T15,T6,T9
1	1	Covered	T6,T9,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T15,T6,T9
1	0	Covered	T6,T9,T12
1	1	Covered	T15,T6,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	7362	0	0
SrcPulseCheck_M	8975355	7362	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	7362
T6	712271	66
T7	224617	0
T8	234183	0
T9	474621	73
T12	0	67
T15	59147	1
T16	198488	0
T17	22616	0
T26	35529	0
T36	0	82
T44	0	69
T45	0	83
T50	0	1
T58	48862	0
T61	175274	0
T71	0	71
T72	0	83

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	7362
T6	14245	66
T7	1276	0
T8	561	0
T9	9686	73
T12	0	67
T15	472	1
T16	405	0
T17	410	0
T26	507	0
T36	0	82
T44	0	69
T45	0	83
T50	0	1
T58	407	0
T61	422	0
T71	0	71
T72	0	83

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T6,T9,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T6,T9,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	7255	0	0
SrcPulseCheck_M	1288412574	7310	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	7255
T6	14245	87
T7	1276	0
T8	561	0
T9	9686	73
T10	196046	0
T12	0	67
T16	405	0
T17	410	0
T26	507	0
T36	0	82
T44	0	52
T45	0	59
T58	407	0
T61	422	0
T71	0	83
T72	0	75
T73	0	55
T74	0	52

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	7310
T6	712271	87
T7	224617	0
T8	234183	0
T9	474621	73
T10	793027	0
T12	0	67
T16	198488	0
T17	22616	0
T26	35529	0
T36	0	82
T44	0	52
T45	0	59
T58	48862	0
T61	175274	0
T71	0	83
T72	0	75
T73	0	55
T74	0	52

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T6,T9,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T6,T9,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	7299	0	0
SrcPulseCheck_M	8975355	7299	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	7299
T6	712271	87
T7	224617	0
T8	234183	0
T9	474621	73
T10	793027	0
T12	0	67
T16	198488	0
T17	22616	0
T26	35529	0
T36	0	82
T44	0	52
T45	0	59
T58	48862	0
T61	175274	0
T71	0	83
T72	0	75
T73	0	55
T74	0	52

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	7299
T6	14245	87
T7	1276	0
T8	561	0
T9	9686	73
T10	196046	0
T12	0	67
T16	405	0
T17	410	0
T26	507	0
T36	0	82
T44	0	52
T45	0	59
T58	407	0
T61	422	0
T71	0	83
T72	0	75
T73	0	55
T74	0	52

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T6,T9,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T6,T9,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	7405	0	0
SrcPulseCheck_M	1288412574	7465	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	7405
T6	14245	70
T7	1276	0
T8	561	0
T9	9686	52
T10	196046	0
T12	0	51
T16	405	0
T17	410	0
T26	507	0
T36	0	71
T44	0	58
T45	0	70
T58	407	0
T61	422	0
T71	0	58
T72	0	82
T73	0	73
T74	0	53

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	7465
T6	712271	70
T7	224617	0
T8	234183	0
T9	474621	52
T10	793027	0
T12	0	51
T16	198488	0
T17	22616	0
T26	35529	0
T36	0	71
T44	0	58
T45	0	70
T58	48862	0
T61	175274	0
T71	0	58
T72	0	82
T73	0	73
T74	0	53

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T6,T9,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T6,T9,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	7451	0	0
SrcPulseCheck_M	8975355	7451	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	7451
T6	712271	70
T7	224617	0
T8	234183	0
T9	474621	52
T10	793027	0
T12	0	51
T16	198488	0
T17	22616	0
T26	35529	0
T36	0	71
T44	0	58
T45	0	70
T58	48862	0
T61	175274	0
T71	0	58
T72	0	82
T73	0	73
T74	0	53

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	7451
T6	14245	70
T7	1276	0
T8	561	0
T9	9686	52
T10	196046	0
T12	0	51
T16	405	0
T17	410	0
T26	507	0
T36	0	71
T44	0	58
T45	0	70
T58	407	0
T61	422	0
T71	0	58
T72	0	82
T73	0	73
T74	0	53

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T6,T9,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T6,T9,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	7402	0	0
SrcPulseCheck_M	1288412574	7456	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	7402
T6	14245	77
T7	1276	0
T8	561	0
T9	9686	73
T10	196046	0
T12	0	67
T16	405	0
T17	410	0
T26	507	0
T36	0	57
T44	0	65
T45	0	81
T58	407	0
T61	422	0
T71	0	73
T72	0	76
T73	0	73
T74	0	52

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	7456
T6	712271	77
T7	224617	0
T8	234183	0
T9	474621	73
T10	793027	0
T12	0	67
T16	198488	0
T17	22616	0
T26	35529	0
T36	0	57
T44	0	65
T45	0	81
T58	48862	0
T61	175274	0
T71	0	73
T72	0	76
T73	0	73
T74	0	52

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T6,T9,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T6,T9,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	7447	0	0
SrcPulseCheck_M	8975355	7447	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	7447
T6	712271	77
T7	224617	0
T8	234183	0
T9	474621	73
T10	793027	0
T12	0	67
T16	198488	0
T17	22616	0
T26	35529	0
T36	0	57
T44	0	65
T45	0	81
T58	48862	0
T61	175274	0
T71	0	73
T72	0	76
T73	0	73
T74	0	52

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	7447
T6	14245	77
T7	1276	0
T8	561	0
T9	9686	73
T10	196046	0
T12	0	67
T16	405	0
T17	410	0
T26	507	0
T36	0	57
T44	0	65
T45	0	81
T58	407	0
T61	422	0
T71	0	73
T72	0	76
T73	0	73
T74	0	52

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T15,T6,T9
1	0	Covered	T15,T6,T9
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T15,T6,T9
1	0	Covered	T78,T79,T21
1	1	Covered	T15,T6,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	1329	0	0
SrcPulseCheck_M	1288412574	1384	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	1329
T6	14245	3
T7	1276	0
T8	561	0
T9	9686	2
T12	0	1
T15	472	1
T16	405	0
T17	410	0
T26	507	0
T36	0	1
T44	0	2
T45	0	1
T50	0	1
T58	407	0
T61	422	0
T71	0	4
T72	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	1384
T6	712271	3
T7	224617	0
T8	234183	0
T9	474621	2
T12	0	1
T15	59147	1
T16	198488	0
T17	22616	0
T26	35529	0
T36	0	1
T44	0	2
T45	0	1
T50	0	1
T58	48862	0
T61	175274	0
T71	0	4
T72	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T15,T6,T9
1	0	Covered	T15,T6,T9
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T15,T6,T9
1	0	Covered	T78,T79,T21
1	1	Covered	T15,T6,T9

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	1374	0	0
SrcPulseCheck_M	8975355	1374	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	1374
T6	712271	3
T7	224617	0
T8	234183	0
T9	474621	2
T12	0	1
T15	59147	1
T16	198488	0
T17	22616	0
T26	35529	0
T36	0	1
T44	0	2
T45	0	1
T50	0	1
T58	48862	0
T61	175274	0
T71	0	4
T72	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	1374
T6	14245	3
T7	1276	0
T8	561	0
T9	9686	2
T12	0	1
T15	472	1
T16	405	0
T17	410	0
T26	507	0
T36	0	1
T44	0	2
T45	0	1
T50	0	1
T58	407	0
T61	422	0
T71	0	4
T72	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T78,T79,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T78,T79,T30
1	1	Covered	T6,T9,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	1315	0	0
SrcPulseCheck_M	1288412574	1367	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	1315
T6	14245	3
T7	1276	0
T8	561	0
T9	9686	2
T10	196046	0
T12	0	1
T16	405	0
T17	410	0
T26	507	0
T36	0	1
T44	0	2
T45	0	1
T58	407	0
T61	422	0
T71	0	4
T72	0	15
T73	0	3
T74	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	1367
T6	712271	3
T7	224617	0
T8	234183	0
T9	474621	2
T10	793027	0
T12	0	1
T16	198488	0
T17	22616	0
T26	35529	0
T36	0	1
T44	0	2
T45	0	1
T58	48862	0
T61	175274	0
T71	0	4
T72	0	15
T73	0	3
T74	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T78,T79,T30

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T78,T79,T30
1	1	Covered	T6,T9,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	1357	0	0
SrcPulseCheck_M	8975355	1357	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	1357
T6	712271	3
T7	224617	0
T8	234183	0
T9	474621	2
T10	793027	0
T12	0	1
T16	198488	0
T17	22616	0
T26	35529	0
T36	0	1
T44	0	2
T45	0	1
T58	48862	0
T61	175274	0
T71	0	4
T72	0	15
T73	0	3
T74	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	1357
T6	14245	3
T7	1276	0
T8	561	0
T9	9686	2
T10	196046	0
T12	0	1
T16	405	0
T17	410	0
T26	507	0
T36	0	1
T44	0	2
T45	0	1
T58	407	0
T61	422	0
T71	0	4
T72	0	15
T73	0	3
T74	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T78,T79,T21
1	1	Covered	T6,T9,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	1315	0	0
SrcPulseCheck_M	1288412574	1370	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	1315
T6	14245	3
T7	1276	0
T8	561	0
T9	9686	2
T10	196046	0
T12	0	1
T16	405	0
T17	410	0
T26	507	0
T36	0	1
T44	0	2
T45	0	1
T58	407	0
T61	422	0
T71	0	4
T72	0	15
T73	0	3
T74	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	1370
T6	712271	3
T7	224617	0
T8	234183	0
T9	474621	2
T10	793027	0
T12	0	1
T16	198488	0
T17	22616	0
T26	35529	0
T36	0	1
T44	0	2
T45	0	1
T58	48862	0
T61	175274	0
T71	0	4
T72	0	15
T73	0	3
T74	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T78,T79,T21
1	1	Covered	T6,T9,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	1359	0	0
SrcPulseCheck_M	8975355	1359	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	1359
T6	712271	3
T7	224617	0
T8	234183	0
T9	474621	2
T10	793027	0
T12	0	1
T16	198488	0
T17	22616	0
T26	35529	0
T36	0	1
T44	0	2
T45	0	1
T58	48862	0
T61	175274	0
T71	0	4
T72	0	15
T73	0	3
T74	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	1359
T6	14245	3
T7	1276	0
T8	561	0
T9	9686	2
T10	196046	0
T12	0	1
T16	405	0
T17	410	0
T26	507	0
T36	0	1
T44	0	2
T45	0	1
T58	407	0
T61	422	0
T71	0	4
T72	0	15
T73	0	3
T74	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T78,T79,T21
1	1	Covered	T6,T9,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	1310	0	0
SrcPulseCheck_M	1288412574	1366	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	1310
T6	14245	3
T7	1276	0
T8	561	0
T9	9686	2
T10	196046	0
T12	0	1
T16	405	0
T17	410	0
T26	507	0
T36	0	1
T44	0	2
T45	0	1
T58	407	0
T61	422	0
T71	0	4
T72	0	15
T73	0	3
T74	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	1366
T6	712271	3
T7	224617	0
T8	234183	0
T9	474621	2
T10	793027	0
T12	0	1
T16	198488	0
T17	22616	0
T26	35529	0
T36	0	1
T44	0	2
T45	0	1
T58	48862	0
T61	175274	0
T71	0	4
T72	0	15
T73	0	3
T74	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T6,T9,T12
1	0	Covered	T78,T79,T21
1	1	Covered	T6,T9,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	1356	0	0
SrcPulseCheck_M	8975355	1356	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	1356
T6	712271	3
T7	224617	0
T8	234183	0
T9	474621	2
T10	793027	0
T12	0	1
T16	198488	0
T17	22616	0
T26	35529	0
T36	0	1
T44	0	2
T45	0	1
T58	48862	0
T61	175274	0
T71	0	4
T72	0	15
T73	0	3
T74	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	1356
T6	14245	3
T7	1276	0
T8	561	0
T9	9686	2
T10	196046	0
T12	0	1
T16	405	0
T17	410	0
T26	507	0
T36	0	1
T44	0	2
T45	0	1
T58	407	0
T61	422	0
T71	0	4
T72	0	15
T73	0	3
T74	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T15
1	0	Covered	T4,T2,T15
1	1	Covered	T6,T9,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T15
1	0	Covered	T6,T9,T12
1	1	Covered	T4,T2,T15

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	7958	0	0
SrcPulseCheck_M	1288412574	8009	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	7958
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	66
T7	1276	0
T9	0	73
T10	0	2
T12	0	67
T13	502	0
T14	417	0
T15	472	1
T27	0	1
T34	0	8
T36	0	82

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	8009
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	66
T7	224617	0
T9	0	73
T10	0	2
T12	0	67
T13	251036	0
T14	77097	0
T15	59147	1
T27	0	1
T34	0	8
T36	0	82

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T15
1	0	Covered	T4,T2,T15
1	1	Covered	T6,T9,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T15
1	0	Covered	T6,T9,T12
1	1	Covered	T4,T2,T15

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	8003	0	0
SrcPulseCheck_M	8975355	8003	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	8003
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	66
T7	224617	0
T9	0	73
T10	0	2
T12	0	67
T13	251036	0
T14	77097	0
T15	59147	1
T27	0	1
T34	0	8
T36	0	82

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	8003
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	66
T7	1276	0
T9	0	73
T10	0	2
T12	0	67
T13	502	0
T14	417	0
T15	472	1
T27	0	1
T34	0	8
T36	0	82

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T6,T9,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T6,T9,T12
1	1	Covered	T4,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	7879	0	0
SrcPulseCheck_M	1288412574	7932	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	7879
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	87
T7	1276	0
T9	0	73
T10	0	2
T12	0	67
T13	502	0
T14	417	0
T15	472	0
T32	0	2
T34	0	8
T36	0	82
T44	0	52

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	7932
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	87
T7	224617	0
T9	0	73
T10	0	2
T12	0	67
T13	251036	0
T14	77097	0
T15	59147	0
T32	0	2
T34	0	8
T36	0	82
T44	0	52

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T6,T9,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T6,T9,T12
1	1	Covered	T4,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	7919	0	0
SrcPulseCheck_M	8975355	7919	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	7919
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	87
T7	224617	0
T9	0	73
T10	0	2
T12	0	67
T13	251036	0
T14	77097	0
T15	59147	0
T32	0	2
T34	0	8
T36	0	82
T44	0	52

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	7919
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	87
T7	1276	0
T9	0	73
T10	0	2
T12	0	67
T13	502	0
T14	417	0
T15	472	0
T32	0	2
T34	0	8
T36	0	82
T44	0	52

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T6,T9,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T6,T9,T12
1	1	Covered	T4,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	7951	0	0
SrcPulseCheck_M	1288412574	8012	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	7951
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	70
T7	1276	0
T9	0	52
T10	0	2
T12	0	51
T13	502	0
T14	417	0
T15	472	0
T32	0	2
T34	0	8
T36	0	71
T44	0	58

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	8012
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	70
T7	224617	0
T9	0	52
T10	0	2
T12	0	51
T13	251036	0
T14	77097	0
T15	59147	0
T32	0	2
T34	0	8
T36	0	71
T44	0	58

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T6,T9,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T6,T9,T12
1	1	Covered	T4,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	8002	0	0
SrcPulseCheck_M	8975355	8002	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	8002
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	70
T7	224617	0
T9	0	52
T10	0	2
T12	0	51
T13	251036	0
T14	77097	0
T15	59147	0
T32	0	2
T34	0	8
T36	0	71
T44	0	58

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	8002
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	70
T7	1276	0
T9	0	52
T10	0	2
T12	0	51
T13	502	0
T14	417	0
T15	472	0
T32	0	2
T34	0	8
T36	0	71
T44	0	58

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T6,T9,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T6,T9,T12
1	1	Covered	T4,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	8003	0	0
SrcPulseCheck_M	1288412574	8054	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	8003
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	77
T7	1276	0
T9	0	73
T10	0	2
T12	0	67
T13	502	0
T14	417	0
T15	472	0
T32	0	2
T34	0	8
T36	0	57
T44	0	65

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	8054
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	77
T7	224617	0
T9	0	73
T10	0	2
T12	0	67
T13	251036	0
T14	77097	0
T15	59147	0
T32	0	2
T34	0	8
T36	0	57
T44	0	65

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T6,T9,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T6,T9,T12
1	1	Covered	T4,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	8046	0	0
SrcPulseCheck_M	8975355	8046	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	8046
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	77
T7	224617	0
T9	0	73
T10	0	2
T12	0	67
T13	251036	0
T14	77097	0
T15	59147	0
T32	0	2
T34	0	8
T36	0	57
T44	0	65

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	8046
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	77
T7	1276	0
T9	0	73
T10	0	2
T12	0	67
T13	502	0
T14	417	0
T15	472	0
T32	0	2
T34	0	8
T36	0	57
T44	0	65

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T15
1	0	Covered	T4,T2,T15
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T15
1	0	Covered	T78,T79,T21
1	1	Covered	T4,T2,T15

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	1961	0	0
SrcPulseCheck_M	1288412574	2017	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	1961
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	3
T7	1276	0
T9	0	2
T10	0	2
T12	0	1
T13	502	0
T14	417	0
T15	472	1
T27	0	1
T34	0	8
T36	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	2017
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	3
T7	224617	0
T9	0	2
T10	0	2
T12	0	1
T13	251036	0
T14	77097	0
T15	59147	1
T27	0	1
T34	0	8
T36	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T15
1	0	Covered	T4,T2,T15
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T15
1	0	Covered	T78,T79,T21
1	1	Covered	T4,T2,T15

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	2009	0	0
SrcPulseCheck_M	8975355	2009	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	2009
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	3
T7	224617	0
T9	0	2
T10	0	2
T12	0	1
T13	251036	0
T14	77097	0
T15	59147	1
T27	0	1
T34	0	8
T36	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	2009
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	3
T7	1276	0
T9	0	2
T10	0	2
T12	0	1
T13	502	0
T14	417	0
T15	472	1
T27	0	1
T34	0	8
T36	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T78,T79,T21
1	1	Covered	T4,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	1918	0	0
SrcPulseCheck_M	1288412574	1968	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	1918
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	3
T7	1276	0
T9	0	2
T10	0	2
T12	0	1
T13	502	0
T14	417	0
T15	472	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	1968
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	3
T7	224617	0
T9	0	2
T10	0	2
T12	0	1
T13	251036	0
T14	77097	0
T15	59147	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T78,T79,T21
1	1	Covered	T4,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	1960	0	0
SrcPulseCheck_M	8975355	1960	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	1960
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	3
T7	224617	0
T9	0	2
T10	0	2
T12	0	1
T13	251036	0
T14	77097	0
T15	59147	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	1960
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	3
T7	1276	0
T9	0	2
T10	0	2
T12	0	1
T13	502	0
T14	417	0
T15	472	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T78,T79,T21
1	1	Covered	T4,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	1910	0	0
SrcPulseCheck_M	1288412574	1964	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	1910
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	3
T7	1276	0
T9	0	2
T10	0	2
T12	0	1
T13	502	0
T14	417	0
T15	472	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	1964
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	3
T7	224617	0
T9	0	2
T10	0	2
T12	0	1
T13	251036	0
T14	77097	0
T15	59147	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T78,T79,T21
1	1	Covered	T4,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	1953	0	0
SrcPulseCheck_M	8975355	1953	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	1953
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	3
T7	224617	0
T9	0	2
T10	0	2
T12	0	1
T13	251036	0
T14	77097	0
T15	59147	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	1953
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	3
T7	1276	0
T9	0	2
T10	0	2
T12	0	1
T13	502	0
T14	417	0
T15	472	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T78,T79,T21
1	1	Covered	T4,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	1938	0	0
SrcPulseCheck_M	1288412574	1992	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	1938
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	3
T7	1276	0
T9	0	2
T10	0	2
T12	0	1
T13	502	0
T14	417	0
T15	472	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	1992
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	3
T7	224617	0
T9	0	2
T10	0	2
T12	0	1
T13	251036	0
T14	77097	0
T15	59147	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T78,T79,T21
1	1	Covered	T4,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	1983	0	0
SrcPulseCheck_M	8975355	1983	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	1983
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	3
T7	224617	0
T9	0	2
T10	0	2
T12	0	1
T13	251036	0
T14	77097	0
T15	59147	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	1983
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	3
T7	1276	0
T9	0	2
T10	0	2
T12	0	1
T13	502	0
T14	417	0
T15	472	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T15
1	0	Covered	T4,T2,T15
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T15
1	0	Covered	T78,T79,T21
1	1	Covered	T4,T2,T15

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	1957	0	0
SrcPulseCheck_M	1288412574	2012	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	1957
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	3
T7	1276	0
T9	0	2
T10	0	2
T12	0	1
T13	502	0
T14	417	0
T15	472	1
T27	0	1
T34	0	8
T36	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	2012
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	3
T7	224617	0
T9	0	2
T10	0	2
T12	0	1
T13	251036	0
T14	77097	0
T15	59147	1
T27	0	1
T34	0	8
T36	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T15
1	0	Covered	T4,T2,T15
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T15
1	0	Covered	T78,T79,T21
1	1	Covered	T4,T2,T15

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	2001	0	0
SrcPulseCheck_M	8975355	2001	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	2001
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	3
T7	224617	0
T9	0	2
T10	0	2
T12	0	1
T13	251036	0
T14	77097	0
T15	59147	1
T27	0	1
T34	0	8
T36	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	2001
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	3
T7	1276	0
T9	0	2
T10	0	2
T12	0	1
T13	502	0
T14	417	0
T15	472	1
T27	0	1
T34	0	8
T36	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T78,T79,T21
1	1	Covered	T4,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	1889	0	0
SrcPulseCheck_M	1288412574	1942	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	1889
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	3
T7	1276	0
T9	0	2
T10	0	2
T12	0	1
T13	502	0
T14	417	0
T15	472	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	1942
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	3
T7	224617	0
T9	0	2
T10	0	2
T12	0	1
T13	251036	0
T14	77097	0
T15	59147	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T78,T79,T21
1	1	Covered	T4,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	1932	0	0
SrcPulseCheck_M	8975355	1932	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	1932
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	3
T7	224617	0
T9	0	2
T10	0	2
T12	0	1
T13	251036	0
T14	77097	0
T15	59147	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	1932
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	3
T7	1276	0
T9	0	2
T10	0	2
T12	0	1
T13	502	0
T14	417	0
T15	472	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T78,T79,T21
1	1	Covered	T4,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	1915	0	0
SrcPulseCheck_M	1288412574	1964	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	1915
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	3
T7	1276	0
T9	0	2
T10	0	2
T12	0	1
T13	502	0
T14	417	0
T15	472	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	1964
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	3
T7	224617	0
T9	0	2
T10	0	2
T12	0	1
T13	251036	0
T14	77097	0
T15	59147	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T78,T79,T21
1	1	Covered	T4,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	1955	0	0
SrcPulseCheck_M	8975355	1955	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	1955
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	3
T7	224617	0
T9	0	2
T10	0	2
T12	0	1
T13	251036	0
T14	77097	0
T15	59147	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	1955
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	3
T7	1276	0
T9	0	2
T10	0	2
T12	0	1
T13	502	0
T14	417	0
T15	472	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T78,T79,T21
1	1	Covered	T4,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8975355	1885	0	0
SrcPulseCheck_M	1288412574	1939	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8975355	1885
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	3
T7	1276	0
T9	0	2
T10	0	2
T12	0	1
T13	502	0
T14	417	0
T15	472	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1288412574	1939
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	3
T7	224617	0
T9	0	2
T10	0	2
T12	0	1
T13	251036	0
T14	77097	0
T15	59147	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T78,T79,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T2,T6
1	0	Covered	T78,T79,T21
1	1	Covered	T4,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1288412574	1931	0	0
SrcPulseCheck_M	8975355	1931	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1288412574	1931
T1	262107	0
T2	244117	3
T3	227880	0
T4	392983	14
T5	234703	0
T6	712271	3
T7	224617	0
T9	0	2
T10	0	2
T12	0	1
T13	251036	0
T14	77097	0
T15	59147	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8975355	1931
T1	545	0
T2	9573	3
T3	949	0
T4	31438	14
T5	521	0
T6	14245	3
T7	1276	0
T9	0	2
T10	0	2
T12	0	1
T13	502	0
T14	417	0
T15	472	0
T32	0	2
T34	0	8
T36	0	1
T44	0	2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc