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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.31 96.36 100.00 96.79 98.74 99.52 93.49


Total test records in report: 916
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T803 /workspace/coverage/default/23.sysrst_ctrl_smoke.2234946036 Jun 26 04:54:34 PM PDT 24 Jun 26 04:54:40 PM PDT 24 2114776390 ps
T29 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2116912717 Jun 26 04:35:14 PM PDT 24 Jun 26 04:35:22 PM PDT 24 2147158915 ps
T804 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.2555106545 Jun 26 04:35:25 PM PDT 24 Jun 26 04:35:37 PM PDT 24 2013035569 ps
T21 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.1645630541 Jun 26 04:35:30 PM PDT 24 Jun 26 04:35:48 PM PDT 24 4808173934 ps
T30 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2198508562 Jun 26 04:35:12 PM PDT 24 Jun 26 04:35:28 PM PDT 24 2064618134 ps
T31 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.4143248099 Jun 26 04:35:18 PM PDT 24 Jun 26 04:38:14 PM PDT 24 38972055231 ps
T57 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.4188383414 Jun 26 04:35:23 PM PDT 24 Jun 26 04:35:32 PM PDT 24 2045464941 ps
T291 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1004288496 Jun 26 04:35:15 PM PDT 24 Jun 26 04:37:18 PM PDT 24 25019458203 ps
T805 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2566964797 Jun 26 04:35:42 PM PDT 24 Jun 26 04:35:49 PM PDT 24 2028490107 ps
T287 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1981367252 Jun 26 04:35:32 PM PDT 24 Jun 26 04:35:53 PM PDT 24 22491624659 ps
T806 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2115510992 Jun 26 04:35:30 PM PDT 24 Jun 26 04:35:37 PM PDT 24 2041241686 ps
T348 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.659280904 Jun 26 04:35:33 PM PDT 24 Jun 26 04:35:40 PM PDT 24 2054998704 ps
T349 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.801848618 Jun 26 04:35:17 PM PDT 24 Jun 26 04:35:24 PM PDT 24 2133708564 ps
T308 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1425079451 Jun 26 04:35:21 PM PDT 24 Jun 26 04:35:32 PM PDT 24 2122873994 ps
T807 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1362108215 Jun 26 04:35:40 PM PDT 24 Jun 26 04:35:49 PM PDT 24 2013006674 ps
T281 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2633072372 Jun 26 04:35:25 PM PDT 24 Jun 26 04:36:01 PM PDT 24 42826832084 ps
T294 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1188603941 Jun 26 04:35:44 PM PDT 24 Jun 26 04:35:50 PM PDT 24 2229762489 ps
T808 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2712327695 Jun 26 04:35:26 PM PDT 24 Jun 26 04:35:35 PM PDT 24 2023899357 ps
T350 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3776680765 Jun 26 04:35:27 PM PDT 24 Jun 26 04:35:39 PM PDT 24 2039332525 ps
T282 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2038749276 Jun 26 04:35:38 PM PDT 24 Jun 26 04:35:44 PM PDT 24 2190717911 ps
T809 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.4188929951 Jun 26 04:35:31 PM PDT 24 Jun 26 04:35:42 PM PDT 24 2015135915 ps
T351 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.2129102989 Jun 26 04:35:17 PM PDT 24 Jun 26 04:35:27 PM PDT 24 2030049734 ps
T18 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.1494123568 Jun 26 04:35:31 PM PDT 24 Jun 26 04:36:12 PM PDT 24 10219061885 ps
T810 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.185051379 Jun 26 04:35:39 PM PDT 24 Jun 26 04:35:44 PM PDT 24 2031660175 ps
T337 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2753148241 Jun 26 04:35:27 PM PDT 24 Jun 26 04:35:37 PM PDT 24 6077721358 ps
T305 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.252625511 Jun 26 04:35:21 PM PDT 24 Jun 26 04:35:31 PM PDT 24 2091551314 ps
T300 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.971592238 Jun 26 04:35:40 PM PDT 24 Jun 26 04:35:46 PM PDT 24 2224212171 ps
T811 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2579230615 Jun 26 04:35:24 PM PDT 24 Jun 26 04:35:36 PM PDT 24 2014218941 ps
T338 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.508353935 Jun 26 04:35:42 PM PDT 24 Jun 26 04:35:52 PM PDT 24 2065711334 ps
T288 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2435779751 Jun 26 04:35:36 PM PDT 24 Jun 26 04:36:37 PM PDT 24 42602589839 ps
T289 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.704810477 Jun 26 04:35:25 PM PDT 24 Jun 26 04:35:38 PM PDT 24 2043653399 ps
T283 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1165769129 Jun 26 04:35:22 PM PDT 24 Jun 26 04:35:57 PM PDT 24 22335916584 ps
T290 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.238725227 Jun 26 04:35:40 PM PDT 24 Jun 26 04:35:48 PM PDT 24 2145190974 ps
T339 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2697312887 Jun 26 04:35:20 PM PDT 24 Jun 26 04:39:34 PM PDT 24 53947014349 ps
T292 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1593791898 Jun 26 04:35:18 PM PDT 24 Jun 26 04:35:24 PM PDT 24 3109034626 ps
T812 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1716811620 Jun 26 04:35:24 PM PDT 24 Jun 26 04:35:34 PM PDT 24 2086373186 ps
T306 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3133762005 Jun 26 04:35:32 PM PDT 24 Jun 26 04:36:10 PM PDT 24 42820417968 ps
T22 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.3018608379 Jun 26 04:35:24 PM PDT 24 Jun 26 04:35:55 PM PDT 24 10314516289 ps
T340 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2143092752 Jun 26 04:35:24 PM PDT 24 Jun 26 04:35:34 PM PDT 24 2063175880 ps
T304 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.203410649 Jun 26 04:35:09 PM PDT 24 Jun 26 04:36:09 PM PDT 24 42599923193 ps
T813 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.861668496 Jun 26 04:35:40 PM PDT 24 Jun 26 04:35:59 PM PDT 24 22279635169 ps
T341 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.871257767 Jun 26 04:35:12 PM PDT 24 Jun 26 04:35:19 PM PDT 24 2684486875 ps
T303 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.740247882 Jun 26 04:35:15 PM PDT 24 Jun 26 04:36:12 PM PDT 24 42584267781 ps
T293 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.928136177 Jun 26 04:35:33 PM PDT 24 Jun 26 04:35:55 PM PDT 24 22455202351 ps
T295 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.979554540 Jun 26 04:35:32 PM PDT 24 Jun 26 04:35:41 PM PDT 24 2441595171 ps
T814 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.954737748 Jun 26 04:35:28 PM PDT 24 Jun 26 04:35:39 PM PDT 24 2015314542 ps
T815 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3926189609 Jun 26 04:35:40 PM PDT 24 Jun 26 04:35:52 PM PDT 24 4643751726 ps
T296 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.594411416 Jun 26 04:35:27 PM PDT 24 Jun 26 04:35:37 PM PDT 24 2180331201 ps
T307 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2792766139 Jun 26 04:35:42 PM PDT 24 Jun 26 04:35:49 PM PDT 24 2175640465 ps
T816 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2490949182 Jun 26 04:35:40 PM PDT 24 Jun 26 04:35:45 PM PDT 24 2060226085 ps
T817 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3719750583 Jun 26 04:35:16 PM PDT 24 Jun 26 04:36:20 PM PDT 24 22197734660 ps
T818 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.705466433 Jun 26 04:35:19 PM PDT 24 Jun 26 04:35:26 PM PDT 24 2071781605 ps
T819 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.2823947412 Jun 26 04:35:27 PM PDT 24 Jun 26 04:35:42 PM PDT 24 6037098174 ps
T301 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.2995786436 Jun 26 04:35:14 PM PDT 24 Jun 26 04:35:46 PM PDT 24 42948980510 ps
T820 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1292137695 Jun 26 04:35:30 PM PDT 24 Jun 26 04:35:41 PM PDT 24 2010721286 ps
T821 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3216226582 Jun 26 04:35:12 PM PDT 24 Jun 26 04:35:16 PM PDT 24 2081574683 ps
T822 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2279781162 Jun 26 04:35:36 PM PDT 24 Jun 26 04:35:43 PM PDT 24 2029643467 ps
T309 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2583795624 Jun 26 04:35:31 PM PDT 24 Jun 26 04:35:39 PM PDT 24 2099547821 ps
T823 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2554893048 Jun 26 04:35:38 PM PDT 24 Jun 26 04:35:43 PM PDT 24 2444718130 ps
T19 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2087776735 Jun 26 04:35:45 PM PDT 24 Jun 26 04:35:52 PM PDT 24 7886705917 ps
T298 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1225765 Jun 26 04:35:28 PM PDT 24 Jun 26 04:35:36 PM PDT 24 2136281656 ps
T824 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.493376618 Jun 26 04:35:23 PM PDT 24 Jun 26 04:35:30 PM PDT 24 2437406596 ps
T299 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3585791916 Jun 26 04:35:20 PM PDT 24 Jun 26 04:35:28 PM PDT 24 3747689390 ps
T825 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2939006530 Jun 26 04:35:34 PM PDT 24 Jun 26 04:35:43 PM PDT 24 2089563041 ps
T826 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1122814903 Jun 26 04:35:30 PM PDT 24 Jun 26 04:35:37 PM PDT 24 2028581651 ps
T827 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1712148290 Jun 26 04:35:15 PM PDT 24 Jun 26 04:35:18 PM PDT 24 2058721687 ps
T828 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.776356368 Jun 26 04:35:31 PM PDT 24 Jun 26 04:35:43 PM PDT 24 2012270572 ps
T829 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3782574275 Jun 26 04:35:24 PM PDT 24 Jun 26 04:35:36 PM PDT 24 2013948407 ps
T830 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1355331866 Jun 26 04:35:20 PM PDT 24 Jun 26 04:35:31 PM PDT 24 2060017429 ps
T831 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2547279293 Jun 26 04:35:34 PM PDT 24 Jun 26 04:35:43 PM PDT 24 2080736939 ps
T832 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3714411778 Jun 26 04:35:33 PM PDT 24 Jun 26 04:35:41 PM PDT 24 2027336592 ps
T833 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.822723523 Jun 26 04:35:32 PM PDT 24 Jun 26 04:35:41 PM PDT 24 2052889426 ps
T834 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1185534146 Jun 26 04:35:31 PM PDT 24 Jun 26 04:35:39 PM PDT 24 2035796897 ps
T835 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1096668089 Jun 26 04:35:18 PM PDT 24 Jun 26 04:35:24 PM PDT 24 4111355553 ps
T391 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3369432188 Jun 26 04:35:40 PM PDT 24 Jun 26 04:36:14 PM PDT 24 42805135523 ps
T836 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.3498567963 Jun 26 04:35:10 PM PDT 24 Jun 26 04:35:17 PM PDT 24 2012060881 ps
T837 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.957188174 Jun 26 04:35:46 PM PDT 24 Jun 26 04:35:53 PM PDT 24 2066162103 ps
T838 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.2969248133 Jun 26 04:35:14 PM PDT 24 Jun 26 04:35:44 PM PDT 24 42924204087 ps
T839 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.999037958 Jun 26 04:35:24 PM PDT 24 Jun 26 04:35:32 PM PDT 24 2137987545 ps
T20 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2983959944 Jun 26 04:35:25 PM PDT 24 Jun 26 04:35:57 PM PDT 24 10232670332 ps
T840 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3762747752 Jun 26 04:35:23 PM PDT 24 Jun 26 04:36:00 PM PDT 24 42765672352 ps
T389 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.4154359789 Jun 26 04:35:23 PM PDT 24 Jun 26 04:37:18 PM PDT 24 42359437262 ps
T841 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1243818922 Jun 26 04:35:23 PM PDT 24 Jun 26 04:36:01 PM PDT 24 42493837225 ps
T353 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3366462201 Jun 26 04:35:29 PM PDT 24 Jun 26 04:35:45 PM PDT 24 4035974370 ps
T842 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.617598658 Jun 26 04:35:39 PM PDT 24 Jun 26 04:35:44 PM PDT 24 2034938783 ps
T843 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1002524707 Jun 26 04:35:24 PM PDT 24 Jun 26 04:35:40 PM PDT 24 22309696340 ps
T844 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.3118010412 Jun 26 04:35:22 PM PDT 24 Jun 26 04:35:39 PM PDT 24 4536982120 ps
T845 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.992334512 Jun 26 04:35:35 PM PDT 24 Jun 26 04:35:42 PM PDT 24 5311737514 ps
T846 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.3625866796 Jun 26 04:35:32 PM PDT 24 Jun 26 04:35:39 PM PDT 24 2062725740 ps
T847 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2164898107 Jun 26 04:35:26 PM PDT 24 Jun 26 04:35:41 PM PDT 24 3196186933 ps
T848 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3509017833 Jun 26 04:35:43 PM PDT 24 Jun 26 04:35:50 PM PDT 24 2015894253 ps
T849 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3586114143 Jun 26 04:35:34 PM PDT 24 Jun 26 04:35:42 PM PDT 24 2021558976 ps
T850 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2949351187 Jun 26 04:35:29 PM PDT 24 Jun 26 04:35:44 PM PDT 24 5498847110 ps
T851 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.2333535802 Jun 26 04:35:55 PM PDT 24 Jun 26 04:36:02 PM PDT 24 2025644311 ps
T852 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.512085784 Jun 26 04:35:28 PM PDT 24 Jun 26 04:35:37 PM PDT 24 2020638434 ps
T853 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.73574543 Jun 26 04:35:41 PM PDT 24 Jun 26 04:35:51 PM PDT 24 2010761092 ps
T342 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.3653087274 Jun 26 04:35:13 PM PDT 24 Jun 26 04:35:21 PM PDT 24 2037422244 ps
T854 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1661676171 Jun 26 04:35:30 PM PDT 24 Jun 26 04:35:39 PM PDT 24 2014403990 ps
T855 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.644706021 Jun 26 04:35:46 PM PDT 24 Jun 26 04:35:52 PM PDT 24 2024230984 ps
T856 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2239016947 Jun 26 04:35:25 PM PDT 24 Jun 26 04:35:39 PM PDT 24 9026066289 ps
T857 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.2154519804 Jun 26 04:35:38 PM PDT 24 Jun 26 04:35:45 PM PDT 24 2017698600 ps
T858 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.1776816812 Jun 26 04:35:36 PM PDT 24 Jun 26 04:35:46 PM PDT 24 2012599491 ps
T859 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1117838547 Jun 26 04:35:37 PM PDT 24 Jun 26 04:35:47 PM PDT 24 2011501065 ps
T860 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1666434594 Jun 26 04:35:22 PM PDT 24 Jun 26 04:35:30 PM PDT 24 2099309162 ps
T861 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2397792155 Jun 26 04:35:28 PM PDT 24 Jun 26 04:35:38 PM PDT 24 2542224072 ps
T862 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1756019709 Jun 26 04:35:29 PM PDT 24 Jun 26 04:35:41 PM PDT 24 2137931767 ps
T863 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.4290113206 Jun 26 04:35:24 PM PDT 24 Jun 26 04:35:35 PM PDT 24 2036447289 ps
T864 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.1466800392 Jun 26 04:35:27 PM PDT 24 Jun 26 04:35:38 PM PDT 24 2033356526 ps
T343 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.64550110 Jun 26 04:35:15 PM PDT 24 Jun 26 04:35:19 PM PDT 24 2169514803 ps
T865 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3465271175 Jun 26 04:35:43 PM PDT 24 Jun 26 04:35:53 PM PDT 24 5178182298 ps
T866 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.4190005388 Jun 26 04:35:24 PM PDT 24 Jun 26 04:35:37 PM PDT 24 2120396830 ps
T867 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3428435951 Jun 26 04:35:31 PM PDT 24 Jun 26 04:36:13 PM PDT 24 77053183286 ps
T344 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.970247288 Jun 26 04:35:25 PM PDT 24 Jun 26 04:35:34 PM PDT 24 2180291032 ps
T345 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.815679209 Jun 26 04:35:24 PM PDT 24 Jun 26 04:35:38 PM PDT 24 2308468048 ps
T390 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3356095195 Jun 26 04:35:24 PM PDT 24 Jun 26 04:37:26 PM PDT 24 42373131742 ps
T868 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2403185352 Jun 26 04:35:17 PM PDT 24 Jun 26 04:35:37 PM PDT 24 6012131833 ps
T869 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.3397318921 Jun 26 04:35:23 PM PDT 24 Jun 26 04:35:35 PM PDT 24 2017181867 ps
T346 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.696744282 Jun 26 04:35:15 PM PDT 24 Jun 26 04:38:03 PM PDT 24 67698284200 ps
T870 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2374394280 Jun 26 04:35:27 PM PDT 24 Jun 26 04:35:34 PM PDT 24 2246562406 ps
T871 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1663185946 Jun 26 04:35:45 PM PDT 24 Jun 26 04:35:55 PM PDT 24 2026309930 ps
T872 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.2379272956 Jun 26 04:35:23 PM PDT 24 Jun 26 04:35:35 PM PDT 24 2012081411 ps
T873 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.199413386 Jun 26 04:35:36 PM PDT 24 Jun 26 04:35:45 PM PDT 24 2018284724 ps
T874 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1038991004 Jun 26 04:35:37 PM PDT 24 Jun 26 04:35:47 PM PDT 24 2040531764 ps
T875 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3283043132 Jun 26 04:35:28 PM PDT 24 Jun 26 04:35:40 PM PDT 24 8283629908 ps
T876 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.2825822517 Jun 26 04:35:26 PM PDT 24 Jun 26 04:36:30 PM PDT 24 42582963372 ps
T877 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.2139287588 Jun 26 04:35:23 PM PDT 24 Jun 26 04:35:35 PM PDT 24 2012482034 ps
T878 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3521840444 Jun 26 04:35:34 PM PDT 24 Jun 26 04:35:43 PM PDT 24 2028818167 ps
T879 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.337404835 Jun 26 04:35:30 PM PDT 24 Jun 26 04:35:42 PM PDT 24 5580018780 ps
T880 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.737887838 Jun 26 04:35:31 PM PDT 24 Jun 26 04:35:42 PM PDT 24 2069208533 ps
T881 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3834591923 Jun 26 04:35:18 PM PDT 24 Jun 26 04:35:33 PM PDT 24 5389165185 ps
T882 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1963670139 Jun 26 04:35:14 PM PDT 24 Jun 26 04:35:18 PM PDT 24 2085975025 ps
T883 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1544554242 Jun 26 04:35:37 PM PDT 24 Jun 26 04:35:42 PM PDT 24 2103513332 ps
T884 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1527197901 Jun 26 04:35:31 PM PDT 24 Jun 26 04:35:40 PM PDT 24 2071052667 ps
T885 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1468848887 Jun 26 04:35:43 PM PDT 24 Jun 26 04:35:49 PM PDT 24 2034373548 ps
T886 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2404667458 Jun 26 04:35:46 PM PDT 24 Jun 26 04:35:56 PM PDT 24 2008764304 ps
T887 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.3135785585 Jun 26 04:35:30 PM PDT 24 Jun 26 04:35:36 PM PDT 24 2121750985 ps
T888 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2633268375 Jun 26 04:36:13 PM PDT 24 Jun 26 04:36:28 PM PDT 24 4466219526 ps
T889 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1342298869 Jun 26 04:35:21 PM PDT 24 Jun 26 04:35:34 PM PDT 24 2037056087 ps
T890 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2180982637 Jun 26 04:35:30 PM PDT 24 Jun 26 04:35:49 PM PDT 24 6205627772 ps
T891 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.751269346 Jun 26 04:35:45 PM PDT 24 Jun 26 04:36:09 PM PDT 24 4824455568 ps
T892 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2426865556 Jun 26 04:35:18 PM PDT 24 Jun 26 04:35:25 PM PDT 24 2122453486 ps
T893 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.3348065808 Jun 26 04:35:21 PM PDT 24 Jun 26 04:35:34 PM PDT 24 2065067400 ps
T347 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2814933773 Jun 26 04:35:24 PM PDT 24 Jun 26 04:35:32 PM PDT 24 2081661184 ps
T894 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1545715061 Jun 26 04:35:23 PM PDT 24 Jun 26 04:35:32 PM PDT 24 2013630048 ps
T895 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.298328653 Jun 26 04:35:28 PM PDT 24 Jun 26 04:35:36 PM PDT 24 2192455592 ps
T896 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1532931195 Jun 26 04:35:22 PM PDT 24 Jun 26 04:35:30 PM PDT 24 2216755941 ps
T897 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3353336942 Jun 26 04:35:41 PM PDT 24 Jun 26 04:35:52 PM PDT 24 10494880035 ps
T898 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3270595269 Jun 26 04:35:33 PM PDT 24 Jun 26 04:35:44 PM PDT 24 2013876796 ps
T899 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2412045856 Jun 26 04:35:43 PM PDT 24 Jun 26 04:35:50 PM PDT 24 2499563220 ps
T900 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.2370647784 Jun 26 04:35:13 PM PDT 24 Jun 26 04:35:20 PM PDT 24 2887494299 ps
T901 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2959405633 Jun 26 04:35:18 PM PDT 24 Jun 26 04:35:30 PM PDT 24 2517257771 ps
T902 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2484180568 Jun 26 04:35:23 PM PDT 24 Jun 26 04:35:32 PM PDT 24 2048011533 ps
T903 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2941616343 Jun 26 04:35:39 PM PDT 24 Jun 26 04:35:48 PM PDT 24 2015815281 ps
T904 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1451865790 Jun 26 04:35:30 PM PDT 24 Jun 26 04:35:39 PM PDT 24 2017086460 ps
T905 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.1689175173 Jun 26 04:35:17 PM PDT 24 Jun 26 04:35:29 PM PDT 24 4904290631 ps
T906 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1470012353 Jun 26 04:35:34 PM PDT 24 Jun 26 04:35:45 PM PDT 24 2070397054 ps
T907 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.4098271471 Jun 26 04:35:26 PM PDT 24 Jun 26 04:35:53 PM PDT 24 5349830044 ps
T908 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1961204806 Jun 26 04:35:43 PM PDT 24 Jun 26 04:35:53 PM PDT 24 2013190669 ps
T909 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1381439384 Jun 26 04:35:24 PM PDT 24 Jun 26 04:35:35 PM PDT 24 2022423948 ps
T910 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2698928655 Jun 26 04:35:31 PM PDT 24 Jun 26 04:35:38 PM PDT 24 2157964873 ps
T911 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2177833941 Jun 26 04:35:35 PM PDT 24 Jun 26 04:35:43 PM PDT 24 2172414586 ps
T912 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1073513892 Jun 26 04:35:36 PM PDT 24 Jun 26 04:36:01 PM PDT 24 22400396097 ps
T913 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.1334643979 Jun 26 04:35:25 PM PDT 24 Jun 26 04:35:33 PM PDT 24 2129604068 ps
T914 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1421675246 Jun 26 04:35:25 PM PDT 24 Jun 26 04:35:37 PM PDT 24 2010467315 ps
T915 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3442618092 Jun 26 04:35:31 PM PDT 24 Jun 26 04:35:39 PM PDT 24 2042554476 ps
T916 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.856875134 Jun 26 04:35:37 PM PDT 24 Jun 26 04:35:42 PM PDT 24 2032661730 ps

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3976761855
Short name T6
Test name
Test status
Simulation time 71227139611 ps
CPU time 181.96 seconds
Started Jun 26 04:55:05 PM PDT 24
Finished Jun 26 04:58:12 PM PDT 24
Peak memory 201768 kb
Host smart-4379a7ea-5c64-4676-bf9e-3ba41352dd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976761855 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_w
ith_pre_cond.3976761855
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1574251405
Short name T10
Test name
Test status
Simulation time 980229357513 ps
CPU time 436.69 seconds
Started Jun 26 04:54:34 PM PDT 24
Finished Jun 26 05:01:53 PM PDT 24
Peak memory 214792 kb
Host smart-55c60aec-a96a-4b6b-868d-b19ce3f726cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574251405 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.1574251405
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.996178925
Short name T42
Test name
Test status
Simulation time 66165275733 ps
CPU time 151.47 seconds
Started Jun 26 04:55:04 PM PDT 24
Finished Jun 26 04:57:40 PM PDT 24
Peak memory 210256 kb
Host smart-9f46f72a-4ab2-4bd4-ab99-9533185f136f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996178925 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.996178925
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.3539715176
Short name T79
Test name
Test status
Simulation time 30809681055 ps
CPU time 83.67 seconds
Started Jun 26 04:53:41 PM PDT 24
Finished Jun 26 04:55:08 PM PDT 24
Peak memory 201500 kb
Host smart-13265efc-2fe4-4fa1-985a-6ac3b1f710ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539715176 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.3539715176
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.170554434
Short name T2
Test name
Test status
Simulation time 47866518133 ps
CPU time 62.6 seconds
Started Jun 26 04:53:50 PM PDT 24
Finished Jun 26 04:54:56 PM PDT 24
Peak memory 201740 kb
Host smart-44bb898a-27d9-4b10-8db3-6bc59c64370c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170554434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_combo_detect.170554434
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3073908275
Short name T88
Test name
Test status
Simulation time 50004567523 ps
CPU time 16.99 seconds
Started Jun 26 04:54:28 PM PDT 24
Finished Jun 26 04:54:48 PM PDT 24
Peak memory 217868 kb
Host smart-5e2b3931-9f7c-4967-8ba8-7ef8536c9600
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073908275 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.3073908275
Directory /workspace/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.2999412902
Short name T51
Test name
Test status
Simulation time 65657959166 ps
CPU time 172.12 seconds
Started Jun 26 04:55:38 PM PDT 24
Finished Jun 26 04:58:34 PM PDT 24
Peak memory 201280 kb
Host smart-f5dfb1af-3d8c-44e0-a3eb-ddf97a56593c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999412902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s
tress_all.2999412902
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2633072372
Short name T281
Test name
Test status
Simulation time 42826832084 ps
CPU time 29.96 seconds
Started Jun 26 04:35:25 PM PDT 24
Finished Jun 26 04:36:01 PM PDT 24
Peak memory 202148 kb
Host smart-74c71d65-6a7a-4ac3-857a-0148856ff41a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633072372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.2633072372
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.2391791734
Short name T86
Test name
Test status
Simulation time 53174933285 ps
CPU time 61.77 seconds
Started Jun 26 04:55:01 PM PDT 24
Finished Jun 26 04:56:07 PM PDT 24
Peak memory 211736 kb
Host smart-3f717c7e-f58e-49ef-ab92-539cfcdffaac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391791734 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.2391791734
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.255748407
Short name T356
Test name
Test status
Simulation time 146442675093 ps
CPU time 41.55 seconds
Started Jun 26 04:55:10 PM PDT 24
Finished Jun 26 04:55:56 PM PDT 24
Peak memory 217788 kb
Host smart-9cbd7c0a-9f3c-4dfd-8e59-4bfc65a81871
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255748407 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.255748407
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.2702739121
Short name T12
Test name
Test status
Simulation time 32637984934 ps
CPU time 22.21 seconds
Started Jun 26 04:55:06 PM PDT 24
Finished Jun 26 04:55:33 PM PDT 24
Peak memory 201724 kb
Host smart-2cf743ae-5d4d-4cca-9607-75089802260e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702739121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.2702739121
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.984193565
Short name T72
Test name
Test status
Simulation time 193615883792 ps
CPU time 135.11 seconds
Started Jun 26 04:55:29 PM PDT 24
Finished Jun 26 04:57:50 PM PDT 24
Peak memory 201840 kb
Host smart-d55a4bff-5293-43be-adbb-f1ca76c9c7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984193565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_wi
th_pre_cond.984193565
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.366531710
Short name T83
Test name
Test status
Simulation time 39769665464 ps
CPU time 62.28 seconds
Started Jun 26 04:53:48 PM PDT 24
Finished Jun 26 04:54:54 PM PDT 24
Peak memory 218356 kb
Host smart-0c6386d3-30ea-43da-9847-445f82bb3e13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366531710 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.366531710
Directory /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.976170230
Short name T39
Test name
Test status
Simulation time 132093858546 ps
CPU time 168.58 seconds
Started Jun 26 04:54:23 PM PDT 24
Finished Jun 26 04:57:12 PM PDT 24
Peak memory 210180 kb
Host smart-1bfdc84d-dec5-4123-b252-41ce68ea29a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976170230 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.976170230
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.2714863841
Short name T58
Test name
Test status
Simulation time 2036049890 ps
CPU time 1.96 seconds
Started Jun 26 04:54:19 PM PDT 24
Finished Jun 26 04:54:22 PM PDT 24
Peak memory 201416 kb
Host smart-4d26b228-7da8-4f1c-a596-97166b054c63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714863841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_te
st.2714863841
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.2596522338
Short name T73
Test name
Test status
Simulation time 73940931722 ps
CPU time 190.72 seconds
Started Jun 26 04:55:30 PM PDT 24
Finished Jun 26 04:58:48 PM PDT 24
Peak memory 201688 kb
Host smart-3c8f8e1c-2dd2-42d9-bb4f-95e5afc9b8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596522338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_w
ith_pre_cond.2596522338
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1004288496
Short name T291
Test name
Test status
Simulation time 25019458203 ps
CPU time 120.28 seconds
Started Jun 26 04:35:15 PM PDT 24
Finished Jun 26 04:37:18 PM PDT 24
Peak memory 202156 kb
Host smart-3cb351e0-92c7-4046-9591-b0de2dc7da82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004288496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_bit_bash.1004288496
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1571749834
Short name T134
Test name
Test status
Simulation time 167519081000 ps
CPU time 109.39 seconds
Started Jun 26 04:53:51 PM PDT 24
Finished Jun 26 04:55:43 PM PDT 24
Peak memory 210112 kb
Host smart-98452407-cc7f-4888-a58f-8b1b8bc0eb71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571749834 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.1571749834
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.265901564
Short name T277
Test name
Test status
Simulation time 69412997955 ps
CPU time 24.82 seconds
Started Jun 26 04:54:00 PM PDT 24
Finished Jun 26 04:54:28 PM PDT 24
Peak memory 210160 kb
Host smart-f809f6e5-aa44-459a-96fc-9468d601e897
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265901564 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.265901564
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.298442614
Short name T80
Test name
Test status
Simulation time 3097887548 ps
CPU time 4.54 seconds
Started Jun 26 04:54:23 PM PDT 24
Finished Jun 26 04:54:29 PM PDT 24
Peak memory 201392 kb
Host smart-0879d853-ac2e-4a5d-9e99-f1ed2c608931
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298442614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctr
l_edge_detect.298442614
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.3128398664
Short name T104
Test name
Test status
Simulation time 227944457765 ps
CPU time 67.5 seconds
Started Jun 26 04:54:31 PM PDT 24
Finished Jun 26 04:55:41 PM PDT 24
Peak memory 218312 kb
Host smart-1809f049-b5c1-4daf-88a9-559c22707322
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128398664 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.3128398664
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.3199432225
Short name T213
Test name
Test status
Simulation time 3238924887 ps
CPU time 2.6 seconds
Started Jun 26 04:54:08 PM PDT 24
Finished Jun 26 04:54:14 PM PDT 24
Peak memory 201496 kb
Host smart-cadab810-e8c5-4acb-bf1f-d72504a56dbc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199432225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_edge_detect.3199432225
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.139732204
Short name T194
Test name
Test status
Simulation time 215314896394 ps
CPU time 77.56 seconds
Started Jun 26 04:55:28 PM PDT 24
Finished Jun 26 04:56:51 PM PDT 24
Peak memory 210220 kb
Host smart-1a00db25-bdd9-4574-958d-9395b3153738
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139732204 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.139732204
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.238725227
Short name T290
Test name
Test status
Simulation time 2145190974 ps
CPU time 4.44 seconds
Started Jun 26 04:35:40 PM PDT 24
Finished Jun 26 04:35:48 PM PDT 24
Peak memory 201912 kb
Host smart-e8c73526-5e4f-477b-bf84-e1fa2652b5aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238725227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors
.238725227
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.2419030918
Short name T179
Test name
Test status
Simulation time 16533567158 ps
CPU time 10.72 seconds
Started Jun 26 04:54:20 PM PDT 24
Finished Jun 26 04:54:32 PM PDT 24
Peak memory 201548 kb
Host smart-0c373631-e05d-4b17-8050-372629a0fad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419030918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.2419030918
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.3152062118
Short name T229
Test name
Test status
Simulation time 2922752954 ps
CPU time 2.59 seconds
Started Jun 26 04:54:46 PM PDT 24
Finished Jun 26 04:54:50 PM PDT 24
Peak memory 201416 kb
Host smart-5b2bee43-4219-4638-8b6a-3c3d0edc9aa2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152062118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.3152062118
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.3984654009
Short name T285
Test name
Test status
Simulation time 42012359047 ps
CPU time 105.9 seconds
Started Jun 26 04:53:38 PM PDT 24
Finished Jun 26 04:55:28 PM PDT 24
Peak memory 221220 kb
Host smart-f557b1fc-0c01-4f99-aa9d-0ed51bf2de64
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984654009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.3984654009
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2598996402
Short name T115
Test name
Test status
Simulation time 94478932444 ps
CPU time 62.45 seconds
Started Jun 26 04:53:54 PM PDT 24
Finished Jun 26 04:54:59 PM PDT 24
Peak memory 201776 kb
Host smart-e750dceb-666e-47cc-87e4-3ee9a97b43d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598996402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wi
th_pre_cond.2598996402
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.526189012
Short name T358
Test name
Test status
Simulation time 118757733971 ps
CPU time 156.19 seconds
Started Jun 26 04:54:29 PM PDT 24
Finished Jun 26 04:57:08 PM PDT 24
Peak memory 201660 kb
Host smart-1ed62760-fcb5-4ca9-b22d-2dfdb6e2b198
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526189012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_combo_detect.526189012
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.1001559441
Short name T3
Test name
Test status
Simulation time 4748124703 ps
CPU time 6.94 seconds
Started Jun 26 04:54:06 PM PDT 24
Finished Jun 26 04:54:16 PM PDT 24
Peak memory 201464 kb
Host smart-53833fc9-2b5d-4777-8dfd-7997699608a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001559441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.1001559441
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1561774851
Short name T181
Test name
Test status
Simulation time 92701422354 ps
CPU time 224.5 seconds
Started Jun 26 04:55:16 PM PDT 24
Finished Jun 26 04:59:04 PM PDT 24
Peak memory 201896 kb
Host smart-7f7867b6-aa99-41df-90b4-70601bc961a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561774851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_w
ith_pre_cond.1561774851
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.1004643390
Short name T122
Test name
Test status
Simulation time 88269539867 ps
CPU time 33.77 seconds
Started Jun 26 04:54:19 PM PDT 24
Finished Jun 26 04:54:54 PM PDT 24
Peak memory 210256 kb
Host smart-d4f64e3b-388f-4dbe-ac5f-64eeb656d870
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004643390 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.1004643390
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.30027887
Short name T360
Test name
Test status
Simulation time 173161968514 ps
CPU time 80.67 seconds
Started Jun 26 04:54:02 PM PDT 24
Finished Jun 26 04:55:26 PM PDT 24
Peak memory 201812 kb
Host smart-c60de9ce-9aba-4789-9d9f-a7ba3d0edf94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30027887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctr
l_combo_detect.30027887
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1812192670
Short name T140
Test name
Test status
Simulation time 903981627160 ps
CPU time 77.94 seconds
Started Jun 26 04:53:44 PM PDT 24
Finished Jun 26 04:55:07 PM PDT 24
Peak memory 218296 kb
Host smart-1494e399-b343-49a4-984b-7cdf7c346f8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812192670 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.1812192670
Directory /workspace/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.1494123568
Short name T18
Test name
Test status
Simulation time 10219061885 ps
CPU time 35.23 seconds
Started Jun 26 04:35:31 PM PDT 24
Finished Jun 26 04:36:12 PM PDT 24
Peak memory 202092 kb
Host smart-6f95eb13-1cdf-438f-863c-1fbec5114c27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494123568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.1494123568
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.207506758
Short name T368
Test name
Test status
Simulation time 157856191414 ps
CPU time 208.48 seconds
Started Jun 26 04:54:29 PM PDT 24
Finished Jun 26 04:58:00 PM PDT 24
Peak memory 201712 kb
Host smart-ca78d93e-dbf8-4648-9758-cf8125ebbf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207506758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_wi
th_pre_cond.207506758
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.740247882
Short name T303
Test name
Test status
Simulation time 42584267781 ps
CPU time 54.81 seconds
Started Jun 26 04:35:15 PM PDT 24
Finished Jun 26 04:36:12 PM PDT 24
Peak memory 202216 kb
Host smart-3be657f3-2f6a-4537-bb0e-28361c2c93ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740247882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_tl_intg_err.740247882
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.3059882047
Short name T378
Test name
Test status
Simulation time 85610822762 ps
CPU time 58.48 seconds
Started Jun 26 04:55:06 PM PDT 24
Finished Jun 26 04:56:09 PM PDT 24
Peak memory 202028 kb
Host smart-df8cc475-5b12-48f3-b295-d4522359b693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059882047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w
ith_pre_cond.3059882047
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2400314275
Short name T264
Test name
Test status
Simulation time 60048176576 ps
CPU time 141.77 seconds
Started Jun 26 04:54:17 PM PDT 24
Finished Jun 26 04:56:40 PM PDT 24
Peak memory 218272 kb
Host smart-ab6e16e2-f56a-4f48-b0fd-def576643d99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400314275 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.2400314275
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.3191180367
Short name T4
Test name
Test status
Simulation time 157193636932 ps
CPU time 108.79 seconds
Started Jun 26 04:54:38 PM PDT 24
Finished Jun 26 04:56:30 PM PDT 24
Peak memory 201688 kb
Host smart-ff5e3bc3-66d9-4522-a2ef-f45d9fad72b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191180367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_combo_detect.3191180367
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1647466360
Short name T369
Test name
Test status
Simulation time 80365421206 ps
CPU time 188.23 seconds
Started Jun 26 04:53:52 PM PDT 24
Finished Jun 26 04:57:03 PM PDT 24
Peak memory 201736 kb
Host smart-5f9de69c-6526-48c9-807a-06974c462db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647466360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_w
ith_pre_cond.1647466360
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.4082334437
Short name T383
Test name
Test status
Simulation time 520017143410 ps
CPU time 21.9 seconds
Started Jun 26 04:54:15 PM PDT 24
Finished Jun 26 04:54:38 PM PDT 24
Peak memory 201844 kb
Host smart-c5e56d1b-3d47-4cbc-81c8-66e6e04c1244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082334437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_s
tress_all.4082334437
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.3931909554
Short name T363
Test name
Test status
Simulation time 85358197400 ps
CPU time 25.47 seconds
Started Jun 26 04:54:15 PM PDT 24
Finished Jun 26 04:54:43 PM PDT 24
Peak memory 201748 kb
Host smart-aab79907-3228-4287-9ff1-5da40b5c529c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931909554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_combo_detect.3931909554
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.2625123955
Short name T361
Test name
Test status
Simulation time 132555370089 ps
CPU time 178.76 seconds
Started Jun 26 04:54:24 PM PDT 24
Finished Jun 26 04:57:25 PM PDT 24
Peak memory 201696 kb
Host smart-4378cc89-346e-4e63-9189-ebbc9a9d1e64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625123955 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.2625123955
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3391786639
Short name T395
Test name
Test status
Simulation time 201752720967 ps
CPU time 372.63 seconds
Started Jun 26 04:54:37 PM PDT 24
Finished Jun 26 05:00:53 PM PDT 24
Peak memory 201792 kb
Host smart-fdf04433-520e-4fed-ad86-f24cae72dfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391786639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w
ith_pre_cond.3391786639
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.852454698
Short name T392
Test name
Test status
Simulation time 96629121440 ps
CPU time 62.69 seconds
Started Jun 26 04:55:35 PM PDT 24
Finished Jun 26 04:56:43 PM PDT 24
Peak memory 201800 kb
Host smart-30e8c4c1-d932-41b6-86d3-0ce75451addd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852454698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_wi
th_pre_cond.852454698
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.685847566
Short name T731
Test name
Test status
Simulation time 47053425021 ps
CPU time 9.19 seconds
Started Jun 26 04:53:50 PM PDT 24
Finished Jun 26 04:54:03 PM PDT 24
Peak memory 201804 kb
Host smart-27aeba99-3df7-4fb5-9148-ced7cde6d1e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685847566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_combo_detect.685847566
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3585791916
Short name T299
Test name
Test status
Simulation time 3747689390 ps
CPU time 2.5 seconds
Started Jun 26 04:35:20 PM PDT 24
Finished Jun 26 04:35:28 PM PDT 24
Peak memory 202080 kb
Host smart-d83ebea4-564c-4447-bb82-32ba261e7ce8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585791916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.3585791916
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.2267868106
Short name T255
Test name
Test status
Simulation time 119759821721 ps
CPU time 50.64 seconds
Started Jun 26 04:54:07 PM PDT 24
Finished Jun 26 04:55:00 PM PDT 24
Peak memory 201884 kb
Host smart-6b929796-0360-470c-a9a5-4554d0edbbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267868106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_w
ith_pre_cond.2267868106
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.299077900
Short name T239
Test name
Test status
Simulation time 5012376397 ps
CPU time 1.85 seconds
Started Jun 26 04:54:25 PM PDT 24
Finished Jun 26 04:54:29 PM PDT 24
Peak memory 201512 kb
Host smart-27aaa3e6-ec65-48d5-b65a-072601166e3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299077900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctr
l_edge_detect.299077900
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.3353019077
Short name T151
Test name
Test status
Simulation time 4383298030 ps
CPU time 2.7 seconds
Started Jun 26 04:54:39 PM PDT 24
Finished Jun 26 04:54:44 PM PDT 24
Peak memory 201556 kb
Host smart-eab15ee7-51e6-427a-a21a-0850024aaddf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353019077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_edge_detect.3353019077
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.120595518
Short name T163
Test name
Test status
Simulation time 51567940839 ps
CPU time 130.71 seconds
Started Jun 26 04:55:30 PM PDT 24
Finished Jun 26 04:57:48 PM PDT 24
Peak memory 210092 kb
Host smart-3aefe51d-b1f3-42ba-8ec4-6aa313245663
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120595518 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.120595518
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3366462201
Short name T353
Test name
Test status
Simulation time 4035974370 ps
CPU time 10.23 seconds
Started Jun 26 04:35:29 PM PDT 24
Finished Jun 26 04:35:45 PM PDT 24
Peak memory 201824 kb
Host smart-9b7d14ae-1783-4578-abb8-7c35d44bdef2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366462201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.3366462201
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.978389596
Short name T71
Test name
Test status
Simulation time 64832837181 ps
CPU time 45.5 seconds
Started Jun 26 04:54:09 PM PDT 24
Finished Jun 26 04:54:57 PM PDT 24
Peak memory 201732 kb
Host smart-203b18d8-8826-4682-b83e-6da08b98e015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978389596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_wi
th_pre_cond.978389596
Directory /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.921543244
Short name T136
Test name
Test status
Simulation time 853704981631 ps
CPU time 99.62 seconds
Started Jun 26 04:53:58 PM PDT 24
Finished Jun 26 04:55:41 PM PDT 24
Peak memory 210000 kb
Host smart-a179a0b6-980d-4c9e-92db-7962e8be69e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921543244 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.921543244
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1336065482
Short name T74
Test name
Test status
Simulation time 41421835681 ps
CPU time 7.11 seconds
Started Jun 26 04:54:32 PM PDT 24
Finished Jun 26 04:54:43 PM PDT 24
Peak memory 201736 kb
Host smart-b853a595-0666-4d3b-a607-78b58fece4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336065482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w
ith_pre_cond.1336065482
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.1224265157
Short name T330
Test name
Test status
Simulation time 50354625914 ps
CPU time 66.16 seconds
Started Jun 26 04:55:28 PM PDT 24
Finished Jun 26 04:56:40 PM PDT 24
Peak memory 201780 kb
Host smart-d81eb060-9aa5-423a-ae9f-33d4612c6534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224265157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_w
ith_pre_cond.1224265157
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.1742873831
Short name T371
Test name
Test status
Simulation time 179068446066 ps
CPU time 52.3 seconds
Started Jun 26 04:55:27 PM PDT 24
Finished Jun 26 04:56:23 PM PDT 24
Peak memory 201628 kb
Host smart-3f82e070-403c-4cbc-837c-5a66c50b883b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742873831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.1742873831
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3210541627
Short name T250
Test name
Test status
Simulation time 72799153052 ps
CPU time 51.78 seconds
Started Jun 26 04:55:39 PM PDT 24
Finished Jun 26 04:56:34 PM PDT 24
Peak memory 201764 kb
Host smart-3ab80725-52f1-4d47-b4c6-3a863d183065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210541627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.3210541627
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.2084028160
Short name T394
Test name
Test status
Simulation time 131950016960 ps
CPU time 342.76 seconds
Started Jun 26 04:55:46 PM PDT 24
Finished Jun 26 05:01:32 PM PDT 24
Peak memory 201868 kb
Host smart-cd2f688a-1dd7-4a33-9f49-f83152d17baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084028160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_w
ith_pre_cond.2084028160
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.1046082523
Short name T370
Test name
Test status
Simulation time 124114082595 ps
CPU time 207.92 seconds
Started Jun 26 04:55:45 PM PDT 24
Finished Jun 26 04:59:15 PM PDT 24
Peak memory 201820 kb
Host smart-044506c0-ad4b-4aaa-bb11-f834c49b839a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046082523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_w
ith_pre_cond.1046082523
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.2468283242
Short name T376
Test name
Test status
Simulation time 155973074908 ps
CPU time 91.57 seconds
Started Jun 26 04:55:56 PM PDT 24
Finished Jun 26 04:57:29 PM PDT 24
Peak memory 201752 kb
Host smart-e5feb856-6eef-433f-812b-f562ed911445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468283242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_w
ith_pre_cond.2468283242
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2792766139
Short name T307
Test name
Test status
Simulation time 2175640465 ps
CPU time 2.71 seconds
Started Jun 26 04:35:42 PM PDT 24
Finished Jun 26 04:35:49 PM PDT 24
Peak memory 210352 kb
Host smart-2c1a8071-722d-4a25-8c46-c8625c3dd393
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792766139 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2792766139
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.2795343411
Short name T217
Test name
Test status
Simulation time 57759180504 ps
CPU time 75.79 seconds
Started Jun 26 04:54:25 PM PDT 24
Finished Jun 26 04:55:44 PM PDT 24
Peak memory 210116 kb
Host smart-69e6a226-1ba2-4a1f-8de4-ed4dd1b00e66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795343411 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.2795343411
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.960350865
Short name T262
Test name
Test status
Simulation time 112265037833 ps
CPU time 19.3 seconds
Started Jun 26 04:54:33 PM PDT 24
Finished Jun 26 04:54:56 PM PDT 24
Peak memory 201780 kb
Host smart-5391f813-848c-49f3-a00c-f491aafa85e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960350865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_wi
th_pre_cond.960350865
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.815679209
Short name T345
Test name
Test status
Simulation time 2308468048 ps
CPU time 7.43 seconds
Started Jun 26 04:35:24 PM PDT 24
Finished Jun 26 04:35:38 PM PDT 24
Peak memory 201660 kb
Host smart-4337d501-966c-45f7-a2d0-71aba7bc27b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815679209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_
csr_aliasing.815679209
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.696744282
Short name T346
Test name
Test status
Simulation time 67698284200 ps
CPU time 166.49 seconds
Started Jun 26 04:35:15 PM PDT 24
Finished Jun 26 04:38:03 PM PDT 24
Peak memory 202068 kb
Host smart-af271566-2f6e-4b9a-94ad-ae9e0bc83ea0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696744282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_
csr_bit_bash.696744282
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2403185352
Short name T868
Test name
Test status
Simulation time 6012131833 ps
CPU time 15.17 seconds
Started Jun 26 04:35:17 PM PDT 24
Finished Jun 26 04:35:37 PM PDT 24
Peak memory 201904 kb
Host smart-17aa3fa2-9363-485d-b4b4-f50adbbd81dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403185352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.2403185352
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2116912717
Short name T29
Test name
Test status
Simulation time 2147158915 ps
CPU time 6.25 seconds
Started Jun 26 04:35:14 PM PDT 24
Finished Jun 26 04:35:22 PM PDT 24
Peak memory 201848 kb
Host smart-e4418e63-787c-48aa-ad29-09a714a1b0bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116912717 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2116912717
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.64550110
Short name T343
Test name
Test status
Simulation time 2169514803 ps
CPU time 1.65 seconds
Started Jun 26 04:35:15 PM PDT 24
Finished Jun 26 04:35:19 PM PDT 24
Peak memory 201828 kb
Host smart-3b2becf1-0e30-47c6-8646-ee0d04eaa60b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64550110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_rw.64550110
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1661676171
Short name T854
Test name
Test status
Simulation time 2014403990 ps
CPU time 3.87 seconds
Started Jun 26 04:35:30 PM PDT 24
Finished Jun 26 04:35:39 PM PDT 24
Peak memory 201528 kb
Host smart-53fcc9de-4305-49d0-b5a0-3fb345197c76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661676171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_tes
t.1661676171
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.337404835
Short name T879
Test name
Test status
Simulation time 5580018780 ps
CPU time 6.45 seconds
Started Jun 26 04:35:30 PM PDT 24
Finished Jun 26 04:35:42 PM PDT 24
Peak memory 202108 kb
Host smart-1e9fb944-a72e-4e26-ba79-5310805b1f12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337404835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
sysrst_ctrl_same_csr_outstanding.337404835
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.203410649
Short name T304
Test name
Test status
Simulation time 42599923193 ps
CPU time 58.33 seconds
Started Jun 26 04:35:09 PM PDT 24
Finished Jun 26 04:36:09 PM PDT 24
Peak memory 202168 kb
Host smart-a7d1b6a9-e52c-49d8-a6d5-d1cd83b4e9ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203410649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_tl_intg_err.203410649
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2959405633
Short name T901
Test name
Test status
Simulation time 2517257771 ps
CPU time 7.82 seconds
Started Jun 26 04:35:18 PM PDT 24
Finished Jun 26 04:35:30 PM PDT 24
Peak memory 202004 kb
Host smart-14cea9ce-a4e3-48cf-b247-8b2101ad592c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959405633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.2959405633
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.4143248099
Short name T31
Test name
Test status
Simulation time 38972055231 ps
CPU time 171.32 seconds
Started Jun 26 04:35:18 PM PDT 24
Finished Jun 26 04:38:14 PM PDT 24
Peak memory 202112 kb
Host smart-9ce3b52c-f44e-4bb2-9846-d6c3ac5c6d88
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143248099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_bit_bash.4143248099
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2753148241
Short name T337
Test name
Test status
Simulation time 6077721358 ps
CPU time 4.36 seconds
Started Jun 26 04:35:27 PM PDT 24
Finished Jun 26 04:35:37 PM PDT 24
Peak memory 201552 kb
Host smart-d5aab0ae-235b-4cfa-b7c3-2935ab130db4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753148241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.2753148241
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3442618092
Short name T915
Test name
Test status
Simulation time 2042554476 ps
CPU time 2.25 seconds
Started Jun 26 04:35:31 PM PDT 24
Finished Jun 26 04:35:39 PM PDT 24
Peak memory 201676 kb
Host smart-fbbc156d-d404-4d55-89f5-72ee57481b66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442618092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.3442618092
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.199413386
Short name T873
Test name
Test status
Simulation time 2018284724 ps
CPU time 5.31 seconds
Started Jun 26 04:35:36 PM PDT 24
Finished Jun 26 04:35:45 PM PDT 24
Peak memory 201516 kb
Host smart-872f0040-464f-4f58-b007-493f01504889
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199413386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test
.199413386
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3834591923
Short name T881
Test name
Test status
Simulation time 5389165185 ps
CPU time 4.49 seconds
Started Jun 26 04:35:18 PM PDT 24
Finished Jun 26 04:35:33 PM PDT 24
Peak memory 202480 kb
Host smart-e2b1ae3a-aac9-4bc0-9126-c5658bb7c0a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834591923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.3834591923
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2583795624
Short name T309
Test name
Test status
Simulation time 2099547821 ps
CPU time 2.33 seconds
Started Jun 26 04:35:31 PM PDT 24
Finished Jun 26 04:35:39 PM PDT 24
Peak memory 201872 kb
Host smart-5dc84490-786c-43b2-9e3a-0acb286ac966
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583795624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error
s.2583795624
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.928136177
Short name T293
Test name
Test status
Simulation time 22455202351 ps
CPU time 16.75 seconds
Started Jun 26 04:35:33 PM PDT 24
Finished Jun 26 04:35:55 PM PDT 24
Peak memory 202108 kb
Host smart-2218f662-2cbe-42e3-8e7f-8cd75b1d6591
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928136177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_tl_intg_err.928136177
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.252625511
Short name T305
Test name
Test status
Simulation time 2091551314 ps
CPU time 3.63 seconds
Started Jun 26 04:35:21 PM PDT 24
Finished Jun 26 04:35:31 PM PDT 24
Peak memory 201872 kb
Host smart-460abd3f-a6c5-4d27-b771-f72c4b5b73a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252625511 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.252625511
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.4188383414
Short name T57
Test name
Test status
Simulation time 2045464941 ps
CPU time 3.31 seconds
Started Jun 26 04:35:23 PM PDT 24
Finished Jun 26 04:35:32 PM PDT 24
Peak memory 201824 kb
Host smart-bb8cf3a9-58b3-4da1-b16a-76caa970f177
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188383414 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.4188383414
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1712148290
Short name T827
Test name
Test status
Simulation time 2058721687 ps
CPU time 1.22 seconds
Started Jun 26 04:35:15 PM PDT 24
Finished Jun 26 04:35:18 PM PDT 24
Peak memory 201548 kb
Host smart-c9fa823b-65e2-4747-9f4e-a972014bc880
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712148290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.1712148290
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3283043132
Short name T875
Test name
Test status
Simulation time 8283629908 ps
CPU time 6.36 seconds
Started Jun 26 04:35:28 PM PDT 24
Finished Jun 26 04:35:40 PM PDT 24
Peak memory 202140 kb
Host smart-228d5520-d309-4c83-b203-d4e6df65f9f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283043132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.sysrst_ctrl_same_csr_outstanding.3283043132
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1593791898
Short name T292
Test name
Test status
Simulation time 3109034626 ps
CPU time 2.19 seconds
Started Jun 26 04:35:18 PM PDT 24
Finished Jun 26 04:35:24 PM PDT 24
Peak memory 202148 kb
Host smart-6ecf9ced-5959-4c34-bb26-cf3edbaef070
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593791898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_erro
rs.1593791898
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1243818922
Short name T841
Test name
Test status
Simulation time 42493837225 ps
CPU time 32.15 seconds
Started Jun 26 04:35:23 PM PDT 24
Finished Jun 26 04:36:01 PM PDT 24
Peak memory 201320 kb
Host smart-ad34087b-1920-4a7e-a7cc-0872bce3bf2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243818922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.1243818922
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1532931195
Short name T896
Test name
Test status
Simulation time 2216755941 ps
CPU time 2.46 seconds
Started Jun 26 04:35:22 PM PDT 24
Finished Jun 26 04:35:30 PM PDT 24
Peak memory 202036 kb
Host smart-b36f3b18-4bf9-4d61-bc04-d8bd89177cf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532931195 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1532931195
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.822723523
Short name T833
Test name
Test status
Simulation time 2052889426 ps
CPU time 3.4 seconds
Started Jun 26 04:35:32 PM PDT 24
Finished Jun 26 04:35:41 PM PDT 24
Peak memory 201688 kb
Host smart-f021b8b6-08d0-4a3c-8a06-56e2e41fff43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822723523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_r
w.822723523
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.4188929951
Short name T809
Test name
Test status
Simulation time 2015135915 ps
CPU time 5.52 seconds
Started Jun 26 04:35:31 PM PDT 24
Finished Jun 26 04:35:42 PM PDT 24
Peak memory 201516 kb
Host smart-fb439712-9085-4787-a4d3-fa257657d2fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188929951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_te
st.4188929951
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2180982637
Short name T890
Test name
Test status
Simulation time 6205627772 ps
CPU time 13.92 seconds
Started Jun 26 04:35:30 PM PDT 24
Finished Jun 26 04:35:49 PM PDT 24
Peak memory 202152 kb
Host smart-c7a6dde4-e75d-4348-89b5-30fffe95d474
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180982637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.sysrst_ctrl_same_csr_outstanding.2180982637
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2177833941
Short name T911
Test name
Test status
Simulation time 2172414586 ps
CPU time 3.02 seconds
Started Jun 26 04:35:35 PM PDT 24
Finished Jun 26 04:35:43 PM PDT 24
Peak memory 202092 kb
Host smart-2c207eb6-d1df-4ad6-a6e9-d6356f903e89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177833941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_erro
rs.2177833941
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3133762005
Short name T306
Test name
Test status
Simulation time 42820417968 ps
CPU time 28.64 seconds
Started Jun 26 04:35:32 PM PDT 24
Finished Jun 26 04:36:10 PM PDT 24
Peak memory 202108 kb
Host smart-e12376f9-c039-4fa7-9519-61f7acfb7880
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133762005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.3133762005
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.737887838
Short name T880
Test name
Test status
Simulation time 2069208533 ps
CPU time 5.62 seconds
Started Jun 26 04:35:31 PM PDT 24
Finished Jun 26 04:35:42 PM PDT 24
Peak memory 201764 kb
Host smart-3d416a84-5723-4008-a4a2-c808dd08d4b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737887838 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.737887838
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.659280904
Short name T348
Test name
Test status
Simulation time 2054998704 ps
CPU time 2 seconds
Started Jun 26 04:35:33 PM PDT 24
Finished Jun 26 04:35:40 PM PDT 24
Peak memory 201668 kb
Host smart-3a6de91f-bf26-4dcd-9383-234f6df77192
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659280904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_r
w.659280904
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2698928655
Short name T910
Test name
Test status
Simulation time 2157964873 ps
CPU time 0.9 seconds
Started Jun 26 04:35:31 PM PDT 24
Finished Jun 26 04:35:38 PM PDT 24
Peak memory 201816 kb
Host smart-a4edac8f-33b5-4a15-93b9-0a115f2bf4a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698928655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.2698928655
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3926189609
Short name T815
Test name
Test status
Simulation time 4643751726 ps
CPU time 8.35 seconds
Started Jun 26 04:35:40 PM PDT 24
Finished Jun 26 04:35:52 PM PDT 24
Peak memory 202112 kb
Host smart-ea1ac2f2-b36a-4ede-8089-c380200f3f69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926189609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.3926189609
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.704810477
Short name T289
Test name
Test status
Simulation time 2043653399 ps
CPU time 6.59 seconds
Started Jun 26 04:35:25 PM PDT 24
Finished Jun 26 04:35:38 PM PDT 24
Peak memory 201964 kb
Host smart-76b2f673-003e-4f0d-b3f2-cd025b141528
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704810477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_error
s.704810477
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1165769129
Short name T283
Test name
Test status
Simulation time 22335916584 ps
CPU time 28.2 seconds
Started Jun 26 04:35:22 PM PDT 24
Finished Jun 26 04:35:57 PM PDT 24
Peak memory 202092 kb
Host smart-a3edc072-bc2c-43b6-ba5a-6332f2d04f89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165769129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_tl_intg_err.1165769129
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1470012353
Short name T906
Test name
Test status
Simulation time 2070397054 ps
CPU time 6.09 seconds
Started Jun 26 04:35:34 PM PDT 24
Finished Jun 26 04:35:45 PM PDT 24
Peak memory 201776 kb
Host smart-fe69cde3-13a1-4a82-a658-461c98746fed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470012353 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1470012353
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1038991004
Short name T874
Test name
Test status
Simulation time 2040531764 ps
CPU time 5.98 seconds
Started Jun 26 04:35:37 PM PDT 24
Finished Jun 26 04:35:47 PM PDT 24
Peak memory 201692 kb
Host smart-dba94d3f-2e5c-41c1-8efb-4c1bc1b7a878
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038991004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_
rw.1038991004
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.856875134
Short name T916
Test name
Test status
Simulation time 2032661730 ps
CPU time 1.62 seconds
Started Jun 26 04:35:37 PM PDT 24
Finished Jun 26 04:35:42 PM PDT 24
Peak memory 201580 kb
Host smart-8f1be7d8-f6d3-4440-8a0a-797559a7e2a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856875134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_tes
t.856875134
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2983959944
Short name T20
Test name
Test status
Simulation time 10232670332 ps
CPU time 25.58 seconds
Started Jun 26 04:35:25 PM PDT 24
Finished Jun 26 04:35:57 PM PDT 24
Peak memory 202160 kb
Host smart-ef1f840b-bffc-4f93-b842-4d22ffaa6952
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983959944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.2983959944
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.594411416
Short name T296
Test name
Test status
Simulation time 2180331201 ps
CPU time 3.81 seconds
Started Jun 26 04:35:27 PM PDT 24
Finished Jun 26 04:35:37 PM PDT 24
Peak memory 202148 kb
Host smart-b0a20529-bd2c-4220-8a71-c4157054c2d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594411416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_error
s.594411416
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2435779751
Short name T288
Test name
Test status
Simulation time 42602589839 ps
CPU time 56.28 seconds
Started Jun 26 04:35:36 PM PDT 24
Finished Jun 26 04:36:37 PM PDT 24
Peak memory 202156 kb
Host smart-2480fb41-e63f-410c-ae43-919919d4f899
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435779751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_tl_intg_err.2435779751
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.4190005388
Short name T866
Test name
Test status
Simulation time 2120396830 ps
CPU time 6.61 seconds
Started Jun 26 04:35:24 PM PDT 24
Finished Jun 26 04:35:37 PM PDT 24
Peak memory 201864 kb
Host smart-020409cd-c43b-4cae-9323-7cfeaac0e743
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190005388 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.4190005388
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2814933773
Short name T347
Test name
Test status
Simulation time 2081661184 ps
CPU time 2.12 seconds
Started Jun 26 04:35:24 PM PDT 24
Finished Jun 26 04:35:32 PM PDT 24
Peak memory 201664 kb
Host smart-831c651b-91b3-4130-90aa-d3d84ede019b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814933773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_
rw.2814933773
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2566964797
Short name T805
Test name
Test status
Simulation time 2028490107 ps
CPU time 3.18 seconds
Started Jun 26 04:35:42 PM PDT 24
Finished Jun 26 04:35:49 PM PDT 24
Peak memory 201752 kb
Host smart-516df934-dcd2-4dff-81f1-ecc42400a9fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566964797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.2566964797
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.992334512
Short name T845
Test name
Test status
Simulation time 5311737514 ps
CPU time 2.12 seconds
Started Jun 26 04:35:35 PM PDT 24
Finished Jun 26 04:35:42 PM PDT 24
Peak memory 202052 kb
Host smart-096e3781-1cf0-45f3-a5b5-a90d13a31ec8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992334512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.sysrst_ctrl_same_csr_outstanding.992334512
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1225765
Short name T298
Test name
Test status
Simulation time 2136281656 ps
CPU time 2.2 seconds
Started Jun 26 04:35:28 PM PDT 24
Finished Jun 26 04:35:36 PM PDT 24
Peak memory 201964 kb
Host smart-2792c641-b36f-4e77-8655-e3437ae7e001
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_errors.1225765
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1073513892
Short name T912
Test name
Test status
Simulation time 22400396097 ps
CPU time 20.86 seconds
Started Jun 26 04:35:36 PM PDT 24
Finished Jun 26 04:36:01 PM PDT 24
Peak memory 202180 kb
Host smart-ad8023ae-7ad7-47d7-bcd9-3efdf75e74a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073513892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_tl_intg_err.1073513892
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2374394280
Short name T870
Test name
Test status
Simulation time 2246562406 ps
CPU time 1.3 seconds
Started Jun 26 04:35:27 PM PDT 24
Finished Jun 26 04:35:34 PM PDT 24
Peak memory 201904 kb
Host smart-1263083c-c9fd-4fea-9482-030aa663191a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374394280 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2374394280
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2143092752
Short name T340
Test name
Test status
Simulation time 2063175880 ps
CPU time 3.3 seconds
Started Jun 26 04:35:24 PM PDT 24
Finished Jun 26 04:35:34 PM PDT 24
Peak memory 201828 kb
Host smart-ecf03c45-6d0d-429f-b18a-3239b1941478
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143092752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_
rw.2143092752
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.185051379
Short name T810
Test name
Test status
Simulation time 2031660175 ps
CPU time 1.96 seconds
Started Jun 26 04:35:39 PM PDT 24
Finished Jun 26 04:35:44 PM PDT 24
Peak memory 201704 kb
Host smart-3b365501-e47d-4cce-920b-e950eb0e5b0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185051379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_tes
t.185051379
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3353336942
Short name T897
Test name
Test status
Simulation time 10494880035 ps
CPU time 7.34 seconds
Started Jun 26 04:35:41 PM PDT 24
Finished Jun 26 04:35:52 PM PDT 24
Peak memory 202184 kb
Host smart-cba79ac7-2cba-4601-9bbb-dab86b043412
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353336942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.3353336942
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2939006530
Short name T825
Test name
Test status
Simulation time 2089563041 ps
CPU time 4.08 seconds
Started Jun 26 04:35:34 PM PDT 24
Finished Jun 26 04:35:43 PM PDT 24
Peak memory 202052 kb
Host smart-9ddd9b4e-f6a9-4b86-9ed6-28af98b1a93e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939006530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.2939006530
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3356095195
Short name T390
Test name
Test status
Simulation time 42373131742 ps
CPU time 116.36 seconds
Started Jun 26 04:35:24 PM PDT 24
Finished Jun 26 04:37:26 PM PDT 24
Peak memory 202164 kb
Host smart-87052a4a-3e57-41fd-8ef8-b6aed1055dcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356095195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_tl_intg_err.3356095195
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2554893048
Short name T823
Test name
Test status
Simulation time 2444718130 ps
CPU time 1.15 seconds
Started Jun 26 04:35:38 PM PDT 24
Finished Jun 26 04:35:43 PM PDT 24
Peak memory 201840 kb
Host smart-7bdde08f-e70a-4d9b-a0d3-75b31e7ba1dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554893048 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2554893048
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.4290113206
Short name T863
Test name
Test status
Simulation time 2036447289 ps
CPU time 5.04 seconds
Started Jun 26 04:35:24 PM PDT 24
Finished Jun 26 04:35:35 PM PDT 24
Peak memory 201712 kb
Host smart-690933ec-374c-436b-8267-05c94d7a3abd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290113206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.4290113206
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.776356368
Short name T828
Test name
Test status
Simulation time 2012270572 ps
CPU time 5.89 seconds
Started Jun 26 04:35:31 PM PDT 24
Finished Jun 26 04:35:43 PM PDT 24
Peak memory 201536 kb
Host smart-27e9e052-2602-44cc-8a31-00c309875ff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776356368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_tes
t.776356368
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2087776735
Short name T19
Test name
Test status
Simulation time 7886705917 ps
CPU time 2.63 seconds
Started Jun 26 04:35:45 PM PDT 24
Finished Jun 26 04:35:52 PM PDT 24
Peak memory 202096 kb
Host smart-370c59d6-4fa0-40dd-a253-ef40ea2dfc6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087776735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_same_csr_outstanding.2087776735
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1663185946
Short name T871
Test name
Test status
Simulation time 2026309930 ps
CPU time 6.62 seconds
Started Jun 26 04:35:45 PM PDT 24
Finished Jun 26 04:35:55 PM PDT 24
Peak memory 202032 kb
Host smart-c8ea8222-0376-4359-bcaf-06af678fa773
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663185946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.1663185946
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1981367252
Short name T287
Test name
Test status
Simulation time 22491624659 ps
CPU time 16.15 seconds
Started Jun 26 04:35:32 PM PDT 24
Finished Jun 26 04:35:53 PM PDT 24
Peak memory 202152 kb
Host smart-38ad6bb5-2100-4028-9457-5dbff8d3e841
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981367252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.1981367252
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1716811620
Short name T812
Test name
Test status
Simulation time 2086373186 ps
CPU time 3.22 seconds
Started Jun 26 04:35:24 PM PDT 24
Finished Jun 26 04:35:34 PM PDT 24
Peak memory 201724 kb
Host smart-8bbe7a8f-39fc-4788-8215-c497720e01f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716811620 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1716811620
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2484180568
Short name T902
Test name
Test status
Simulation time 2048011533 ps
CPU time 2.86 seconds
Started Jun 26 04:35:23 PM PDT 24
Finished Jun 26 04:35:32 PM PDT 24
Peak memory 201812 kb
Host smart-682591a8-f40f-40d2-ba0c-0f74f6f8cc96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484180568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.2484180568
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2404667458
Short name T886
Test name
Test status
Simulation time 2008764304 ps
CPU time 5.94 seconds
Started Jun 26 04:35:46 PM PDT 24
Finished Jun 26 04:35:56 PM PDT 24
Peak memory 201600 kb
Host smart-0a7a6745-a90e-4b87-b28a-5db16d30dc1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404667458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_te
st.2404667458
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3465271175
Short name T865
Test name
Test status
Simulation time 5178182298 ps
CPU time 6.43 seconds
Started Jun 26 04:35:43 PM PDT 24
Finished Jun 26 04:35:53 PM PDT 24
Peak memory 202104 kb
Host smart-b26ae94a-883f-4384-8408-776b804e1a0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465271175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
7.sysrst_ctrl_same_csr_outstanding.3465271175
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.979554540
Short name T295
Test name
Test status
Simulation time 2441595171 ps
CPU time 3.71 seconds
Started Jun 26 04:35:32 PM PDT 24
Finished Jun 26 04:35:41 PM PDT 24
Peak memory 202088 kb
Host smart-e96006c8-8b7d-4dc3-893e-42a68bc23496
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979554540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_error
s.979554540
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1002524707
Short name T843
Test name
Test status
Simulation time 22309696340 ps
CPU time 10.21 seconds
Started Jun 26 04:35:24 PM PDT 24
Finished Jun 26 04:35:40 PM PDT 24
Peak memory 202112 kb
Host smart-0c4057c5-7c54-41d1-9706-2db6418a4701
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002524707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_tl_intg_err.1002524707
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2547279293
Short name T831
Test name
Test status
Simulation time 2080736939 ps
CPU time 3.56 seconds
Started Jun 26 04:35:34 PM PDT 24
Finished Jun 26 04:35:43 PM PDT 24
Peak memory 201844 kb
Host smart-9bbbc652-fb40-4ffa-9d56-cb8988bb8030
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547279293 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2547279293
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.1334643979
Short name T913
Test name
Test status
Simulation time 2129604068 ps
CPU time 2.2 seconds
Started Jun 26 04:35:25 PM PDT 24
Finished Jun 26 04:35:33 PM PDT 24
Peak memory 201812 kb
Host smart-e4addf0a-6242-496e-9667-7a1f856b8310
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334643979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_
rw.1334643979
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1185534146
Short name T834
Test name
Test status
Simulation time 2035796897 ps
CPU time 1.93 seconds
Started Jun 26 04:35:31 PM PDT 24
Finished Jun 26 04:35:39 PM PDT 24
Peak memory 202072 kb
Host smart-60caa1d2-c5af-4ca0-8e57-7e2480ea019c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185534146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_te
st.1185534146
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2239016947
Short name T856
Test name
Test status
Simulation time 9026066289 ps
CPU time 8.86 seconds
Started Jun 26 04:35:25 PM PDT 24
Finished Jun 26 04:35:39 PM PDT 24
Peak memory 202128 kb
Host smart-f3bac85e-2578-4268-86bc-180b87912f79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239016947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_same_csr_outstanding.2239016947
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2412045856
Short name T899
Test name
Test status
Simulation time 2499563220 ps
CPU time 2.72 seconds
Started Jun 26 04:35:43 PM PDT 24
Finished Jun 26 04:35:50 PM PDT 24
Peak memory 202136 kb
Host smart-4c8e5c4f-2773-4838-80fe-cb1b7c6ab767
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412045856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_erro
rs.2412045856
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3369432188
Short name T391
Test name
Test status
Simulation time 42805135523 ps
CPU time 30.56 seconds
Started Jun 26 04:35:40 PM PDT 24
Finished Jun 26 04:36:14 PM PDT 24
Peak memory 202168 kb
Host smart-36d4a396-c1b1-457b-847f-13f0233f8c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369432188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_tl_intg_err.3369432188
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1527197901
Short name T884
Test name
Test status
Simulation time 2071052667 ps
CPU time 3.46 seconds
Started Jun 26 04:35:31 PM PDT 24
Finished Jun 26 04:35:40 PM PDT 24
Peak memory 201884 kb
Host smart-9838cc2d-555f-4ab2-8783-e916ad20ff1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527197901 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1527197901
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.508353935
Short name T338
Test name
Test status
Simulation time 2065711334 ps
CPU time 6.15 seconds
Started Jun 26 04:35:42 PM PDT 24
Finished Jun 26 04:35:52 PM PDT 24
Peak memory 201780 kb
Host smart-2ded1e52-739e-4008-8f34-dd554315b786
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508353935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_r
w.508353935
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1421675246
Short name T914
Test name
Test status
Simulation time 2010467315 ps
CPU time 5.73 seconds
Started Jun 26 04:35:25 PM PDT 24
Finished Jun 26 04:35:37 PM PDT 24
Peak memory 201572 kb
Host smart-c9873daf-3602-4545-983b-1a7f3955c9be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421675246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.1421675246
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.751269346
Short name T891
Test name
Test status
Simulation time 4824455568 ps
CPU time 19.29 seconds
Started Jun 26 04:35:45 PM PDT 24
Finished Jun 26 04:36:09 PM PDT 24
Peak memory 201856 kb
Host smart-61fb860f-829b-46dd-8534-e8fea1b4657c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751269346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.sysrst_ctrl_same_csr_outstanding.751269346
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.957188174
Short name T837
Test name
Test status
Simulation time 2066162103 ps
CPU time 2.42 seconds
Started Jun 26 04:35:46 PM PDT 24
Finished Jun 26 04:35:53 PM PDT 24
Peak memory 201960 kb
Host smart-01d819f0-9b47-4295-846d-29f70d91ba3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957188174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_error
s.957188174
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.861668496
Short name T813
Test name
Test status
Simulation time 22279635169 ps
CPU time 14.93 seconds
Started Jun 26 04:35:40 PM PDT 24
Finished Jun 26 04:35:59 PM PDT 24
Peak memory 202180 kb
Host smart-db0ed8d1-f0cd-47fd-9e30-77d315fe4451
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861668496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_tl_intg_err.861668496
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2164898107
Short name T847
Test name
Test status
Simulation time 3196186933 ps
CPU time 9.58 seconds
Started Jun 26 04:35:26 PM PDT 24
Finished Jun 26 04:35:41 PM PDT 24
Peak memory 202004 kb
Host smart-2f39bf92-2b8f-4f8f-87e0-186b06f7ed62
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164898107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_aliasing.2164898107
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.298328653
Short name T895
Test name
Test status
Simulation time 2192455592 ps
CPU time 2.31 seconds
Started Jun 26 04:35:28 PM PDT 24
Finished Jun 26 04:35:36 PM PDT 24
Peak memory 201684 kb
Host smart-509f4f66-7f7b-459a-8100-5740cb786a4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298328653 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.298328653
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1666434594
Short name T860
Test name
Test status
Simulation time 2099309162 ps
CPU time 2.15 seconds
Started Jun 26 04:35:22 PM PDT 24
Finished Jun 26 04:35:30 PM PDT 24
Peak memory 201700 kb
Host smart-f049e62e-62b6-47d0-bf4d-6297e77b8d8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666434594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.1666434594
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.705466433
Short name T818
Test name
Test status
Simulation time 2071781605 ps
CPU time 1.22 seconds
Started Jun 26 04:35:19 PM PDT 24
Finished Jun 26 04:35:26 PM PDT 24
Peak memory 201972 kb
Host smart-8d2b9787-80b7-46af-84e1-d7a62c269171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705466433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test
.705466433
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2633268375
Short name T888
Test name
Test status
Simulation time 4466219526 ps
CPU time 11.22 seconds
Started Jun 26 04:36:13 PM PDT 24
Finished Jun 26 04:36:28 PM PDT 24
Peak memory 202040 kb
Host smart-f87be940-3944-4115-8d0c-0b0e93cb7ee8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633268375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.2633268375
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.3348065808
Short name T893
Test name
Test status
Simulation time 2065067400 ps
CPU time 7.26 seconds
Started Jun 26 04:35:21 PM PDT 24
Finished Jun 26 04:35:34 PM PDT 24
Peak memory 202028 kb
Host smart-0932783a-e522-48ee-8e53-58ca2d58d477
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348065808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error
s.3348065808
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.3135785585
Short name T887
Test name
Test status
Simulation time 2121750985 ps
CPU time 0.93 seconds
Started Jun 26 04:35:30 PM PDT 24
Finished Jun 26 04:35:36 PM PDT 24
Peak memory 201720 kb
Host smart-e3b7f48a-e83a-46aa-bd24-a9a73a85d8e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135785585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_te
st.3135785585
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1381439384
Short name T909
Test name
Test status
Simulation time 2022423948 ps
CPU time 4.35 seconds
Started Jun 26 04:35:24 PM PDT 24
Finished Jun 26 04:35:35 PM PDT 24
Peak memory 201536 kb
Host smart-15762b02-a43b-4a2e-a7d3-58d8e6463157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381439384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.1381439384
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3270595269
Short name T898
Test name
Test status
Simulation time 2013876796 ps
CPU time 5.41 seconds
Started Jun 26 04:35:33 PM PDT 24
Finished Jun 26 04:35:44 PM PDT 24
Peak memory 201680 kb
Host smart-fd1c8970-900a-44c0-986c-e006c4583f35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270595269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.3270595269
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.2333535802
Short name T851
Test name
Test status
Simulation time 2025644311 ps
CPU time 3.02 seconds
Started Jun 26 04:35:55 PM PDT 24
Finished Jun 26 04:36:02 PM PDT 24
Peak memory 201676 kb
Host smart-d5d74ca1-780a-4d3a-b018-0ebc0894b189
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333535802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.2333535802
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1468848887
Short name T885
Test name
Test status
Simulation time 2034373548 ps
CPU time 1.8 seconds
Started Jun 26 04:35:43 PM PDT 24
Finished Jun 26 04:35:49 PM PDT 24
Peak memory 201544 kb
Host smart-ec1bc7bd-bece-4505-b6f3-14c78f61f9eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468848887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_te
st.1468848887
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1451865790
Short name T904
Test name
Test status
Simulation time 2017086460 ps
CPU time 3.25 seconds
Started Jun 26 04:35:30 PM PDT 24
Finished Jun 26 04:35:39 PM PDT 24
Peak memory 201612 kb
Host smart-e015505d-2d0e-40c2-ad7d-2a3cd35f866c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451865790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te
st.1451865790
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.617598658
Short name T842
Test name
Test status
Simulation time 2034938783 ps
CPU time 1.29 seconds
Started Jun 26 04:35:39 PM PDT 24
Finished Jun 26 04:35:44 PM PDT 24
Peak memory 201500 kb
Host smart-4a5c4fc3-dec9-46c0-90e4-3b767b6b6ed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617598658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_tes
t.617598658
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.954737748
Short name T814
Test name
Test status
Simulation time 2015314542 ps
CPU time 5.31 seconds
Started Jun 26 04:35:28 PM PDT 24
Finished Jun 26 04:35:39 PM PDT 24
Peak memory 201700 kb
Host smart-762beef5-be09-4ae4-8c48-ed68dd8572cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954737748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_tes
t.954737748
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3509017833
Short name T848
Test name
Test status
Simulation time 2015894253 ps
CPU time 3.04 seconds
Started Jun 26 04:35:43 PM PDT 24
Finished Jun 26 04:35:50 PM PDT 24
Peak memory 201552 kb
Host smart-d2a88d65-7187-48ec-ad1b-a071db2d1945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509017833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_te
st.3509017833
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.2154519804
Short name T857
Test name
Test status
Simulation time 2017698600 ps
CPU time 3.06 seconds
Started Jun 26 04:35:38 PM PDT 24
Finished Jun 26 04:35:45 PM PDT 24
Peak memory 201556 kb
Host smart-ae3f05b7-f58a-4c2b-ba0c-82c10df903e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154519804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_te
st.2154519804
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.970247288
Short name T344
Test name
Test status
Simulation time 2180291032 ps
CPU time 3.41 seconds
Started Jun 26 04:35:25 PM PDT 24
Finished Jun 26 04:35:34 PM PDT 24
Peak memory 202124 kb
Host smart-1085cfa3-7f16-461c-bcde-ec7eb2deae95
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970247288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_
csr_aliasing.970247288
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3428435951
Short name T867
Test name
Test status
Simulation time 77053183286 ps
CPU time 36.24 seconds
Started Jun 26 04:35:31 PM PDT 24
Finished Jun 26 04:36:13 PM PDT 24
Peak memory 202092 kb
Host smart-31c3db10-67c1-4723-b3e3-ae4c1f9061e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428435951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_bit_bash.3428435951
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1096668089
Short name T835
Test name
Test status
Simulation time 4111355553 ps
CPU time 2.05 seconds
Started Jun 26 04:35:18 PM PDT 24
Finished Jun 26 04:35:24 PM PDT 24
Peak memory 201808 kb
Host smart-9f14abce-d8ec-403a-a248-2e4db4dc0298
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096668089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.1096668089
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1188603941
Short name T294
Test name
Test status
Simulation time 2229762489 ps
CPU time 2.49 seconds
Started Jun 26 04:35:44 PM PDT 24
Finished Jun 26 04:35:50 PM PDT 24
Peak memory 201968 kb
Host smart-be64553b-246d-48ea-aed9-71d6bc5cad12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188603941 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1188603941
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.3653087274
Short name T342
Test name
Test status
Simulation time 2037422244 ps
CPU time 6.13 seconds
Started Jun 26 04:35:13 PM PDT 24
Finished Jun 26 04:35:21 PM PDT 24
Peak memory 202104 kb
Host smart-8a4dc179-a3a1-439e-9d82-3bb8019f302d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653087274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.3653087274
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.512085784
Short name T852
Test name
Test status
Simulation time 2020638434 ps
CPU time 3.07 seconds
Started Jun 26 04:35:28 PM PDT 24
Finished Jun 26 04:35:37 PM PDT 24
Peak memory 201532 kb
Host smart-da7c9d49-91f3-4b8a-965c-216cf0a67ba4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512085784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_test
.512085784
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.4098271471
Short name T907
Test name
Test status
Simulation time 5349830044 ps
CPU time 21.29 seconds
Started Jun 26 04:35:26 PM PDT 24
Finished Jun 26 04:35:53 PM PDT 24
Peak memory 202052 kb
Host smart-fda6e378-7cfc-4100-820b-9794b8232e17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098271471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_same_csr_outstanding.4098271471
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.493376618
Short name T824
Test name
Test status
Simulation time 2437406596 ps
CPU time 1.95 seconds
Started Jun 26 04:35:23 PM PDT 24
Finished Jun 26 04:35:30 PM PDT 24
Peak memory 202104 kb
Host smart-b88cac99-b706-4308-a7d2-d2150ef085e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493376618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_errors
.493376618
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3719750583
Short name T817
Test name
Test status
Simulation time 22197734660 ps
CPU time 60.12 seconds
Started Jun 26 04:35:16 PM PDT 24
Finished Jun 26 04:36:20 PM PDT 24
Peak memory 202148 kb
Host smart-aaaf7759-530f-4e81-b5ce-ba5dd2c2c539
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719750583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.3719750583
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3714411778
Short name T832
Test name
Test status
Simulation time 2027336592 ps
CPU time 2.99 seconds
Started Jun 26 04:35:33 PM PDT 24
Finished Jun 26 04:35:41 PM PDT 24
Peak memory 201600 kb
Host smart-3d4c4207-355d-4240-bbaa-8a64ec97779e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714411778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_te
st.3714411778
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.3625866796
Short name T846
Test name
Test status
Simulation time 2062725740 ps
CPU time 1.65 seconds
Started Jun 26 04:35:32 PM PDT 24
Finished Jun 26 04:35:39 PM PDT 24
Peak memory 201544 kb
Host smart-8e4a7fea-1655-42c1-903d-a2099bb03306
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625866796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_te
st.3625866796
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2712327695
Short name T808
Test name
Test status
Simulation time 2023899357 ps
CPU time 3.25 seconds
Started Jun 26 04:35:26 PM PDT 24
Finished Jun 26 04:35:35 PM PDT 24
Peak memory 201588 kb
Host smart-52e73dec-b6bc-4459-a52e-f79a2d988f07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712327695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_te
st.2712327695
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1544554242
Short name T883
Test name
Test status
Simulation time 2103513332 ps
CPU time 1.17 seconds
Started Jun 26 04:35:37 PM PDT 24
Finished Jun 26 04:35:42 PM PDT 24
Peak memory 201540 kb
Host smart-491cfcef-c1b3-4e82-9ba2-91a4d3296412
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544554242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.1544554242
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3521840444
Short name T878
Test name
Test status
Simulation time 2028818167 ps
CPU time 3.31 seconds
Started Jun 26 04:35:34 PM PDT 24
Finished Jun 26 04:35:43 PM PDT 24
Peak memory 201528 kb
Host smart-45633001-109e-4a2f-8e05-1633727d9b69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521840444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_te
st.3521840444
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2279781162
Short name T822
Test name
Test status
Simulation time 2029643467 ps
CPU time 2.24 seconds
Started Jun 26 04:35:36 PM PDT 24
Finished Jun 26 04:35:43 PM PDT 24
Peak memory 201516 kb
Host smart-4c9dcf84-dfe3-49fc-b1fa-d366c8dea371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279781162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.2279781162
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1117838547
Short name T859
Test name
Test status
Simulation time 2011501065 ps
CPU time 5.75 seconds
Started Jun 26 04:35:37 PM PDT 24
Finished Jun 26 04:35:47 PM PDT 24
Peak memory 201720 kb
Host smart-b5cb487f-764f-4b94-9a78-d3930be5f3de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117838547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_te
st.1117838547
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3782574275
Short name T829
Test name
Test status
Simulation time 2013948407 ps
CPU time 5.94 seconds
Started Jun 26 04:35:24 PM PDT 24
Finished Jun 26 04:35:36 PM PDT 24
Peak memory 201500 kb
Host smart-5b726c90-76f8-4266-b2c2-07496d5e59bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782574275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_te
st.3782574275
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1122814903
Short name T826
Test name
Test status
Simulation time 2028581651 ps
CPU time 1.85 seconds
Started Jun 26 04:35:30 PM PDT 24
Finished Jun 26 04:35:37 PM PDT 24
Peak memory 201500 kb
Host smart-9270f1a1-068f-4925-9115-cdc97915f5af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122814903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_te
st.1122814903
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2490949182
Short name T816
Test name
Test status
Simulation time 2060226085 ps
CPU time 1.41 seconds
Started Jun 26 04:35:40 PM PDT 24
Finished Jun 26 04:35:45 PM PDT 24
Peak memory 201576 kb
Host smart-eaea0b04-5585-4b81-9b3f-781b5fec347d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490949182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_te
st.2490949182
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.871257767
Short name T341
Test name
Test status
Simulation time 2684486875 ps
CPU time 5.46 seconds
Started Jun 26 04:35:12 PM PDT 24
Finished Jun 26 04:35:19 PM PDT 24
Peak memory 202000 kb
Host smart-7783c3be-0ace-46ed-adac-1d9ccd123a18
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871257767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_aliasing.871257767
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2697312887
Short name T339
Test name
Test status
Simulation time 53947014349 ps
CPU time 248.32 seconds
Started Jun 26 04:35:20 PM PDT 24
Finished Jun 26 04:39:34 PM PDT 24
Peak memory 202108 kb
Host smart-8ef81841-cb56-4e1b-9b60-648c12229479
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697312887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.2697312887
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.2823947412
Short name T819
Test name
Test status
Simulation time 6037098174 ps
CPU time 4.83 seconds
Started Jun 26 04:35:27 PM PDT 24
Finished Jun 26 04:35:42 PM PDT 24
Peak memory 201924 kb
Host smart-a56ad34d-7d4e-40f6-a65b-42c799ed36c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823947412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_hw_reset.2823947412
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.999037958
Short name T839
Test name
Test status
Simulation time 2137987545 ps
CPU time 2.13 seconds
Started Jun 26 04:35:24 PM PDT 24
Finished Jun 26 04:35:32 PM PDT 24
Peak memory 201772 kb
Host smart-bde78ba4-674b-473a-8c1e-1d73f30b1acd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999037958 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.999037958
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3216226582
Short name T821
Test name
Test status
Simulation time 2081574683 ps
CPU time 2.14 seconds
Started Jun 26 04:35:12 PM PDT 24
Finished Jun 26 04:35:16 PM PDT 24
Peak memory 201792 kb
Host smart-57973aa8-b19c-4374-af72-cf4e770852b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216226582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r
w.3216226582
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.2139287588
Short name T877
Test name
Test status
Simulation time 2012482034 ps
CPU time 5.99 seconds
Started Jun 26 04:35:23 PM PDT 24
Finished Jun 26 04:35:35 PM PDT 24
Peak memory 201668 kb
Host smart-616f363b-a8ce-4fa7-a561-c5d7250db939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139287588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes
t.2139287588
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.3118010412
Short name T844
Test name
Test status
Simulation time 4536982120 ps
CPU time 11.04 seconds
Started Jun 26 04:35:22 PM PDT 24
Finished Jun 26 04:35:39 PM PDT 24
Peak memory 202120 kb
Host smart-e7723c78-2575-4bd7-a6ab-d868a5068f49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118010412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_same_csr_outstanding.3118010412
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.2995786436
Short name T301
Test name
Test status
Simulation time 42948980510 ps
CPU time 30.13 seconds
Started Jun 26 04:35:14 PM PDT 24
Finished Jun 26 04:35:46 PM PDT 24
Peak memory 202140 kb
Host smart-978ce711-5c99-4d9d-9eaf-582fb60d591a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995786436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_tl_intg_err.2995786436
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1961204806
Short name T908
Test name
Test status
Simulation time 2013190669 ps
CPU time 5.47 seconds
Started Jun 26 04:35:43 PM PDT 24
Finished Jun 26 04:35:53 PM PDT 24
Peak memory 201584 kb
Host smart-e62105a0-3216-4448-aee9-b552d8f12910
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961204806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_te
st.1961204806
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.1776816812
Short name T858
Test name
Test status
Simulation time 2012599491 ps
CPU time 5.84 seconds
Started Jun 26 04:35:36 PM PDT 24
Finished Jun 26 04:35:46 PM PDT 24
Peak memory 201692 kb
Host smart-f7b58d55-014e-4dfe-9a1a-575f48520916
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776816812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_te
st.1776816812
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1292137695
Short name T820
Test name
Test status
Simulation time 2010721286 ps
CPU time 5.65 seconds
Started Jun 26 04:35:30 PM PDT 24
Finished Jun 26 04:35:41 PM PDT 24
Peak memory 201540 kb
Host smart-7f35a291-ce17-4c05-95d3-437eebd36004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292137695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.1292137695
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.73574543
Short name T853
Test name
Test status
Simulation time 2010761092 ps
CPU time 5.88 seconds
Started Jun 26 04:35:41 PM PDT 24
Finished Jun 26 04:35:51 PM PDT 24
Peak memory 201736 kb
Host smart-ffe048cc-372d-4d24-9e87-513f40176ab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73574543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_test
.73574543
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2115510992
Short name T806
Test name
Test status
Simulation time 2041241686 ps
CPU time 1.97 seconds
Started Jun 26 04:35:30 PM PDT 24
Finished Jun 26 04:35:37 PM PDT 24
Peak memory 201700 kb
Host smart-7f28fff5-73e1-4a1f-b036-150e592a2ed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115510992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.2115510992
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.3397318921
Short name T869
Test name
Test status
Simulation time 2017181867 ps
CPU time 5.85 seconds
Started Jun 26 04:35:23 PM PDT 24
Finished Jun 26 04:35:35 PM PDT 24
Peak memory 201552 kb
Host smart-d2d14792-2b21-4ade-b5af-a74121dc2f88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397318921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.3397318921
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1362108215
Short name T807
Test name
Test status
Simulation time 2013006674 ps
CPU time 5.73 seconds
Started Jun 26 04:35:40 PM PDT 24
Finished Jun 26 04:35:49 PM PDT 24
Peak memory 201668 kb
Host smart-ec9d37b8-3b5a-41e2-9fe7-12f3f638cb01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362108215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_te
st.1362108215
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.644706021
Short name T855
Test name
Test status
Simulation time 2024230984 ps
CPU time 2.74 seconds
Started Jun 26 04:35:46 PM PDT 24
Finished Jun 26 04:35:52 PM PDT 24
Peak memory 201696 kb
Host smart-7ad3adc8-3c42-43f1-8de6-36d9c1106349
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644706021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_tes
t.644706021
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3586114143
Short name T849
Test name
Test status
Simulation time 2021558976 ps
CPU time 3.12 seconds
Started Jun 26 04:35:34 PM PDT 24
Finished Jun 26 04:35:42 PM PDT 24
Peak memory 201668 kb
Host smart-c4ab8847-f6c3-4847-9957-aa02c90397c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586114143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te
st.3586114143
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2941616343
Short name T903
Test name
Test status
Simulation time 2015815281 ps
CPU time 5.93 seconds
Started Jun 26 04:35:39 PM PDT 24
Finished Jun 26 04:35:48 PM PDT 24
Peak memory 201524 kb
Host smart-daf32f0b-006b-45df-b246-997236551d66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941616343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.2941616343
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1756019709
Short name T862
Test name
Test status
Simulation time 2137931767 ps
CPU time 5.59 seconds
Started Jun 26 04:35:29 PM PDT 24
Finished Jun 26 04:35:41 PM PDT 24
Peak memory 201868 kb
Host smart-3c3fb66a-add8-4aff-8870-e0deaf73075a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756019709 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1756019709
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2426865556
Short name T892
Test name
Test status
Simulation time 2122453486 ps
CPU time 2.05 seconds
Started Jun 26 04:35:18 PM PDT 24
Finished Jun 26 04:35:25 PM PDT 24
Peak memory 201828 kb
Host smart-8c46de30-ffc1-41ae-a4cd-89aad632017b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426865556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.2426865556
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1545715061
Short name T894
Test name
Test status
Simulation time 2013630048 ps
CPU time 3.28 seconds
Started Jun 26 04:35:23 PM PDT 24
Finished Jun 26 04:35:32 PM PDT 24
Peak memory 201588 kb
Host smart-02f6042e-7b12-4199-873d-51dcbb5bce6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545715061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_tes
t.1545715061
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.1645630541
Short name T21
Test name
Test status
Simulation time 4808173934 ps
CPU time 11.91 seconds
Started Jun 26 04:35:30 PM PDT 24
Finished Jun 26 04:35:48 PM PDT 24
Peak memory 202112 kb
Host smart-70f21b35-1e05-4f88-976e-1df6e26ca83c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645630541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.1645630541
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.1466800392
Short name T864
Test name
Test status
Simulation time 2033356526 ps
CPU time 5.68 seconds
Started Jun 26 04:35:27 PM PDT 24
Finished Jun 26 04:35:38 PM PDT 24
Peak memory 202000 kb
Host smart-f2c65e42-fee3-4f67-aa86-d921532b074b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466800392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_error
s.1466800392
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1425079451
Short name T308
Test name
Test status
Simulation time 2122873994 ps
CPU time 5.23 seconds
Started Jun 26 04:35:21 PM PDT 24
Finished Jun 26 04:35:32 PM PDT 24
Peak memory 201864 kb
Host smart-87037409-a8d6-4380-9db4-19eaab4f44a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425079451 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1425079451
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3776680765
Short name T350
Test name
Test status
Simulation time 2039332525 ps
CPU time 5.63 seconds
Started Jun 26 04:35:27 PM PDT 24
Finished Jun 26 04:35:39 PM PDT 24
Peak memory 201740 kb
Host smart-113f9c22-0ab6-49f1-a39c-e8b544c1d2a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776680765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_r
w.3776680765
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2579230615
Short name T811
Test name
Test status
Simulation time 2014218941 ps
CPU time 5.66 seconds
Started Jun 26 04:35:24 PM PDT 24
Finished Jun 26 04:35:36 PM PDT 24
Peak memory 201580 kb
Host smart-6b55d68b-9c12-4ce9-b9a8-ca09eba6e103
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579230615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_tes
t.2579230615
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1342298869
Short name T889
Test name
Test status
Simulation time 2037056087 ps
CPU time 6.7 seconds
Started Jun 26 04:35:21 PM PDT 24
Finished Jun 26 04:35:34 PM PDT 24
Peak memory 202012 kb
Host smart-bf6e7dd1-62e7-465d-b5f3-ff4ced903171
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342298869 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_error
s.1342298869
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.2969248133
Short name T838
Test name
Test status
Simulation time 42924204087 ps
CPU time 28.46 seconds
Started Jun 26 04:35:14 PM PDT 24
Finished Jun 26 04:35:44 PM PDT 24
Peak memory 202124 kb
Host smart-507f2bc6-2cce-46ec-a34f-ca660caa8f8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969248133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.2969248133
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1355331866
Short name T830
Test name
Test status
Simulation time 2060017429 ps
CPU time 6.37 seconds
Started Jun 26 04:35:20 PM PDT 24
Finished Jun 26 04:35:31 PM PDT 24
Peak memory 201764 kb
Host smart-20ce0d47-c444-4bd6-bd83-e5a8b5be1999
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355331866 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1355331866
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.2129102989
Short name T351
Test name
Test status
Simulation time 2030049734 ps
CPU time 5.83 seconds
Started Jun 26 04:35:17 PM PDT 24
Finished Jun 26 04:35:27 PM PDT 24
Peak memory 201804 kb
Host smart-f5d1818f-f9f5-4bd9-86f2-ee0e7a8e6f9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129102989 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_r
w.2129102989
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.3498567963
Short name T836
Test name
Test status
Simulation time 2012060881 ps
CPU time 5.47 seconds
Started Jun 26 04:35:10 PM PDT 24
Finished Jun 26 04:35:17 PM PDT 24
Peak memory 201588 kb
Host smart-f56d03f5-58d5-41a0-ad0a-b9290edb3fe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498567963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_tes
t.3498567963
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2949351187
Short name T850
Test name
Test status
Simulation time 5498847110 ps
CPU time 4.55 seconds
Started Jun 26 04:35:29 PM PDT 24
Finished Jun 26 04:35:44 PM PDT 24
Peak memory 202148 kb
Host smart-5493d959-7d2b-463a-908e-67f90f74a721
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949351187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.2949351187
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1963670139
Short name T882
Test name
Test status
Simulation time 2085975025 ps
CPU time 2.65 seconds
Started Jun 26 04:35:14 PM PDT 24
Finished Jun 26 04:35:18 PM PDT 24
Peak memory 202036 kb
Host smart-5984d6d9-37a3-4bf6-8794-513af9d8c354
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963670139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error
s.1963670139
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3762747752
Short name T840
Test name
Test status
Simulation time 42765672352 ps
CPU time 30.97 seconds
Started Jun 26 04:35:23 PM PDT 24
Finished Jun 26 04:36:00 PM PDT 24
Peak memory 202148 kb
Host smart-cfd089b5-2941-4a2a-891e-14fff250e66a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762747752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.3762747752
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2038749276
Short name T282
Test name
Test status
Simulation time 2190717911 ps
CPU time 2.28 seconds
Started Jun 26 04:35:38 PM PDT 24
Finished Jun 26 04:35:44 PM PDT 24
Peak memory 201968 kb
Host smart-cc2f2d85-24e1-4411-858d-593b5753478c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038749276 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2038749276
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.801848618
Short name T349
Test name
Test status
Simulation time 2133708564 ps
CPU time 1.83 seconds
Started Jun 26 04:35:17 PM PDT 24
Finished Jun 26 04:35:24 PM PDT 24
Peak memory 201756 kb
Host smart-104434fe-3cb0-48bf-94c8-6d801f62fa7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801848618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw
.801848618
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.2555106545
Short name T804
Test name
Test status
Simulation time 2013035569 ps
CPU time 5.81 seconds
Started Jun 26 04:35:25 PM PDT 24
Finished Jun 26 04:35:37 PM PDT 24
Peak memory 201412 kb
Host smart-6c720b1b-764d-4b65-83f4-7e382b28d08a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555106545 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_tes
t.2555106545
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.3018608379
Short name T22
Test name
Test status
Simulation time 10314516289 ps
CPU time 24.4 seconds
Started Jun 26 04:35:24 PM PDT 24
Finished Jun 26 04:35:55 PM PDT 24
Peak memory 202132 kb
Host smart-ea6543f1-e05d-41ed-b1ff-97c2b0eb03d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018608379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_same_csr_outstanding.3018608379
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.2370647784
Short name T900
Test name
Test status
Simulation time 2887494299 ps
CPU time 4.16 seconds
Started Jun 26 04:35:13 PM PDT 24
Finished Jun 26 04:35:20 PM PDT 24
Peak memory 201944 kb
Host smart-c18f602a-c493-40f9-a502-0329ff113db4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370647784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_error
s.2370647784
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.2825822517
Short name T876
Test name
Test status
Simulation time 42582963372 ps
CPU time 58.78 seconds
Started Jun 26 04:35:26 PM PDT 24
Finished Jun 26 04:36:30 PM PDT 24
Peak memory 201832 kb
Host smart-d9fd93db-c2d0-414a-9f40-8ff4838ec4f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825822517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.2825822517
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.971592238
Short name T300
Test name
Test status
Simulation time 2224212171 ps
CPU time 2.52 seconds
Started Jun 26 04:35:40 PM PDT 24
Finished Jun 26 04:35:46 PM PDT 24
Peak memory 202032 kb
Host smart-1153d0a6-e3a2-43d3-bc73-64187ef1e947
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971592238 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.971592238
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2198508562
Short name T30
Test name
Test status
Simulation time 2064618134 ps
CPU time 5.9 seconds
Started Jun 26 04:35:12 PM PDT 24
Finished Jun 26 04:35:28 PM PDT 24
Peak memory 201716 kb
Host smart-38e32fe5-efb7-40bd-86d1-0756cf9db46e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198508562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_r
w.2198508562
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.2379272956
Short name T872
Test name
Test status
Simulation time 2012081411 ps
CPU time 5.42 seconds
Started Jun 26 04:35:23 PM PDT 24
Finished Jun 26 04:35:35 PM PDT 24
Peak memory 201584 kb
Host smart-6dccd859-0c76-4565-8afb-b2c4d31e44fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379272956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_tes
t.2379272956
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.1689175173
Short name T905
Test name
Test status
Simulation time 4904290631 ps
CPU time 7.24 seconds
Started Jun 26 04:35:17 PM PDT 24
Finished Jun 26 04:35:29 PM PDT 24
Peak memory 201952 kb
Host smart-159268d9-293f-43c2-9a37-57e9c5046884
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689175173 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_same_csr_outstanding.1689175173
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2397792155
Short name T861
Test name
Test status
Simulation time 2542224072 ps
CPU time 4.01 seconds
Started Jun 26 04:35:28 PM PDT 24
Finished Jun 26 04:35:38 PM PDT 24
Peak memory 202128 kb
Host smart-cfc6aea9-b47e-4798-a2ec-9a44170dce66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397792155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.2397792155
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.4154359789
Short name T389
Test name
Test status
Simulation time 42359437262 ps
CPU time 108.75 seconds
Started Jun 26 04:35:23 PM PDT 24
Finished Jun 26 04:37:18 PM PDT 24
Peak memory 202168 kb
Host smart-80cf5f68-9014-4625-8fd9-f4f4b655eb89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154359789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.4154359789
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.3278529329
Short name T442
Test name
Test status
Simulation time 2010782895 ps
CPU time 5.62 seconds
Started Jun 26 04:53:38 PM PDT 24
Finished Jun 26 04:53:48 PM PDT 24
Peak memory 201472 kb
Host smart-b128bc0f-9ca4-454a-ac1e-d20a1871ac55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278529329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_tes
t.3278529329
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1166902665
Short name T270
Test name
Test status
Simulation time 3513975032 ps
CPU time 8.9 seconds
Started Jun 26 04:53:42 PM PDT 24
Finished Jun 26 04:53:54 PM PDT 24
Peak memory 201572 kb
Host smart-96185dde-e9ad-4037-94a8-373fd1dd7589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166902665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.1166902665
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.102443404
Short name T260
Test name
Test status
Simulation time 124620280411 ps
CPU time 166.78 seconds
Started Jun 26 04:53:37 PM PDT 24
Finished Jun 26 04:56:28 PM PDT 24
Peak memory 201748 kb
Host smart-d8e1342f-3e4f-48b9-bca3-e7cf4132ab60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102443404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_combo_detect.102443404
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2064479822
Short name T470
Test name
Test status
Simulation time 2195305476 ps
CPU time 3.43 seconds
Started Jun 26 04:53:41 PM PDT 24
Finished Jun 26 04:53:49 PM PDT 24
Peak memory 201436 kb
Host smart-6f9bae48-494f-45a5-a4dc-a7767749a36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064479822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.2064479822
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1434106833
Short name T612
Test name
Test status
Simulation time 2540334460 ps
CPU time 6.91 seconds
Started Jun 26 04:53:39 PM PDT 24
Finished Jun 26 04:53:50 PM PDT 24
Peak memory 201408 kb
Host smart-af7dd3f8-e4de-452e-a1d8-345098a55518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434106833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1434106833
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.2896506155
Short name T94
Test name
Test status
Simulation time 77564513329 ps
CPU time 204.37 seconds
Started Jun 26 04:53:43 PM PDT 24
Finished Jun 26 04:57:12 PM PDT 24
Peak memory 201796 kb
Host smart-c10219a7-761a-486e-8360-dd17f0731a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896506155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi
th_pre_cond.2896506155
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.415794304
Short name T779
Test name
Test status
Simulation time 3156668849 ps
CPU time 8.84 seconds
Started Jun 26 04:53:33 PM PDT 24
Finished Jun 26 04:53:46 PM PDT 24
Peak memory 201416 kb
Host smart-c2a7b927-981c-4228-8da0-23f7931a6b92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415794304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_ec_pwr_on_rst.415794304
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.2549005199
Short name T688
Test name
Test status
Simulation time 2556827793 ps
CPU time 6.56 seconds
Started Jun 26 04:53:39 PM PDT 24
Finished Jun 26 04:53:49 PM PDT 24
Peak memory 201472 kb
Host smart-a2e061d3-8bc4-4e48-89fe-05293f12e50a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549005199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.2549005199
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.3390266986
Short name T215
Test name
Test status
Simulation time 2630031111 ps
CPU time 2.07 seconds
Started Jun 26 04:53:38 PM PDT 24
Finished Jun 26 04:53:44 PM PDT 24
Peak memory 201524 kb
Host smart-07cbef5c-edf6-46e4-ba07-aac880e43193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390266986 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.3390266986
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.1316501645
Short name T324
Test name
Test status
Simulation time 2459043697 ps
CPU time 7.19 seconds
Started Jun 26 04:53:42 PM PDT 24
Finished Jun 26 04:53:54 PM PDT 24
Peak memory 201516 kb
Host smart-a92a92c9-d7e5-4321-a4dd-118e7255b493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316501645 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.1316501645
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.3328918464
Short name T777
Test name
Test status
Simulation time 2200507308 ps
CPU time 6.82 seconds
Started Jun 26 04:53:41 PM PDT 24
Finished Jun 26 04:53:52 PM PDT 24
Peak memory 201484 kb
Host smart-ac2e1474-d1c7-45dd-8568-933a41940ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328918464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.3328918464
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.1944109429
Short name T144
Test name
Test status
Simulation time 2511725828 ps
CPU time 7.19 seconds
Started Jun 26 04:53:52 PM PDT 24
Finished Jun 26 04:54:02 PM PDT 24
Peak memory 201424 kb
Host smart-a398e31c-a658-4c96-9c0d-3bcbb517e90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944109429 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.1944109429
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.1017230052
Short name T788
Test name
Test status
Simulation time 2133553749 ps
CPU time 1.94 seconds
Started Jun 26 04:53:43 PM PDT 24
Finished Jun 26 04:53:49 PM PDT 24
Peak memory 201416 kb
Host smart-bf68c928-040d-4e30-bf40-0e32a2349881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017230052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.1017230052
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.1709323974
Short name T603
Test name
Test status
Simulation time 9433282509 ps
CPU time 26.24 seconds
Started Jun 26 04:53:41 PM PDT 24
Finished Jun 26 04:54:11 PM PDT 24
Peak memory 201556 kb
Host smart-91214805-f3ca-4798-8494-29a43bbdec1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709323974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st
ress_all.1709323974
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.2682545776
Short name T90
Test name
Test status
Simulation time 74290798877 ps
CPU time 171.85 seconds
Started Jun 26 04:53:34 PM PDT 24
Finished Jun 26 04:56:31 PM PDT 24
Peak memory 214500 kb
Host smart-f9c680ec-631c-498a-8f55-d453bfb56b84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682545776 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.2682545776
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.2363004859
Short name T775
Test name
Test status
Simulation time 4040320627 ps
CPU time 6.41 seconds
Started Jun 26 04:53:49 PM PDT 24
Finished Jun 26 04:53:59 PM PDT 24
Peak memory 201428 kb
Host smart-df54a179-95f1-4125-a80c-01535b1f9aa0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363004859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ultra_low_pwr.2363004859
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.2418369368
Short name T414
Test name
Test status
Simulation time 2011651330 ps
CPU time 5.91 seconds
Started Jun 26 04:53:56 PM PDT 24
Finished Jun 26 04:54:04 PM PDT 24
Peak memory 201476 kb
Host smart-5ca511dd-e98f-4265-a991-21f01411e183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418369368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_tes
t.2418369368
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.3875678220
Short name T617
Test name
Test status
Simulation time 3325776603 ps
CPU time 3.3 seconds
Started Jun 26 04:53:49 PM PDT 24
Finished Jun 26 04:53:56 PM PDT 24
Peak memory 201548 kb
Host smart-b165099d-ce0a-4665-a62e-08b5c98416e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875678220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.3875678220
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.2513450264
Short name T582
Test name
Test status
Simulation time 53439316398 ps
CPU time 73.74 seconds
Started Jun 26 04:53:37 PM PDT 24
Finished Jun 26 04:54:55 PM PDT 24
Peak memory 201732 kb
Host smart-cc8f3124-ee29-4236-865c-d0dc4d688ff5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513450264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_combo_detect.2513450264
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.843287438
Short name T763
Test name
Test status
Simulation time 2307714039 ps
CPU time 1.14 seconds
Started Jun 26 04:53:44 PM PDT 24
Finished Jun 26 04:53:50 PM PDT 24
Peak memory 201412 kb
Host smart-1511a514-aa91-40ad-bed7-c29f632d9d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843287438 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.843287438
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2710241688
Short name T189
Test name
Test status
Simulation time 2662794253 ps
CPU time 0.92 seconds
Started Jun 26 04:53:44 PM PDT 24
Finished Jun 26 04:53:49 PM PDT 24
Peak memory 201400 kb
Host smart-d1a0b8d7-2d90-4f3c-a035-354a387b9587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710241688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2710241688
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3319039142
Short name T659
Test name
Test status
Simulation time 66981802222 ps
CPU time 172.88 seconds
Started Jun 26 04:53:43 PM PDT 24
Finished Jun 26 04:56:40 PM PDT 24
Peak memory 201820 kb
Host smart-e2c0e244-ed59-48d5-a5df-7223badc72a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319039142 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi
th_pre_cond.3319039142
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3154338857
Short name T438
Test name
Test status
Simulation time 3576835345 ps
CPU time 9.24 seconds
Started Jun 26 04:53:43 PM PDT 24
Finished Jun 26 04:53:57 PM PDT 24
Peak memory 201408 kb
Host smart-b997e23b-5d78-4f97-9c0f-f9d5e2725dd0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154338857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ec_pwr_on_rst.3154338857
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.4047979021
Short name T158
Test name
Test status
Simulation time 5485636626 ps
CPU time 7.66 seconds
Started Jun 26 04:53:33 PM PDT 24
Finished Jun 26 04:53:45 PM PDT 24
Peak memory 201452 kb
Host smart-ad71a82c-5c84-41f6-9bb6-99fdcd1e4c4a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047979021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.4047979021
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.36875266
Short name T78
Test name
Test status
Simulation time 41206733823 ps
CPU time 8.46 seconds
Started Jun 26 04:53:40 PM PDT 24
Finished Jun 26 04:53:52 PM PDT 24
Peak memory 201584 kb
Host smart-60d3dc93-3d57-4d0a-a946-e6db9ea051b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36875266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.36875266
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.1427216150
Short name T222
Test name
Test status
Simulation time 2614761425 ps
CPU time 7.16 seconds
Started Jun 26 04:53:38 PM PDT 24
Finished Jun 26 04:53:49 PM PDT 24
Peak memory 201516 kb
Host smart-fa822823-d388-4129-a319-921163c0ceb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427216150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.1427216150
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.1743839286
Short name T764
Test name
Test status
Simulation time 2469144373 ps
CPU time 6.94 seconds
Started Jun 26 04:53:47 PM PDT 24
Finished Jun 26 04:53:58 PM PDT 24
Peak memory 201440 kb
Host smart-440acd41-d3e7-4a78-a839-be4e20aa30a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743839286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.1743839286
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.3072349815
Short name T317
Test name
Test status
Simulation time 2162793813 ps
CPU time 3.09 seconds
Started Jun 26 04:53:58 PM PDT 24
Finished Jun 26 04:54:05 PM PDT 24
Peak memory 201408 kb
Host smart-f3e1ef04-02d4-4a29-9985-a8ae5f8c2421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072349815 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.3072349815
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.1787567
Short name T740
Test name
Test status
Simulation time 2513356913 ps
CPU time 5.82 seconds
Started Jun 26 04:53:41 PM PDT 24
Finished Jun 26 04:53:55 PM PDT 24
Peak memory 201468 kb
Host smart-a044adb2-eefa-4b39-a044-4761f6e8995d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787567 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.1787567
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.1638651566
Short name T284
Test name
Test status
Simulation time 42278901765 ps
CPU time 23.7 seconds
Started Jun 26 04:53:46 PM PDT 24
Finished Jun 26 04:54:14 PM PDT 24
Peak memory 221312 kb
Host smart-359485e1-b9f2-450a-8dbe-cbb271dbfa26
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638651566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.1638651566
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.2514756576
Short name T448
Test name
Test status
Simulation time 2126546170 ps
CPU time 1.88 seconds
Started Jun 26 04:53:41 PM PDT 24
Finished Jun 26 04:53:46 PM PDT 24
Peak memory 201384 kb
Host smart-9c4de9e9-366f-469e-86e9-92169f2df717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514756576 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.2514756576
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.3837091668
Short name T449
Test name
Test status
Simulation time 17042806411 ps
CPU time 9.65 seconds
Started Jun 26 04:53:44 PM PDT 24
Finished Jun 26 04:53:58 PM PDT 24
Peak memory 201612 kb
Host smart-e51081c4-2299-4058-8dc3-66f7b98034a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837091668 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.3837091668
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2668224496
Short name T572
Test name
Test status
Simulation time 6465481882 ps
CPU time 6.78 seconds
Started Jun 26 04:53:45 PM PDT 24
Finished Jun 26 04:53:57 PM PDT 24
Peak memory 201452 kb
Host smart-dfc7991a-64e8-423c-927b-0714752b2a9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668224496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ultra_low_pwr.2668224496
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.3420738910
Short name T113
Test name
Test status
Simulation time 2032562771 ps
CPU time 2.06 seconds
Started Jun 26 04:53:59 PM PDT 24
Finished Jun 26 04:54:04 PM PDT 24
Peak memory 201368 kb
Host smart-d723b82e-5a30-4e20-9fb7-f06577b663a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420738910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te
st.3420738910
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.1393382470
Short name T185
Test name
Test status
Simulation time 3039416265 ps
CPU time 4.39 seconds
Started Jun 26 04:54:01 PM PDT 24
Finished Jun 26 04:54:09 PM PDT 24
Peak memory 201492 kb
Host smart-319ad72b-df8e-4b9e-9d61-80384765812e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393382470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.1
393382470
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.3427699949
Short name T388
Test name
Test status
Simulation time 151077677984 ps
CPU time 103.23 seconds
Started Jun 26 04:54:05 PM PDT 24
Finished Jun 26 04:55:51 PM PDT 24
Peak memory 201820 kb
Host smart-b339abf7-6c73-471c-97ef-67c7bfa22466
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427699949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_combo_detect.3427699949
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.114135524
Short name T557
Test name
Test status
Simulation time 3447330569 ps
CPU time 8.94 seconds
Started Jun 26 04:54:05 PM PDT 24
Finished Jun 26 04:54:17 PM PDT 24
Peak memory 201488 kb
Host smart-90e2ce8b-ea14-4990-8c59-0b177053d7ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114135524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_ec_pwr_on_rst.114135524
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.1552294329
Short name T320
Test name
Test status
Simulation time 4625179964 ps
CPU time 3.07 seconds
Started Jun 26 04:53:59 PM PDT 24
Finished Jun 26 04:54:05 PM PDT 24
Peak memory 201560 kb
Host smart-b309cb06-1b9d-4152-b56d-a83a82de6f73
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552294329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_edge_detect.1552294329
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.2028627387
Short name T573
Test name
Test status
Simulation time 2640624374 ps
CPU time 1.78 seconds
Started Jun 26 04:54:05 PM PDT 24
Finished Jun 26 04:54:10 PM PDT 24
Peak memory 201524 kb
Host smart-bb108232-19ad-41d3-a884-476b4ae30ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028627387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.2028627387
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.3358200949
Short name T491
Test name
Test status
Simulation time 2476493026 ps
CPU time 1.98 seconds
Started Jun 26 04:54:01 PM PDT 24
Finished Jun 26 04:54:06 PM PDT 24
Peak memory 201432 kb
Host smart-6cb1b695-c669-498b-8e56-d7de18f2e5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358200949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.3358200949
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.2178476840
Short name T754
Test name
Test status
Simulation time 2143251231 ps
CPU time 6.47 seconds
Started Jun 26 04:54:03 PM PDT 24
Finished Jun 26 04:54:13 PM PDT 24
Peak memory 201368 kb
Host smart-165092f4-c3b9-4e60-b1d2-8dfadac335fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178476840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.2178476840
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.4158589657
Short name T462
Test name
Test status
Simulation time 2514513861 ps
CPU time 6.82 seconds
Started Jun 26 04:54:01 PM PDT 24
Finished Jun 26 04:54:11 PM PDT 24
Peak memory 201428 kb
Host smart-e2a1e900-df79-461c-88a2-6f25d69cef50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158589657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.4158589657
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.3006144997
Short name T683
Test name
Test status
Simulation time 2109573066 ps
CPU time 6.1 seconds
Started Jun 26 04:54:09 PM PDT 24
Finished Jun 26 04:54:17 PM PDT 24
Peak memory 201440 kb
Host smart-c0135a51-86ef-4d58-8326-917f77d71473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006144997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.3006144997
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.198184158
Short name T549
Test name
Test status
Simulation time 686303024347 ps
CPU time 1080.9 seconds
Started Jun 26 04:53:59 PM PDT 24
Finished Jun 26 05:12:04 PM PDT 24
Peak memory 201556 kb
Host smart-9ed8efe5-8cc0-40fa-8647-8488859e2be9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198184158 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_st
ress_all.198184158
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.3587343535
Short name T164
Test name
Test status
Simulation time 70486067322 ps
CPU time 165.32 seconds
Started Jun 26 04:54:01 PM PDT 24
Finished Jun 26 04:56:50 PM PDT 24
Peak memory 218312 kb
Host smart-d4f6e687-cda3-49e6-b838-7fb7cf68db95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587343535 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.3587343535
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.2350229551
Short name T135
Test name
Test status
Simulation time 6830296726 ps
CPU time 8.71 seconds
Started Jun 26 04:53:58 PM PDT 24
Finished Jun 26 04:54:10 PM PDT 24
Peak memory 201552 kb
Host smart-201b397c-11d2-4b26-bb6a-0e3596bf594a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350229551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ultra_low_pwr.2350229551
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.1634265849
Short name T443
Test name
Test status
Simulation time 2057051202 ps
CPU time 1.26 seconds
Started Jun 26 04:54:13 PM PDT 24
Finished Jun 26 04:54:16 PM PDT 24
Peak memory 201424 kb
Host smart-788abaf5-5928-4853-8d3b-93f69a9d21af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634265849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te
st.1634265849
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.1372933054
Short name T545
Test name
Test status
Simulation time 3153546320 ps
CPU time 1.72 seconds
Started Jun 26 04:53:59 PM PDT 24
Finished Jun 26 04:54:04 PM PDT 24
Peak memory 201516 kb
Host smart-7b24b45e-e900-452a-bf0b-8186a41d00f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372933054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.1
372933054
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.1893686067
Short name T148
Test name
Test status
Simulation time 131017044462 ps
CPU time 65.17 seconds
Started Jun 26 04:54:03 PM PDT 24
Finished Jun 26 04:55:12 PM PDT 24
Peak memory 201728 kb
Host smart-6b08a952-42fb-4486-bfd6-692a8bdc618a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893686067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_combo_detect.1893686067
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.32734983
Short name T796
Test name
Test status
Simulation time 3155492514 ps
CPU time 8.03 seconds
Started Jun 26 04:54:13 PM PDT 24
Finished Jun 26 04:54:23 PM PDT 24
Peak memory 201488 kb
Host smart-b729ad5e-c462-4132-a138-f45100b941a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32734983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_ec_pwr_on_rst.32734983
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.2774528826
Short name T489
Test name
Test status
Simulation time 2628975787 ps
CPU time 2.2 seconds
Started Jun 26 04:54:03 PM PDT 24
Finished Jun 26 04:54:10 PM PDT 24
Peak memory 201524 kb
Host smart-f6148cf9-61b4-4b88-9488-741b1e46edc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774528826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.2774528826
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.725592497
Short name T663
Test name
Test status
Simulation time 2463413510 ps
CPU time 7.09 seconds
Started Jun 26 04:54:02 PM PDT 24
Finished Jun 26 04:54:12 PM PDT 24
Peak memory 201468 kb
Host smart-5bb91056-5d41-4c0e-85aa-ca8e6ce23314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725592497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.725592497
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.3220821996
Short name T469
Test name
Test status
Simulation time 2152468677 ps
CPU time 1.93 seconds
Started Jun 26 04:54:08 PM PDT 24
Finished Jun 26 04:54:13 PM PDT 24
Peak memory 201428 kb
Host smart-a46e22ad-2d1b-497f-badd-897b1675d16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220821996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.3220821996
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.810036880
Short name T637
Test name
Test status
Simulation time 2512865853 ps
CPU time 7.38 seconds
Started Jun 26 04:54:03 PM PDT 24
Finished Jun 26 04:54:14 PM PDT 24
Peak memory 201516 kb
Host smart-f91aec95-f714-4c89-8818-181f29a06ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810036880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.810036880
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.3811991633
Short name T727
Test name
Test status
Simulation time 2148474345 ps
CPU time 1.57 seconds
Started Jun 26 04:54:04 PM PDT 24
Finished Jun 26 04:54:09 PM PDT 24
Peak memory 201496 kb
Host smart-3908cb47-cb87-4d9b-9cd3-dc3fed7a7aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811991633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.3811991633
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.3615124170
Short name T512
Test name
Test status
Simulation time 9866083790 ps
CPU time 6.83 seconds
Started Jun 26 04:54:07 PM PDT 24
Finished Jun 26 04:54:17 PM PDT 24
Peak memory 201544 kb
Host smart-1220ba59-8dfe-45b6-9a43-0a78359fa0b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615124170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ultra_low_pwr.3615124170
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.1378526676
Short name T778
Test name
Test status
Simulation time 2012376760 ps
CPU time 6.2 seconds
Started Jun 26 04:54:09 PM PDT 24
Finished Jun 26 04:54:18 PM PDT 24
Peak memory 201424 kb
Host smart-f94e354e-f57c-4723-8059-9cf112049446
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378526676 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te
st.1378526676
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.3764257416
Short name T578
Test name
Test status
Simulation time 3296812449 ps
CPU time 8.54 seconds
Started Jun 26 04:54:10 PM PDT 24
Finished Jun 26 04:54:21 PM PDT 24
Peak memory 201512 kb
Host smart-c868665b-a168-459c-81f1-8492837e8af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764257416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.3
764257416
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.111657482
Short name T653
Test name
Test status
Simulation time 158353469690 ps
CPU time 286.34 seconds
Started Jun 26 04:54:05 PM PDT 24
Finished Jun 26 04:58:55 PM PDT 24
Peak memory 201780 kb
Host smart-2a772dff-461d-41c8-b7db-bdd5a51b4788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111657482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_wi
th_pre_cond.111657482
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.1217655131
Short name T407
Test name
Test status
Simulation time 3535365795 ps
CPU time 5.58 seconds
Started Jun 26 04:54:05 PM PDT 24
Finished Jun 26 04:54:14 PM PDT 24
Peak memory 201468 kb
Host smart-d25896a1-136c-412e-a05b-0590605da174
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217655131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ec_pwr_on_rst.1217655131
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.2695255899
Short name T770
Test name
Test status
Simulation time 2830104547 ps
CPU time 3.67 seconds
Started Jun 26 04:54:02 PM PDT 24
Finished Jun 26 04:54:08 PM PDT 24
Peak memory 201460 kb
Host smart-a421f954-5dc7-4eac-9a6a-6f1ffa24838f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695255899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_edge_detect.2695255899
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.1931020379
Short name T477
Test name
Test status
Simulation time 2609233491 ps
CPU time 6.81 seconds
Started Jun 26 04:54:10 PM PDT 24
Finished Jun 26 04:54:19 PM PDT 24
Peak memory 201484 kb
Host smart-110161ca-3880-4e98-9225-250c714200c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931020379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.1931020379
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.3322847499
Short name T589
Test name
Test status
Simulation time 2460518270 ps
CPU time 2.46 seconds
Started Jun 26 04:54:10 PM PDT 24
Finished Jun 26 04:54:15 PM PDT 24
Peak memory 201440 kb
Host smart-4f246a55-26b4-449d-ac05-98f7ae3d64fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322847499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.3322847499
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.2189923584
Short name T755
Test name
Test status
Simulation time 2035208328 ps
CPU time 5.69 seconds
Started Jun 26 04:54:57 PM PDT 24
Finished Jun 26 04:55:05 PM PDT 24
Peak memory 201356 kb
Host smart-4dd11ed2-b389-4d26-b3aa-77811833d9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189923584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.2189923584
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.4088971024
Short name T522
Test name
Test status
Simulation time 2520480088 ps
CPU time 4.1 seconds
Started Jun 26 04:54:10 PM PDT 24
Finished Jun 26 04:54:16 PM PDT 24
Peak memory 201716 kb
Host smart-49ac3ca1-b10e-440f-8611-4e408f9fd6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088971024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.4088971024
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.1624589915
Short name T781
Test name
Test status
Simulation time 2114761536 ps
CPU time 3.12 seconds
Started Jun 26 04:53:59 PM PDT 24
Finished Jun 26 04:54:06 PM PDT 24
Peak memory 201400 kb
Host smart-b61c85e4-fae6-403d-8498-8938bc78d3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624589915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.1624589915
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.1645433681
Short name T102
Test name
Test status
Simulation time 232617167204 ps
CPU time 557.03 seconds
Started Jun 26 04:54:08 PM PDT 24
Finished Jun 26 05:03:28 PM PDT 24
Peak memory 201660 kb
Host smart-93d79237-b387-465a-8306-146a5ef6c5a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645433681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_s
tress_all.1645433681
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.2370661608
Short name T232
Test name
Test status
Simulation time 25546449186 ps
CPU time 16.04 seconds
Started Jun 26 04:54:05 PM PDT 24
Finished Jun 26 04:54:24 PM PDT 24
Peak memory 210192 kb
Host smart-003d0575-3216-4868-a772-000ae7cc1ac8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370661608 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.2370661608
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.1818616137
Short name T559
Test name
Test status
Simulation time 2038099639 ps
CPU time 1.79 seconds
Started Jun 26 04:54:04 PM PDT 24
Finished Jun 26 04:54:09 PM PDT 24
Peak memory 201424 kb
Host smart-5280b548-15c0-480e-82f1-ef0638912644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818616137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.1818616137
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.2151327227
Short name T534
Test name
Test status
Simulation time 3596452889 ps
CPU time 9.86 seconds
Started Jun 26 04:54:03 PM PDT 24
Finished Jun 26 04:54:16 PM PDT 24
Peak memory 201516 kb
Host smart-6973ddd5-33e7-4ae7-96ce-7adf8bd0707f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151327227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.2
151327227
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.688239420
Short name T355
Test name
Test status
Simulation time 85521323888 ps
CPU time 199.59 seconds
Started Jun 26 04:54:13 PM PDT 24
Finished Jun 26 04:57:35 PM PDT 24
Peak memory 202044 kb
Host smart-73ea2601-c7d7-482a-9b32-b6e831be5dd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688239420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_combo_detect.688239420
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.3650923150
Short name T241
Test name
Test status
Simulation time 55464635929 ps
CPU time 71.88 seconds
Started Jun 26 04:54:13 PM PDT 24
Finished Jun 26 04:55:27 PM PDT 24
Peak memory 202040 kb
Host smart-105bfa4b-09cc-4103-980d-87e9357f2047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650923150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_w
ith_pre_cond.3650923150
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.3494155157
Short name T537
Test name
Test status
Simulation time 3560976525 ps
CPU time 9.51 seconds
Started Jun 26 04:54:05 PM PDT 24
Finished Jun 26 04:54:22 PM PDT 24
Peak memory 201404 kb
Host smart-98890db4-28da-440e-b838-97fbb660e653
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494155157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.3494155157
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.1830017300
Short name T159
Test name
Test status
Simulation time 2971320444 ps
CPU time 3.67 seconds
Started Jun 26 04:54:14 PM PDT 24
Finished Jun 26 04:54:19 PM PDT 24
Peak memory 201712 kb
Host smart-e0bd6e8f-c2cc-4bbf-bb07-facfeea9cee7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830017300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_edge_detect.1830017300
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.3373767621
Short name T527
Test name
Test status
Simulation time 2627551248 ps
CPU time 3.06 seconds
Started Jun 26 04:54:05 PM PDT 24
Finished Jun 26 04:54:11 PM PDT 24
Peak memory 201480 kb
Host smart-953784f1-eff5-47d6-9eba-5cc52395f46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373767621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.3373767621
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.4277942681
Short name T321
Test name
Test status
Simulation time 2465002518 ps
CPU time 6.9 seconds
Started Jun 26 04:54:04 PM PDT 24
Finished Jun 26 04:54:14 PM PDT 24
Peak memory 201436 kb
Host smart-9d9cfcf2-ca3c-4e9c-a3b4-0a91a94c0134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277942681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.4277942681
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.1418664813
Short name T601
Test name
Test status
Simulation time 2168449005 ps
CPU time 1.5 seconds
Started Jun 26 04:54:05 PM PDT 24
Finished Jun 26 04:54:10 PM PDT 24
Peak memory 201736 kb
Host smart-24b8d5b3-af30-414a-9b7e-d02fb059c0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418664813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.1418664813
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.1735913477
Short name T709
Test name
Test status
Simulation time 2540360095 ps
CPU time 2.26 seconds
Started Jun 26 04:54:02 PM PDT 24
Finished Jun 26 04:54:07 PM PDT 24
Peak memory 201740 kb
Host smart-34912b44-96d9-478d-a32c-d4b0f0070e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735913477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.1735913477
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.1752738286
Short name T606
Test name
Test status
Simulation time 2160336898 ps
CPU time 1.39 seconds
Started Jun 26 04:54:09 PM PDT 24
Finished Jun 26 04:54:13 PM PDT 24
Peak memory 201316 kb
Host smart-848276fe-560e-42d5-8ff7-319ebf4dfd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752738286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.1752738286
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3341822331
Short name T32
Test name
Test status
Simulation time 89728911787 ps
CPU time 109.02 seconds
Started Jun 26 04:54:05 PM PDT 24
Finished Jun 26 04:55:57 PM PDT 24
Peak memory 210252 kb
Host smart-1b91cbf7-ada6-4053-9e0b-c0e2e439c314
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341822331 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.3341822331
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.2820890096
Short name T693
Test name
Test status
Simulation time 6500250429 ps
CPU time 7.44 seconds
Started Jun 26 04:54:15 PM PDT 24
Finished Jun 26 04:54:24 PM PDT 24
Peak memory 201552 kb
Host smart-1ea25975-0cb3-473b-b290-996620cfdbf3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820890096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ultra_low_pwr.2820890096
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.2871549943
Short name T503
Test name
Test status
Simulation time 2014600436 ps
CPU time 3.27 seconds
Started Jun 26 04:54:35 PM PDT 24
Finished Jun 26 04:54:41 PM PDT 24
Peak memory 201416 kb
Host smart-aae186d4-8e93-46de-900b-eea08f607087
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871549943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.2871549943
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.449701443
Short name T639
Test name
Test status
Simulation time 3135928749 ps
CPU time 2.61 seconds
Started Jun 26 04:54:12 PM PDT 24
Finished Jun 26 04:54:17 PM PDT 24
Peak memory 201572 kb
Host smart-31536d90-74ee-4633-8bc3-cf0816667e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449701443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.449701443
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.1785489434
Short name T694
Test name
Test status
Simulation time 36492564593 ps
CPU time 25.27 seconds
Started Jun 26 04:54:11 PM PDT 24
Finished Jun 26 04:54:38 PM PDT 24
Peak memory 201792 kb
Host smart-0894a1bb-3ccf-443d-8c5d-596cda6822bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785489434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_w
ith_pre_cond.1785489434
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.684485814
Short name T473
Test name
Test status
Simulation time 3276792308 ps
CPU time 0.98 seconds
Started Jun 26 04:54:12 PM PDT 24
Finished Jun 26 04:54:15 PM PDT 24
Peak memory 201392 kb
Host smart-4579c426-dea6-408e-8cab-93be5ee2c372
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684485814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_ec_pwr_on_rst.684485814
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.756031760
Short name T214
Test name
Test status
Simulation time 3524266060 ps
CPU time 2.76 seconds
Started Jun 26 04:54:15 PM PDT 24
Finished Jun 26 04:54:20 PM PDT 24
Peak memory 201396 kb
Host smart-7d176598-8878-4ec1-ab80-c87c103f418a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756031760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctr
l_edge_detect.756031760
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.943047653
Short name T218
Test name
Test status
Simulation time 2627951424 ps
CPU time 2.02 seconds
Started Jun 26 04:54:13 PM PDT 24
Finished Jun 26 04:54:17 PM PDT 24
Peak memory 201432 kb
Host smart-5657ea68-453d-4ecb-9b55-bbab5078c4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943047653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.943047653
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.3262416144
Short name T627
Test name
Test status
Simulation time 2507681183 ps
CPU time 1.71 seconds
Started Jun 26 04:54:06 PM PDT 24
Finished Jun 26 04:54:11 PM PDT 24
Peak memory 201440 kb
Host smart-8c0c533a-5b47-4839-97d4-0568e9216f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262416144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.3262416144
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.4284969182
Short name T16
Test name
Test status
Simulation time 2025395561 ps
CPU time 6.29 seconds
Started Jun 26 04:54:15 PM PDT 24
Finished Jun 26 04:54:23 PM PDT 24
Peak memory 201416 kb
Host smart-39eedc1c-772c-4238-a98b-6d74325c2d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284969182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.4284969182
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.831236317
Short name T404
Test name
Test status
Simulation time 2539074452 ps
CPU time 2.04 seconds
Started Jun 26 04:54:10 PM PDT 24
Finished Jun 26 04:54:15 PM PDT 24
Peak memory 201516 kb
Host smart-a08a0bd0-e2df-435f-9f63-4361ebcca848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831236317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.831236317
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.3159921791
Short name T624
Test name
Test status
Simulation time 2144135669 ps
CPU time 1.4 seconds
Started Jun 26 04:54:12 PM PDT 24
Finished Jun 26 04:54:15 PM PDT 24
Peak memory 201412 kb
Host smart-78e7b1a1-3bc1-41e0-8965-2f8eb858d8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159921791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.3159921791
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.640871714
Short name T466
Test name
Test status
Simulation time 2033859360 ps
CPU time 1.64 seconds
Started Jun 26 04:54:16 PM PDT 24
Finished Jun 26 04:54:19 PM PDT 24
Peak memory 201504 kb
Host smart-09f582d8-ac9f-4608-9631-84ab953cc34d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640871714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_tes
t.640871714
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.3316603440
Short name T610
Test name
Test status
Simulation time 246318752482 ps
CPU time 129.01 seconds
Started Jun 26 04:54:13 PM PDT 24
Finished Jun 26 04:56:24 PM PDT 24
Peak memory 201552 kb
Host smart-fd2024b8-0f16-42d3-91ef-5b06ae517ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316603440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.3
316603440
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.2545064108
Short name T269
Test name
Test status
Simulation time 30355404039 ps
CPU time 72.38 seconds
Started Jun 26 04:54:10 PM PDT 24
Finished Jun 26 04:55:24 PM PDT 24
Peak memory 201768 kb
Host smart-a2e634df-1a00-4ca4-8fad-ab536591acc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545064108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_combo_detect.2545064108
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.4188658011
Short name T576
Test name
Test status
Simulation time 3658077083 ps
CPU time 5.2 seconds
Started Jun 26 04:54:08 PM PDT 24
Finished Jun 26 04:54:16 PM PDT 24
Peak memory 201404 kb
Host smart-6a0d2fbd-b00f-4089-a443-fa2de2c2d7f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188658011 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ec_pwr_on_rst.4188658011
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.2912030436
Short name T225
Test name
Test status
Simulation time 3251397954 ps
CPU time 7.35 seconds
Started Jun 26 04:54:17 PM PDT 24
Finished Jun 26 04:54:26 PM PDT 24
Peak memory 201500 kb
Host smart-2a3e9870-6762-461b-a4d9-cd0517575599
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912030436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.2912030436
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.276280012
Short name T629
Test name
Test status
Simulation time 2625631191 ps
CPU time 2.38 seconds
Started Jun 26 04:54:18 PM PDT 24
Finished Jun 26 04:54:21 PM PDT 24
Peak memory 201516 kb
Host smart-8ab020a6-1376-49c1-b62a-e7cfb5024fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276280012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.276280012
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.712535331
Short name T63
Test name
Test status
Simulation time 2486369770 ps
CPU time 2.21 seconds
Started Jun 26 04:54:24 PM PDT 24
Finished Jun 26 04:54:28 PM PDT 24
Peak memory 201512 kb
Host smart-934d88a8-24e8-404a-b6cd-53431205394a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712535331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.712535331
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.2798350628
Short name T202
Test name
Test status
Simulation time 2285560092 ps
CPU time 2.14 seconds
Started Jun 26 04:54:18 PM PDT 24
Finished Jun 26 04:54:21 PM PDT 24
Peak memory 201420 kb
Host smart-27509a77-df84-4937-8f7d-d2f78d852932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798350628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.2798350628
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.2917320216
Short name T757
Test name
Test status
Simulation time 2542420261 ps
CPU time 1.42 seconds
Started Jun 26 04:54:18 PM PDT 24
Finished Jun 26 04:54:21 PM PDT 24
Peak memory 201424 kb
Host smart-2a525db7-0a1e-4f9b-9daf-14d9116d8c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917320216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.2917320216
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.4084937928
Short name T760
Test name
Test status
Simulation time 2112009944 ps
CPU time 5.76 seconds
Started Jun 26 04:54:21 PM PDT 24
Finished Jun 26 04:54:28 PM PDT 24
Peak memory 201416 kb
Host smart-e8de3831-8904-47a0-8c13-899370eb85e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084937928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.4084937928
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.482723837
Short name T266
Test name
Test status
Simulation time 333400585032 ps
CPU time 273.8 seconds
Started Jun 26 04:54:12 PM PDT 24
Finished Jun 26 04:58:48 PM PDT 24
Peak memory 201800 kb
Host smart-32d9474c-9a1a-4d72-a2c8-619483c917f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482723837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_st
ress_all.482723837
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.4107472483
Short name T82
Test name
Test status
Simulation time 5133877428 ps
CPU time 6.32 seconds
Started Jun 26 04:54:07 PM PDT 24
Finished Jun 26 04:54:16 PM PDT 24
Peak memory 201520 kb
Host smart-ba36c763-b85c-43bb-8dc0-8d98ae21c667
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107472483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ultra_low_pwr.4107472483
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.715558231
Short name T723
Test name
Test status
Simulation time 3612482538 ps
CPU time 2.2 seconds
Started Jun 26 04:54:22 PM PDT 24
Finished Jun 26 04:54:25 PM PDT 24
Peak memory 201568 kb
Host smart-3b6a5e57-3aae-404d-92c4-fc0f1cac50c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715558231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.715558231
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.3814571717
Short name T743
Test name
Test status
Simulation time 70555186529 ps
CPU time 56.35 seconds
Started Jun 26 04:54:20 PM PDT 24
Finished Jun 26 04:55:18 PM PDT 24
Peak memory 201776 kb
Host smart-769fd4ba-e02f-41f4-8205-b4d2cd2f036e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814571717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_combo_detect.3814571717
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.740122226
Short name T384
Test name
Test status
Simulation time 66092598998 ps
CPU time 40.14 seconds
Started Jun 26 04:54:30 PM PDT 24
Finished Jun 26 04:55:14 PM PDT 24
Peak memory 201848 kb
Host smart-9e7b6266-6f36-4fa0-af17-da29eccee053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740122226 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_wi
th_pre_cond.740122226
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1174542979
Short name T519
Test name
Test status
Simulation time 3058478481 ps
CPU time 4.77 seconds
Started Jun 26 04:54:15 PM PDT 24
Finished Jun 26 04:54:22 PM PDT 24
Peak memory 201440 kb
Host smart-9ad8205b-ae1c-463d-b40f-daf61d79c2ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174542979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ec_pwr_on_rst.1174542979
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.813485927
Short name T587
Test name
Test status
Simulation time 2617322955 ps
CPU time 3.83 seconds
Started Jun 26 04:54:19 PM PDT 24
Finished Jun 26 04:54:25 PM PDT 24
Peak memory 201716 kb
Host smart-db0a9731-889e-4d03-be11-10c997feac2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813485927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.813485927
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.3910585117
Short name T733
Test name
Test status
Simulation time 2474156625 ps
CPU time 2.28 seconds
Started Jun 26 04:54:28 PM PDT 24
Finished Jun 26 04:54:33 PM PDT 24
Peak memory 201520 kb
Host smart-cdec10b8-e073-407f-8608-d7dddcae221d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910585117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.3910585117
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.1273229122
Short name T201
Test name
Test status
Simulation time 2105646685 ps
CPU time 1.96 seconds
Started Jun 26 04:54:15 PM PDT 24
Finished Jun 26 04:54:19 PM PDT 24
Peak memory 201448 kb
Host smart-a3c768bf-aeb8-4e8f-bb04-809ee14b0120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273229122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.1273229122
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.651053600
Short name T762
Test name
Test status
Simulation time 2512255692 ps
CPU time 7.05 seconds
Started Jun 26 04:54:18 PM PDT 24
Finished Jun 26 04:54:26 PM PDT 24
Peak memory 201504 kb
Host smart-c9d973e6-e7f2-428b-b090-6ce0e5cb3011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651053600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.651053600
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.1010993540
Short name T410
Test name
Test status
Simulation time 2145637982 ps
CPU time 1.22 seconds
Started Jun 26 04:54:13 PM PDT 24
Finished Jun 26 04:54:16 PM PDT 24
Peak memory 201444 kb
Host smart-ee195308-457a-4ef4-ab5b-63b560862095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010993540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.1010993540
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.2968966258
Short name T402
Test name
Test status
Simulation time 11628896613 ps
CPU time 15.77 seconds
Started Jun 26 04:54:29 PM PDT 24
Finished Jun 26 04:54:49 PM PDT 24
Peak memory 201580 kb
Host smart-a2077aa9-7d3b-46ab-88cd-dd0dfa4d1394
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968966258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.2968966258
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.3114021624
Short name T481
Test name
Test status
Simulation time 7159077054 ps
CPU time 5.56 seconds
Started Jun 26 04:54:21 PM PDT 24
Finished Jun 26 04:54:28 PM PDT 24
Peak memory 201448 kb
Host smart-d246eae1-d75d-4151-8ba5-3f65f760bba2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114021624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ultra_low_pwr.3114021624
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.995295509
Short name T664
Test name
Test status
Simulation time 2019515856 ps
CPU time 4.32 seconds
Started Jun 26 04:54:21 PM PDT 24
Finished Jun 26 04:54:26 PM PDT 24
Peak memory 201400 kb
Host smart-4afa050a-0e4a-46b6-b538-b2167fff9e39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995295509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_tes
t.995295509
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.3307513185
Short name T464
Test name
Test status
Simulation time 3192206788 ps
CPU time 8.68 seconds
Started Jun 26 04:54:23 PM PDT 24
Finished Jun 26 04:54:33 PM PDT 24
Peak memory 201572 kb
Host smart-0768df17-b082-4cf7-b8b0-229fb0ce2a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307513185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.3
307513185
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.431322917
Short name T556
Test name
Test status
Simulation time 105563735414 ps
CPU time 63.15 seconds
Started Jun 26 04:54:23 PM PDT 24
Finished Jun 26 04:55:28 PM PDT 24
Peak memory 201728 kb
Host smart-4afd222d-4a99-404a-9769-b6f15e93ecaa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431322917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_combo_detect.431322917
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.1178462435
Short name T713
Test name
Test status
Simulation time 42453730823 ps
CPU time 82.92 seconds
Started Jun 26 04:54:28 PM PDT 24
Finished Jun 26 04:55:54 PM PDT 24
Peak memory 201776 kb
Host smart-ec0b96da-3675-48dd-b1bd-09439b87ac78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178462435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_w
ith_pre_cond.1178462435
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.3619257714
Short name T420
Test name
Test status
Simulation time 3110865318 ps
CPU time 4.44 seconds
Started Jun 26 04:54:18 PM PDT 24
Finished Jun 26 04:54:24 PM PDT 24
Peak memory 201408 kb
Host smart-2056ee3c-d342-4052-bdf1-747e321b984c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619257714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ec_pwr_on_rst.3619257714
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.1366058610
Short name T190
Test name
Test status
Simulation time 3411810437 ps
CPU time 7.52 seconds
Started Jun 26 04:54:28 PM PDT 24
Finished Jun 26 04:54:38 PM PDT 24
Peak memory 201524 kb
Host smart-3625cbcd-c956-410a-a60c-e5724640c26a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366058610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_edge_detect.1366058610
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.804271168
Short name T535
Test name
Test status
Simulation time 2703681786 ps
CPU time 1.15 seconds
Started Jun 26 04:54:31 PM PDT 24
Finished Jun 26 04:54:35 PM PDT 24
Peak memory 201484 kb
Host smart-bcb233e4-5c4e-4bef-a41a-990ae88017fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804271168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.804271168
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.1334547406
Short name T671
Test name
Test status
Simulation time 2463790590 ps
CPU time 3.92 seconds
Started Jun 26 04:54:36 PM PDT 24
Finished Jun 26 04:54:43 PM PDT 24
Peak memory 201496 kb
Host smart-a02f9efe-cd59-41df-9d53-69a4a48b6e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334547406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.1334547406
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.3647968291
Short name T661
Test name
Test status
Simulation time 2172190820 ps
CPU time 5.94 seconds
Started Jun 26 04:54:24 PM PDT 24
Finished Jun 26 04:54:32 PM PDT 24
Peak memory 201520 kb
Host smart-a71c6559-173d-4f76-b8b4-0b57f034d8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647968291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.3647968291
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.3579188786
Short name T55
Test name
Test status
Simulation time 2519811057 ps
CPU time 4.14 seconds
Started Jun 26 04:54:31 PM PDT 24
Finished Jun 26 04:54:38 PM PDT 24
Peak memory 201420 kb
Host smart-2857eb6c-9097-4a26-9ec4-15d0bb7ea075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579188786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.3579188786
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.3533353036
Short name T427
Test name
Test status
Simulation time 2188936133 ps
CPU time 1.22 seconds
Started Jun 26 04:54:19 PM PDT 24
Finished Jun 26 04:54:22 PM PDT 24
Peak memory 201464 kb
Host smart-c1f8e8f0-155a-497a-b6ed-203e6ee043cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533353036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.3533353036
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.1172266214
Short name T155
Test name
Test status
Simulation time 9686098517 ps
CPU time 10.11 seconds
Started Jun 26 04:54:28 PM PDT 24
Finished Jun 26 04:54:41 PM PDT 24
Peak memory 201440 kb
Host smart-ebeb974c-b3b9-49b4-9d46-0e96e7bc8a86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172266214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_s
tress_all.1172266214
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.818595118
Short name T496
Test name
Test status
Simulation time 4255947632 ps
CPU time 1.75 seconds
Started Jun 26 04:54:20 PM PDT 24
Finished Jun 26 04:54:23 PM PDT 24
Peak memory 201712 kb
Host smart-b0bd05ff-a580-4b1f-8f29-56736e2903d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818595118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_ultra_low_pwr.818595118
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.3416723374
Short name T551
Test name
Test status
Simulation time 2009858370 ps
CPU time 5.72 seconds
Started Jun 26 04:54:27 PM PDT 24
Finished Jun 26 04:54:35 PM PDT 24
Peak memory 201460 kb
Host smart-e95a1b35-c91a-4259-ae29-ff67ed3eadd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416723374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_te
st.3416723374
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.4080832799
Short name T439
Test name
Test status
Simulation time 3661740244 ps
CPU time 10.37 seconds
Started Jun 26 04:54:25 PM PDT 24
Finished Jun 26 04:54:37 PM PDT 24
Peak memory 201516 kb
Host smart-c922e1eb-5dc8-4df7-89d0-1f28d9603ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080832799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.4
080832799
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.840872960
Short name T237
Test name
Test status
Simulation time 2636109455 ps
CPU time 1.8 seconds
Started Jun 26 04:54:24 PM PDT 24
Finished Jun 26 04:54:28 PM PDT 24
Peak memory 201412 kb
Host smart-2d4f038a-4786-4fc0-8490-5e61b073cf10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840872960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_ec_pwr_on_rst.840872960
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.2486366522
Short name T585
Test name
Test status
Simulation time 2634252405 ps
CPU time 2.33 seconds
Started Jun 26 04:54:18 PM PDT 24
Finished Jun 26 04:54:21 PM PDT 24
Peak memory 201484 kb
Host smart-b6804768-d7e2-4845-905e-3908b7470975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486366522 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.2486366522
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.1965418439
Short name T64
Test name
Test status
Simulation time 2470324083 ps
CPU time 7.77 seconds
Started Jun 26 04:54:25 PM PDT 24
Finished Jun 26 04:54:35 PM PDT 24
Peak memory 201480 kb
Host smart-0c1bd6e9-8ccd-454f-9f13-04b732438b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965418439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.1965418439
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.4266656609
Short name T233
Test name
Test status
Simulation time 2081937911 ps
CPU time 1.89 seconds
Started Jun 26 04:54:25 PM PDT 24
Finished Jun 26 04:54:29 PM PDT 24
Peak memory 201464 kb
Host smart-a239529a-44af-487b-86f2-85a3a043f81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266656609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.4266656609
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.1600675974
Short name T490
Test name
Test status
Simulation time 2555337782 ps
CPU time 1.49 seconds
Started Jun 26 04:54:32 PM PDT 24
Finished Jun 26 04:54:36 PM PDT 24
Peak memory 201340 kb
Host smart-c87c649b-5229-4908-b5cd-d80fd665e6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600675974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.1600675974
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.4124884156
Short name T720
Test name
Test status
Simulation time 2114069416 ps
CPU time 5.74 seconds
Started Jun 26 04:54:19 PM PDT 24
Finished Jun 26 04:54:27 PM PDT 24
Peak memory 201408 kb
Host smart-b5beda50-ed48-42a9-b1f8-47114a99f13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124884156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.4124884156
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1844633043
Short name T121
Test name
Test status
Simulation time 45747060118 ps
CPU time 53.78 seconds
Started Jun 26 04:54:30 PM PDT 24
Finished Jun 26 04:55:27 PM PDT 24
Peak memory 218348 kb
Host smart-f475db44-5c0a-4217-aa7d-5700c3fb5870
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844633043 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.1844633043
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.2683985428
Short name T498
Test name
Test status
Simulation time 3039663226 ps
CPU time 2.08 seconds
Started Jun 26 04:54:34 PM PDT 24
Finished Jun 26 04:54:39 PM PDT 24
Peak memory 201456 kb
Host smart-fd5fceb7-94de-4337-a760-4c8e9e2e414d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683985428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ultra_low_pwr.2683985428
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.1826779084
Short name T568
Test name
Test status
Simulation time 2028625598 ps
CPU time 1.98 seconds
Started Jun 26 04:54:21 PM PDT 24
Finished Jun 26 04:54:24 PM PDT 24
Peak memory 201504 kb
Host smart-e0671a1d-bfed-4b57-8982-46d578daafdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826779084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_te
st.1826779084
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1661992694
Short name T706
Test name
Test status
Simulation time 3295346507 ps
CPU time 2.89 seconds
Started Jun 26 04:54:24 PM PDT 24
Finished Jun 26 04:54:28 PM PDT 24
Peak memory 201500 kb
Host smart-d0b1289c-934c-4a40-b516-17844429942c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661992694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.1
661992694
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.2923847455
Short name T478
Test name
Test status
Simulation time 150840399760 ps
CPU time 399.93 seconds
Started Jun 26 04:54:29 PM PDT 24
Finished Jun 26 05:01:13 PM PDT 24
Peak memory 201804 kb
Host smart-0220f67e-8cc7-40ad-ac72-cc71f3cf0f2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923847455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.2923847455
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.2923057490
Short name T203
Test name
Test status
Simulation time 3568391328 ps
CPU time 2.18 seconds
Started Jun 26 04:54:21 PM PDT 24
Finished Jun 26 04:54:24 PM PDT 24
Peak memory 201400 kb
Host smart-ceb93975-8989-4e73-8995-99bb804815ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923057490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ec_pwr_on_rst.2923057490
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.4053313870
Short name T536
Test name
Test status
Simulation time 3110135880 ps
CPU time 2.33 seconds
Started Jun 26 04:54:22 PM PDT 24
Finished Jun 26 04:54:25 PM PDT 24
Peak memory 201384 kb
Host smart-d656f55f-41ed-46c5-839a-49e473bd2b3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053313870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_edge_detect.4053313870
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.4155912840
Short name T131
Test name
Test status
Simulation time 2698564446 ps
CPU time 1.15 seconds
Started Jun 26 04:54:18 PM PDT 24
Finished Jun 26 04:54:21 PM PDT 24
Peak memory 201508 kb
Host smart-79367519-a00c-465d-b859-bf8e74fe0979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155912840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.4155912840
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.3837650904
Short name T703
Test name
Test status
Simulation time 2487128858 ps
CPU time 4.82 seconds
Started Jun 26 04:54:33 PM PDT 24
Finished Jun 26 04:54:41 PM PDT 24
Peak memory 201480 kb
Host smart-78253219-c724-44ff-b89a-51af7b540bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837650904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.3837650904
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.2648072431
Short name T335
Test name
Test status
Simulation time 2289191302 ps
CPU time 1.12 seconds
Started Jun 26 04:54:27 PM PDT 24
Finished Jun 26 04:54:31 PM PDT 24
Peak memory 201428 kb
Host smart-d4120f27-af06-4972-8911-7930bb8375b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648072431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.2648072431
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.874674149
Short name T636
Test name
Test status
Simulation time 2511245967 ps
CPU time 6.79 seconds
Started Jun 26 04:54:35 PM PDT 24
Finished Jun 26 04:54:45 PM PDT 24
Peak memory 201516 kb
Host smart-694a9663-86e9-4b44-9cf6-0eb9a2afd430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874674149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.874674149
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.2554455367
Short name T730
Test name
Test status
Simulation time 2130029426 ps
CPU time 2.26 seconds
Started Jun 26 04:54:28 PM PDT 24
Finished Jun 26 04:54:33 PM PDT 24
Peak memory 201356 kb
Host smart-b9215511-cbaa-4aa5-9d41-0f1c8995e897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554455367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.2554455367
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.1066737127
Short name T767
Test name
Test status
Simulation time 16879980478 ps
CPU time 44.26 seconds
Started Jun 26 04:54:34 PM PDT 24
Finished Jun 26 04:55:21 PM PDT 24
Peak memory 201464 kb
Host smart-dabbbe31-a465-4aba-99f1-4aa669c5ed8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066737127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_s
tress_all.1066737127
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.1564197284
Short name T139
Test name
Test status
Simulation time 4760953374 ps
CPU time 7.03 seconds
Started Jun 26 04:54:20 PM PDT 24
Finished Jun 26 04:54:29 PM PDT 24
Peak memory 201468 kb
Host smart-edc493d7-5bee-41d5-adcb-cb1c561110f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564197284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ultra_low_pwr.1564197284
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.3603012022
Short name T691
Test name
Test status
Simulation time 2015773895 ps
CPU time 3.05 seconds
Started Jun 26 04:54:00 PM PDT 24
Finished Jun 26 04:54:11 PM PDT 24
Peak memory 201748 kb
Host smart-8e14745d-f8ac-4073-99e6-09654618a812
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603012022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.3603012022
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.580968979
Short name T436
Test name
Test status
Simulation time 3392649369 ps
CPU time 4.75 seconds
Started Jun 26 04:53:53 PM PDT 24
Finished Jun 26 04:54:00 PM PDT 24
Peak memory 201620 kb
Host smart-75e9963e-ee93-4c2b-ae40-bf38fc85e6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580968979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.580968979
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.432588966
Short name T761
Test name
Test status
Simulation time 173352489802 ps
CPU time 119.86 seconds
Started Jun 26 04:53:49 PM PDT 24
Finished Jun 26 04:55:53 PM PDT 24
Peak memory 201852 kb
Host smart-416e6469-b6b7-4b65-9125-5abd606dec03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432588966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_combo_detect.432588966
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.2788780833
Short name T467
Test name
Test status
Simulation time 2221575327 ps
CPU time 3.51 seconds
Started Jun 26 04:53:44 PM PDT 24
Finished Jun 26 04:53:52 PM PDT 24
Peak memory 201428 kb
Host smart-175bdd47-64ce-47af-9397-42dbdf0ebdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788780833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.2788780833
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1949362162
Short name T50
Test name
Test status
Simulation time 2506262680 ps
CPU time 6.42 seconds
Started Jun 26 04:53:51 PM PDT 24
Finished Jun 26 04:54:01 PM PDT 24
Peak memory 201740 kb
Host smart-460d57c3-1d90-4b7b-9a3f-25ff81c4223a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949362162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1949362162
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.3438220616
Short name T719
Test name
Test status
Simulation time 58235291730 ps
CPU time 73.98 seconds
Started Jun 26 04:53:50 PM PDT 24
Finished Jun 26 04:55:07 PM PDT 24
Peak memory 201744 kb
Host smart-795987e4-f9c1-419b-bfd5-2dd6948e660f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438220616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wi
th_pre_cond.3438220616
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.1365477245
Short name T794
Test name
Test status
Simulation time 75037944785 ps
CPU time 195.24 seconds
Started Jun 26 04:53:47 PM PDT 24
Finished Jun 26 04:57:06 PM PDT 24
Peak memory 201540 kb
Host smart-137eddfa-ae58-4229-8024-6d7177228f43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365477245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ec_pwr_on_rst.1365477245
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.167807293
Short name T85
Test name
Test status
Simulation time 3032116217 ps
CPU time 7.69 seconds
Started Jun 26 04:53:46 PM PDT 24
Finished Jun 26 04:53:58 PM PDT 24
Peak memory 201436 kb
Host smart-603d929d-b392-4fe3-bc5b-f5386799fca6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167807293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_edge_detect.167807293
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.3575374953
Short name T630
Test name
Test status
Simulation time 2637070191 ps
CPU time 2.38 seconds
Started Jun 26 04:53:42 PM PDT 24
Finished Jun 26 04:53:48 PM PDT 24
Peak memory 201508 kb
Host smart-0868f356-7c81-4786-aa07-b553d704fc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575374953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.3575374953
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.2618196784
Short name T619
Test name
Test status
Simulation time 2460004233 ps
CPU time 6.82 seconds
Started Jun 26 04:53:49 PM PDT 24
Finished Jun 26 04:54:00 PM PDT 24
Peak memory 201492 kb
Host smart-fca20d3e-209a-40c8-936a-e3ae5d1b0145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618196784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.2618196784
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.3630212216
Short name T631
Test name
Test status
Simulation time 2119073970 ps
CPU time 1.88 seconds
Started Jun 26 04:53:54 PM PDT 24
Finished Jun 26 04:53:58 PM PDT 24
Peak memory 201416 kb
Host smart-3d30c942-2686-4bf9-afb9-96f0acacf280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630212216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.3630212216
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.3955365757
Short name T692
Test name
Test status
Simulation time 2515020130 ps
CPU time 4.04 seconds
Started Jun 26 04:53:57 PM PDT 24
Finished Jun 26 04:54:03 PM PDT 24
Peak memory 201440 kb
Host smart-b5e43ef8-7a81-4d7d-b945-27cfc45c44e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955365757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.3955365757
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.1649529649
Short name T310
Test name
Test status
Simulation time 42015084908 ps
CPU time 59.79 seconds
Started Jun 26 04:53:55 PM PDT 24
Finished Jun 26 04:54:57 PM PDT 24
Peak memory 221268 kb
Host smart-8331022e-e1f3-484f-8c74-b131870bc960
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649529649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.1649529649
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.1517190320
Short name T771
Test name
Test status
Simulation time 2111942256 ps
CPU time 5.8 seconds
Started Jun 26 04:53:57 PM PDT 24
Finished Jun 26 04:54:06 PM PDT 24
Peak memory 201360 kb
Host smart-f57d1580-3e0c-4838-a547-eda45037dbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517190320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.1517190320
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.4113364471
Short name T359
Test name
Test status
Simulation time 195052628166 ps
CPU time 514.3 seconds
Started Jun 26 04:53:44 PM PDT 24
Finished Jun 26 05:02:23 PM PDT 24
Peak memory 201672 kb
Host smart-08782318-e1c7-4fd4-bce8-89d133f06ba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113364471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_st
ress_all.4113364471
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.1030843098
Short name T488
Test name
Test status
Simulation time 4134846752 ps
CPU time 6.54 seconds
Started Jun 26 04:53:45 PM PDT 24
Finished Jun 26 04:53:56 PM PDT 24
Peak memory 201460 kb
Host smart-2015b030-b064-4abd-9fbc-37e1f62ed537
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030843098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ultra_low_pwr.1030843098
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.796333937
Short name T654
Test name
Test status
Simulation time 2013740078 ps
CPU time 5.89 seconds
Started Jun 26 04:54:28 PM PDT 24
Finished Jun 26 04:54:37 PM PDT 24
Peak memory 201404 kb
Host smart-cf5296f2-2f59-4258-9e19-ca49577c5cf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796333937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_tes
t.796333937
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.3085519604
Short name T697
Test name
Test status
Simulation time 3295799547 ps
CPU time 8.89 seconds
Started Jun 26 04:54:28 PM PDT 24
Finished Jun 26 04:54:39 PM PDT 24
Peak memory 201528 kb
Host smart-e184b109-37f3-49b0-8b83-0665748e727e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085519604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.3
085519604
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.2292481927
Short name T729
Test name
Test status
Simulation time 2875878767 ps
CPU time 2.41 seconds
Started Jun 26 04:54:27 PM PDT 24
Finished Jun 26 04:54:32 PM PDT 24
Peak memory 201416 kb
Host smart-44e33d12-9ccb-42d1-b6c8-33a85d6b3028
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292481927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.2292481927
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.3633228762
Short name T180
Test name
Test status
Simulation time 4378165859 ps
CPU time 5.2 seconds
Started Jun 26 04:54:23 PM PDT 24
Finished Jun 26 04:54:29 PM PDT 24
Peak memory 201552 kb
Host smart-1e6ebfcd-8b80-4b7d-a123-13452702f9bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633228762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_edge_detect.3633228762
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.579355662
Short name T69
Test name
Test status
Simulation time 2613772934 ps
CPU time 6.36 seconds
Started Jun 26 04:54:27 PM PDT 24
Finished Jun 26 04:54:36 PM PDT 24
Peak memory 201440 kb
Host smart-087eed1f-52c6-4c7c-8e20-34678d3e6314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579355662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.579355662
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.1692614527
Short name T596
Test name
Test status
Simulation time 2463170949 ps
CPU time 7.17 seconds
Started Jun 26 04:54:24 PM PDT 24
Finished Jun 26 04:54:39 PM PDT 24
Peak memory 201432 kb
Host smart-6088f37c-ae83-4b92-a217-9a0a6c2237a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692614527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.1692614527
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.513817348
Short name T318
Test name
Test status
Simulation time 2117118144 ps
CPU time 2.02 seconds
Started Jun 26 04:54:23 PM PDT 24
Finished Jun 26 04:54:26 PM PDT 24
Peak memory 201372 kb
Host smart-092b571c-ac16-4dc8-9e2d-0fa3417a0d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513817348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.513817348
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.884176320
Short name T447
Test name
Test status
Simulation time 2527767024 ps
CPU time 2.24 seconds
Started Jun 26 04:54:26 PM PDT 24
Finished Jun 26 04:54:30 PM PDT 24
Peak memory 201428 kb
Host smart-d655b367-98ac-4997-8c3e-66f2457672be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884176320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.884176320
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.4225567729
Short name T61
Test name
Test status
Simulation time 2111715581 ps
CPU time 5.42 seconds
Started Jun 26 04:54:19 PM PDT 24
Finished Jun 26 04:54:26 PM PDT 24
Peak memory 201360 kb
Host smart-4cef24ff-d44b-431d-ae91-2f2397b869a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225567729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.4225567729
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.1774575844
Short name T429
Test name
Test status
Simulation time 8373777907 ps
CPU time 22.93 seconds
Started Jun 26 04:54:35 PM PDT 24
Finished Jun 26 04:55:00 PM PDT 24
Peak memory 201548 kb
Host smart-6457888f-21e8-49d1-b779-2c20320cf376
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774575844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s
tress_all.1774575844
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.3225512004
Short name T75
Test name
Test status
Simulation time 6653723543 ps
CPU time 7.71 seconds
Started Jun 26 04:54:36 PM PDT 24
Finished Jun 26 04:54:47 PM PDT 24
Peak memory 201548 kb
Host smart-fdd2d093-3fcb-49ac-88bd-4b621a6a4d64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225512004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ultra_low_pwr.3225512004
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.244019741
Short name T560
Test name
Test status
Simulation time 2065121079 ps
CPU time 1.35 seconds
Started Jun 26 04:54:31 PM PDT 24
Finished Jun 26 04:54:35 PM PDT 24
Peak memory 201416 kb
Host smart-6d102265-9133-4f2c-8a8c-0411e2667ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244019741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_tes
t.244019741
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.3659061911
Short name T753
Test name
Test status
Simulation time 3658385796 ps
CPU time 2.86 seconds
Started Jun 26 04:54:34 PM PDT 24
Finished Jun 26 04:54:40 PM PDT 24
Peak memory 201564 kb
Host smart-c49ea395-0697-45f2-9df8-d4db7daf61b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659061911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.3
659061911
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.625133886
Short name T279
Test name
Test status
Simulation time 159621669480 ps
CPU time 404.43 seconds
Started Jun 26 04:54:29 PM PDT 24
Finished Jun 26 05:01:17 PM PDT 24
Peak memory 201792 kb
Host smart-be3f6ad1-fd33-49aa-b53d-b7b0c57e9b35
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625133886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_combo_detect.625133886
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.2296844979
Short name T98
Test name
Test status
Simulation time 106799982281 ps
CPU time 31.59 seconds
Started Jun 26 04:54:34 PM PDT 24
Finished Jun 26 04:55:09 PM PDT 24
Peak memory 201788 kb
Host smart-698468ca-cd35-4f45-9352-5c7f3b279746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296844979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w
ith_pre_cond.2296844979
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.1835944961
Short name T413
Test name
Test status
Simulation time 2827135675 ps
CPU time 1.4 seconds
Started Jun 26 04:54:30 PM PDT 24
Finished Jun 26 04:54:34 PM PDT 24
Peak memory 201400 kb
Host smart-1eef118c-c86a-4b32-947f-43555ea3f272
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835944961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ec_pwr_on_rst.1835944961
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.871992387
Short name T224
Test name
Test status
Simulation time 2579415196 ps
CPU time 3.5 seconds
Started Jun 26 04:54:31 PM PDT 24
Finished Jun 26 04:54:38 PM PDT 24
Peak memory 201464 kb
Host smart-f7b82241-0ad7-4e7f-a52e-4c6b7d5356a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871992387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctr
l_edge_detect.871992387
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.2682086487
Short name T332
Test name
Test status
Simulation time 2614297611 ps
CPU time 7.43 seconds
Started Jun 26 04:54:32 PM PDT 24
Finished Jun 26 04:54:42 PM PDT 24
Peak memory 201512 kb
Host smart-9c5a7d0a-3c74-4087-91bf-b31d36a79478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682086487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.2682086487
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.911130980
Short name T184
Test name
Test status
Simulation time 2473669123 ps
CPU time 3.87 seconds
Started Jun 26 04:54:31 PM PDT 24
Finished Jun 26 04:54:38 PM PDT 24
Peak memory 201420 kb
Host smart-02067155-1c2a-4e60-b574-2e6d47138f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911130980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.911130980
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.1221953338
Short name T646
Test name
Test status
Simulation time 2248964681 ps
CPU time 5.96 seconds
Started Jun 26 04:54:29 PM PDT 24
Finished Jun 26 04:54:38 PM PDT 24
Peak memory 201424 kb
Host smart-aea7b368-722d-4da8-836d-19cb45b311db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221953338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.1221953338
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.2472702753
Short name T509
Test name
Test status
Simulation time 2520433253 ps
CPU time 3.92 seconds
Started Jun 26 04:54:25 PM PDT 24
Finished Jun 26 04:54:32 PM PDT 24
Peak memory 201420 kb
Host smart-eb047b94-6192-48b1-bf60-d6ee2e4d3d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472702753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.2472702753
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.3414817737
Short name T632
Test name
Test status
Simulation time 2115784509 ps
CPU time 3.37 seconds
Started Jun 26 04:54:35 PM PDT 24
Finished Jun 26 04:54:41 PM PDT 24
Peak memory 201444 kb
Host smart-98f20caf-f1c7-4a78-ba49-9d65908eca52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414817737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.3414817737
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.3631813570
Short name T609
Test name
Test status
Simulation time 6625736689 ps
CPU time 5.2 seconds
Started Jun 26 04:54:24 PM PDT 24
Finished Jun 26 04:54:31 PM PDT 24
Peak memory 201488 kb
Host smart-ba44feb7-b011-4e50-bf0c-a85baf07a0a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631813570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s
tress_all.3631813570
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2741630792
Short name T105
Test name
Test status
Simulation time 65409355888 ps
CPU time 82.77 seconds
Started Jun 26 04:54:29 PM PDT 24
Finished Jun 26 04:55:55 PM PDT 24
Peak memory 210204 kb
Host smart-003b5dee-7f87-481e-93b6-7887b0076cfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741630792 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.2741630792
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.2500940833
Short name T513
Test name
Test status
Simulation time 12938526484 ps
CPU time 8.1 seconds
Started Jun 26 04:54:28 PM PDT 24
Finished Jun 26 04:54:39 PM PDT 24
Peak memory 201552 kb
Host smart-7635bf13-2e45-46a7-bccd-16c7074f3ee7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500940833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ultra_low_pwr.2500940833
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.1021827398
Short name T435
Test name
Test status
Simulation time 2048400485 ps
CPU time 1.56 seconds
Started Jun 26 04:54:52 PM PDT 24
Finished Jun 26 04:54:55 PM PDT 24
Peak memory 201412 kb
Host smart-c7358eba-25fa-415c-b042-71c4b957da85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021827398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.1021827398
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.896017324
Short name T209
Test name
Test status
Simulation time 4027336553 ps
CPU time 1.79 seconds
Started Jun 26 04:54:35 PM PDT 24
Finished Jun 26 04:54:40 PM PDT 24
Peak memory 201492 kb
Host smart-ce37cacc-9e99-4d96-9572-c8c0f23967d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896017324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.896017324
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.1745863639
Short name T354
Test name
Test status
Simulation time 159785472393 ps
CPU time 392.19 seconds
Started Jun 26 04:54:36 PM PDT 24
Finished Jun 26 05:01:11 PM PDT 24
Peak memory 201784 kb
Host smart-ce4063ed-4d55-4431-b4d5-4eef9d6c0261
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745863639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_combo_detect.1745863639
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.3467961776
Short name T651
Test name
Test status
Simulation time 2682641438 ps
CPU time 2.17 seconds
Started Jun 26 04:54:31 PM PDT 24
Finished Jun 26 04:54:37 PM PDT 24
Peak memory 201408 kb
Host smart-286f667d-be36-493e-aa53-9d48a8e6c66f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467961776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ec_pwr_on_rst.3467961776
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.2100728252
Short name T8
Test name
Test status
Simulation time 2805446457 ps
CPU time 7.5 seconds
Started Jun 26 04:54:35 PM PDT 24
Finished Jun 26 04:54:46 PM PDT 24
Peak memory 201484 kb
Host smart-d169451b-3212-4bba-bb02-6c10597bfb19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100728252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_edge_detect.2100728252
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.1058795435
Short name T68
Test name
Test status
Simulation time 2624377664 ps
CPU time 2.32 seconds
Started Jun 26 04:54:37 PM PDT 24
Finished Jun 26 04:54:42 PM PDT 24
Peak memory 201432 kb
Host smart-2f73c82e-71c2-4ec2-a129-0e5eeadff1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058795435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.1058795435
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.1317549649
Short name T245
Test name
Test status
Simulation time 2480912052 ps
CPU time 2.36 seconds
Started Jun 26 04:54:24 PM PDT 24
Finished Jun 26 04:54:29 PM PDT 24
Peak memory 201424 kb
Host smart-cacde64a-fb6b-4b3e-af83-820c9b5db40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317549649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.1317549649
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.117874831
Short name T479
Test name
Test status
Simulation time 2020710771 ps
CPU time 4.43 seconds
Started Jun 26 04:54:29 PM PDT 24
Finished Jun 26 04:54:37 PM PDT 24
Peak memory 201424 kb
Host smart-0b537733-0be8-47da-842a-91bdee2f6129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117874831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.117874831
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.3774872055
Short name T710
Test name
Test status
Simulation time 2522179107 ps
CPU time 2.4 seconds
Started Jun 26 04:54:31 PM PDT 24
Finished Jun 26 04:54:36 PM PDT 24
Peak memory 201420 kb
Host smart-3a078213-7698-4c6e-acd0-3dd49fa6bc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774872055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.3774872055
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.3178491153
Short name T434
Test name
Test status
Simulation time 2111040383 ps
CPU time 5.23 seconds
Started Jun 26 04:54:34 PM PDT 24
Finished Jun 26 04:54:42 PM PDT 24
Peak memory 201352 kb
Host smart-dd3c902b-4df0-4b13-9190-fe871052aedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178491153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.3178491153
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.8188930
Short name T494
Test name
Test status
Simulation time 15111486056 ps
CPU time 4.29 seconds
Started Jun 26 04:54:38 PM PDT 24
Finished Jun 26 04:54:46 PM PDT 24
Peak memory 201456 kb
Host smart-afb81a1f-0fd4-47ec-a9b2-9c267798a89b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8188930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stre
ss_all.8188930
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.1229641082
Short name T649
Test name
Test status
Simulation time 19613182358 ps
CPU time 46.28 seconds
Started Jun 26 04:54:43 PM PDT 24
Finished Jun 26 04:55:31 PM PDT 24
Peak memory 210100 kb
Host smart-0950e9ff-0aa5-4ef9-80e1-49baadeee0eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229641082 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.1229641082
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.2980253826
Short name T400
Test name
Test status
Simulation time 2733793125790 ps
CPU time 144.38 seconds
Started Jun 26 04:54:34 PM PDT 24
Finished Jun 26 04:57:01 PM PDT 24
Peak memory 201464 kb
Host smart-add239f0-459d-4445-9e99-2a8ae00690e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980253826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.2980253826
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.513441677
Short name T418
Test name
Test status
Simulation time 2012288034 ps
CPU time 5.45 seconds
Started Jun 26 04:54:36 PM PDT 24
Finished Jun 26 04:54:45 PM PDT 24
Peak memory 201432 kb
Host smart-4bcee799-2358-4948-9aab-499c886c3b3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513441677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_tes
t.513441677
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3976236799
Short name T708
Test name
Test status
Simulation time 3486716387 ps
CPU time 8.84 seconds
Started Jun 26 04:54:42 PM PDT 24
Finished Jun 26 04:54:53 PM PDT 24
Peak memory 201500 kb
Host smart-7e766be3-78eb-4cdb-bd6d-20f7085eae12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976236799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.3
976236799
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.1658819804
Short name T367
Test name
Test status
Simulation time 109495624531 ps
CPU time 73.46 seconds
Started Jun 26 04:54:50 PM PDT 24
Finished Jun 26 04:56:05 PM PDT 24
Peak memory 201780 kb
Host smart-32834353-ecbf-44cf-b881-adc4bdac026e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658819804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_combo_detect.1658819804
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.2189800499
Short name T81
Test name
Test status
Simulation time 105941699205 ps
CPU time 266.96 seconds
Started Jun 26 04:54:38 PM PDT 24
Finished Jun 26 04:59:08 PM PDT 24
Peak memory 201788 kb
Host smart-d89ec72b-2c01-428f-9434-92a69ab679c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189800499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_w
ith_pre_cond.2189800499
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.828432697
Short name T523
Test name
Test status
Simulation time 3266362629 ps
CPU time 1.98 seconds
Started Jun 26 04:54:25 PM PDT 24
Finished Jun 26 04:54:29 PM PDT 24
Peak memory 201412 kb
Host smart-86903e2c-b50b-4b11-b05e-1f3d5e93a3fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828432697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_ec_pwr_on_rst.828432697
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.1643217162
Short name T581
Test name
Test status
Simulation time 2629012299 ps
CPU time 2.44 seconds
Started Jun 26 04:54:36 PM PDT 24
Finished Jun 26 04:54:41 PM PDT 24
Peak memory 201484 kb
Host smart-bd61ebd3-c562-498a-a123-2744dc2c755c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643217162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.1643217162
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.858164717
Short name T533
Test name
Test status
Simulation time 2503699437 ps
CPU time 1.84 seconds
Started Jun 26 04:54:30 PM PDT 24
Finished Jun 26 04:54:35 PM PDT 24
Peak memory 201436 kb
Host smart-77d59a90-4b8e-40f4-bfc2-01a79f3cfb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858164717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.858164717
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.1744806722
Short name T56
Test name
Test status
Simulation time 2157925229 ps
CPU time 5.87 seconds
Started Jun 26 04:54:29 PM PDT 24
Finished Jun 26 04:54:38 PM PDT 24
Peak memory 201424 kb
Host smart-42bcd300-c521-4a7b-8ab4-362b8caf8aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744806722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.1744806722
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.1307835916
Short name T799
Test name
Test status
Simulation time 2511596283 ps
CPU time 7.17 seconds
Started Jun 26 04:54:34 PM PDT 24
Finished Jun 26 04:54:44 PM PDT 24
Peak memory 201464 kb
Host smart-74644cd7-1cb9-4abf-be88-45fcc99d7860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307835916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.1307835916
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.2234946036
Short name T803
Test name
Test status
Simulation time 2114776390 ps
CPU time 3.23 seconds
Started Jun 26 04:54:34 PM PDT 24
Finished Jun 26 04:54:40 PM PDT 24
Peak memory 201360 kb
Host smart-66807454-4b37-4655-bb21-75641e4818fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234946036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.2234946036
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.3682952900
Short name T278
Test name
Test status
Simulation time 101957834328 ps
CPU time 64.94 seconds
Started Jun 26 04:54:29 PM PDT 24
Finished Jun 26 04:55:36 PM PDT 24
Peak memory 201724 kb
Host smart-6b27750b-8b84-4cba-b2d1-c3f46b506738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682952900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.3682952900
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.162461775
Short name T38
Test name
Test status
Simulation time 66871907029 ps
CPU time 43.47 seconds
Started Jun 26 04:54:47 PM PDT 24
Finished Jun 26 04:55:33 PM PDT 24
Peak memory 210104 kb
Host smart-1f0b401d-fa86-4d1f-84b1-de30ec620d80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162461775 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.162461775
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.1538791643
Short name T23
Test name
Test status
Simulation time 1934336094496 ps
CPU time 219.02 seconds
Started Jun 26 04:54:25 PM PDT 24
Finished Jun 26 04:58:06 PM PDT 24
Peak memory 201512 kb
Host smart-72b371da-ee0a-4e47-a798-bb633d7d5613
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538791643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ultra_low_pwr.1538791643
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.3878314671
Short name T680
Test name
Test status
Simulation time 2029167986 ps
CPU time 1.84 seconds
Started Jun 26 04:54:29 PM PDT 24
Finished Jun 26 04:54:34 PM PDT 24
Peak memory 201420 kb
Host smart-0786e43e-eb2a-4283-8a0e-e2a2d37fcbd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878314671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_te
st.3878314671
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.1404409739
Short name T782
Test name
Test status
Simulation time 57474946440 ps
CPU time 72.42 seconds
Started Jun 26 04:54:37 PM PDT 24
Finished Jun 26 04:55:53 PM PDT 24
Peak memory 201604 kb
Host smart-3887fc02-4934-406d-ae2f-d7e8746fed45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404409739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.1
404409739
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.1414487847
Short name T679
Test name
Test status
Simulation time 96927035566 ps
CPU time 66.28 seconds
Started Jun 26 04:54:32 PM PDT 24
Finished Jun 26 04:55:41 PM PDT 24
Peak memory 201744 kb
Host smart-5bc0a18c-5187-4cb7-ad80-ffd4cf6de8cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414487847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_combo_detect.1414487847
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.2921393267
Short name T314
Test name
Test status
Simulation time 3536798935 ps
CPU time 2.8 seconds
Started Jun 26 04:54:35 PM PDT 24
Finished Jun 26 04:54:40 PM PDT 24
Peak memory 201396 kb
Host smart-45d491b0-6e50-4b59-b7a0-f68b7539572a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921393267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ec_pwr_on_rst.2921393267
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.1573626256
Short name T40
Test name
Test status
Simulation time 6472600557 ps
CPU time 7.07 seconds
Started Jun 26 04:54:38 PM PDT 24
Finished Jun 26 04:54:48 PM PDT 24
Peak memory 201460 kb
Host smart-395ab5e3-282f-4a0a-94b6-4845ccfc9d6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573626256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_edge_detect.1573626256
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.2297635453
Short name T219
Test name
Test status
Simulation time 2611966681 ps
CPU time 7.05 seconds
Started Jun 26 04:54:31 PM PDT 24
Finished Jun 26 04:54:41 PM PDT 24
Peak memory 201424 kb
Host smart-326bfb0c-3441-4529-9df7-16c10858225e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297635453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.2297635453
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.1088562430
Short name T558
Test name
Test status
Simulation time 2522115633 ps
CPU time 1.39 seconds
Started Jun 26 04:54:32 PM PDT 24
Finished Jun 26 04:54:37 PM PDT 24
Peak memory 201444 kb
Host smart-3761fbc5-e32a-439a-a7e9-a10424c0d425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088562430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.1088562430
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.2384659481
Short name T244
Test name
Test status
Simulation time 2033456006 ps
CPU time 4.21 seconds
Started Jun 26 04:54:30 PM PDT 24
Finished Jun 26 04:54:38 PM PDT 24
Peak memory 201352 kb
Host smart-f68cbba3-0d51-4dc0-8a0f-d6fbf87ea41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384659481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.2384659481
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.1938459039
Short name T648
Test name
Test status
Simulation time 2515798350 ps
CPU time 6.18 seconds
Started Jun 26 04:54:25 PM PDT 24
Finished Jun 26 04:54:34 PM PDT 24
Peak memory 201440 kb
Host smart-fcfec04b-67d7-4049-8173-d122b38198c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938459039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.1938459039
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.2390211563
Short name T93
Test name
Test status
Simulation time 2112368671 ps
CPU time 5.7 seconds
Started Jun 26 04:54:33 PM PDT 24
Finished Jun 26 04:54:42 PM PDT 24
Peak memory 201360 kb
Host smart-69711856-4eb8-41b6-89f1-1a21217d614a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390211563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.2390211563
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.2099908501
Short name T445
Test name
Test status
Simulation time 7445798341 ps
CPU time 2.54 seconds
Started Jun 26 04:54:38 PM PDT 24
Finished Jun 26 04:54:47 PM PDT 24
Peak memory 201456 kb
Host smart-a10107a5-cdfe-4f99-b8fc-95c201e1dd95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099908501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_s
tress_all.2099908501
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2912314461
Short name T352
Test name
Test status
Simulation time 39449091476 ps
CPU time 79.76 seconds
Started Jun 26 04:54:30 PM PDT 24
Finished Jun 26 04:55:53 PM PDT 24
Peak memory 210104 kb
Host smart-2bf0a00d-9349-4bcc-8296-3ddf5c6f1941
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912314461 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.2912314461
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1222534454
Short name T7
Test name
Test status
Simulation time 6385165412 ps
CPU time 6.24 seconds
Started Jun 26 04:54:30 PM PDT 24
Finished Jun 26 04:54:39 PM PDT 24
Peak memory 201488 kb
Host smart-64bd9858-1a50-4284-b8d3-ec9ef46cb01a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222534454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.1222534454
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.2351573706
Short name T766
Test name
Test status
Simulation time 2010894755 ps
CPU time 5.65 seconds
Started Jun 26 04:54:38 PM PDT 24
Finished Jun 26 04:54:47 PM PDT 24
Peak memory 201516 kb
Host smart-3f4a3f2c-0683-4493-8121-5a0ad4e5f591
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351573706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te
st.2351573706
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1086786597
Short name T117
Test name
Test status
Simulation time 3438971447 ps
CPU time 9.93 seconds
Started Jun 26 04:54:35 PM PDT 24
Finished Jun 26 04:54:47 PM PDT 24
Peak memory 201540 kb
Host smart-e4fc758f-4e93-41b6-9cd4-74ab3295dc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086786597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.1
086786597
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.1129203374
Short name T450
Test name
Test status
Simulation time 79768706020 ps
CPU time 103.31 seconds
Started Jun 26 04:54:41 PM PDT 24
Finished Jun 26 04:56:26 PM PDT 24
Peak memory 201840 kb
Host smart-61215043-8b44-43fe-a7dd-934762669d97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129203374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.1129203374
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.561550845
Short name T604
Test name
Test status
Simulation time 76466563190 ps
CPU time 182.52 seconds
Started Jun 26 04:54:32 PM PDT 24
Finished Jun 26 04:57:37 PM PDT 24
Peak memory 201776 kb
Host smart-65811441-f55d-4481-8b78-66032183568e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561550845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_wi
th_pre_cond.561550845
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.1508136548
Short name T471
Test name
Test status
Simulation time 4098004396 ps
CPU time 3.2 seconds
Started Jun 26 04:54:27 PM PDT 24
Finished Jun 26 04:54:33 PM PDT 24
Peak memory 201408 kb
Host smart-54904415-2d7e-4ab5-9119-8a0d5c32bc32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508136548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ec_pwr_on_rst.1508136548
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.524219033
Short name T167
Test name
Test status
Simulation time 4179131072 ps
CPU time 2.7 seconds
Started Jun 26 04:54:33 PM PDT 24
Finished Jun 26 04:54:38 PM PDT 24
Peak memory 201432 kb
Host smart-3b16dcf6-cd5c-49ed-a3ba-23af1e91dd7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524219033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctr
l_edge_detect.524219033
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3833771265
Short name T676
Test name
Test status
Simulation time 2656276293 ps
CPU time 1.23 seconds
Started Jun 26 04:54:51 PM PDT 24
Finished Jun 26 04:54:53 PM PDT 24
Peak memory 201440 kb
Host smart-bcd3b9cb-1365-43d0-9e55-c48fc149a4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833771265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.3833771265
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.2948331448
Short name T618
Test name
Test status
Simulation time 2472263808 ps
CPU time 7.89 seconds
Started Jun 26 04:54:27 PM PDT 24
Finished Jun 26 04:54:37 PM PDT 24
Peak memory 201436 kb
Host smart-287fb961-6130-4078-9a10-1da211043d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948331448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.2948331448
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.116119194
Short name T647
Test name
Test status
Simulation time 2178973401 ps
CPU time 3.28 seconds
Started Jun 26 04:54:38 PM PDT 24
Finished Jun 26 04:54:44 PM PDT 24
Peak memory 201428 kb
Host smart-615d8ef3-48e3-487a-98d1-2ec9de2c0c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116119194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.116119194
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.2671896953
Short name T331
Test name
Test status
Simulation time 2667037950 ps
CPU time 1.08 seconds
Started Jun 26 04:54:37 PM PDT 24
Finished Jun 26 04:54:42 PM PDT 24
Peak memory 201424 kb
Host smart-750ed5b3-3cbf-4649-bab3-7322203c4792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671896953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.2671896953
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.3667986277
Short name T465
Test name
Test status
Simulation time 2127385365 ps
CPU time 1.91 seconds
Started Jun 26 04:54:35 PM PDT 24
Finished Jun 26 04:54:40 PM PDT 24
Peak memory 201408 kb
Host smart-1d1e73b5-984a-42c0-ac52-40d45cddc590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667986277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.3667986277
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.3633086419
Short name T451
Test name
Test status
Simulation time 10120969301 ps
CPU time 26.53 seconds
Started Jun 26 04:54:40 PM PDT 24
Finished Jun 26 04:55:09 PM PDT 24
Peak memory 201552 kb
Host smart-36556406-b834-4c96-8738-b05c99dc08f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633086419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.3633086419
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2994964456
Short name T398
Test name
Test status
Simulation time 86481896958 ps
CPU time 58.31 seconds
Started Jun 26 04:54:42 PM PDT 24
Finished Jun 26 04:55:42 PM PDT 24
Peak memory 214980 kb
Host smart-40da1e13-989f-408a-927d-7328a8f7bad5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994964456 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.2994964456
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.2007624355
Short name T474
Test name
Test status
Simulation time 16573493926 ps
CPU time 2.73 seconds
Started Jun 26 04:54:40 PM PDT 24
Finished Jun 26 04:54:45 PM PDT 24
Peak memory 201456 kb
Host smart-4ed9d979-66b8-4040-861f-0d75daa2a71b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007624355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ultra_low_pwr.2007624355
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.3565751792
Short name T417
Test name
Test status
Simulation time 2026625703 ps
CPU time 2.4 seconds
Started Jun 26 04:54:36 PM PDT 24
Finished Jun 26 04:54:42 PM PDT 24
Peak memory 201456 kb
Host smart-bc1e22c1-dc7b-4313-8144-a3d127274117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565751792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.3565751792
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.3934891969
Short name T47
Test name
Test status
Simulation time 4039274899 ps
CPU time 5.53 seconds
Started Jun 26 04:54:48 PM PDT 24
Finished Jun 26 04:54:56 PM PDT 24
Peak memory 201472 kb
Host smart-d36e17cb-9f66-4b44-b2d3-0bed520a182d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934891969 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.3
934891969
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.19084969
Short name T385
Test name
Test status
Simulation time 93120099683 ps
CPU time 238.51 seconds
Started Jun 26 04:54:37 PM PDT 24
Finished Jun 26 04:58:39 PM PDT 24
Peak memory 201744 kb
Host smart-2062a7fc-f960-48f8-898b-8f87a76913d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19084969 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctr
l_combo_detect.19084969
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2740930920
Short name T650
Test name
Test status
Simulation time 3340614662 ps
CPU time 8.63 seconds
Started Jun 26 04:54:32 PM PDT 24
Finished Jun 26 04:54:44 PM PDT 24
Peak memory 201404 kb
Host smart-e6480683-bf20-4c3a-9d10-97fe00a9a062
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740930920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ec_pwr_on_rst.2740930920
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.2884724522
Short name T776
Test name
Test status
Simulation time 3242388398 ps
CPU time 2.27 seconds
Started Jun 26 04:54:38 PM PDT 24
Finished Jun 26 04:54:44 PM PDT 24
Peak memory 201408 kb
Host smart-11322d84-a027-464c-86bb-98f88107c127
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884724522 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_edge_detect.2884724522
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3294887340
Short name T430
Test name
Test status
Simulation time 2636013449 ps
CPU time 2.54 seconds
Started Jun 26 04:54:37 PM PDT 24
Finished Jun 26 04:54:43 PM PDT 24
Peak memory 201428 kb
Host smart-6b7ad016-01ff-4eba-9d58-ec62e5082879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294887340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.3294887340
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.2597174291
Short name T666
Test name
Test status
Simulation time 2452257640 ps
CPU time 3.89 seconds
Started Jun 26 04:54:39 PM PDT 24
Finished Jun 26 04:54:46 PM PDT 24
Peak memory 201484 kb
Host smart-1c99524c-bda1-43ad-a6b3-6491b04521bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597174291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.2597174291
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.3483487867
Short name T508
Test name
Test status
Simulation time 2263419318 ps
CPU time 2.11 seconds
Started Jun 26 04:54:48 PM PDT 24
Finished Jun 26 04:54:53 PM PDT 24
Peak memory 201536 kb
Host smart-321e704e-5cc1-4a0b-9b90-1f8fbe88c05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483487867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.3483487867
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.2832997930
Short name T598
Test name
Test status
Simulation time 2528315629 ps
CPU time 2.37 seconds
Started Jun 26 04:54:37 PM PDT 24
Finished Jun 26 04:54:42 PM PDT 24
Peak memory 201432 kb
Host smart-cbf098bc-9804-44d4-b374-e48dbaed7fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832997930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.2832997930
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.194992987
Short name T747
Test name
Test status
Simulation time 2109463756 ps
CPU time 5.96 seconds
Started Jun 26 04:54:45 PM PDT 24
Finished Jun 26 04:54:53 PM PDT 24
Peak memory 201352 kb
Host smart-b2941a6c-32af-47e1-8b6c-3c2dffc25f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194992987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.194992987
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.1869984841
Short name T463
Test name
Test status
Simulation time 167721958953 ps
CPU time 218.33 seconds
Started Jun 26 04:54:48 PM PDT 24
Finished Jun 26 04:58:29 PM PDT 24
Peak memory 201836 kb
Host smart-383d1719-50d5-489b-8b4b-9525b321d158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869984841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.1869984841
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.3721868925
Short name T792
Test name
Test status
Simulation time 18893154010 ps
CPU time 13.48 seconds
Started Jun 26 04:54:36 PM PDT 24
Finished Jun 26 04:54:53 PM PDT 24
Peak memory 209852 kb
Host smart-d5322822-77e7-4a29-9370-c89a33a2137c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721868925 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.3721868925
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.386950299
Short name T77
Test name
Test status
Simulation time 8158621970 ps
CPU time 1.05 seconds
Started Jun 26 04:54:44 PM PDT 24
Finished Jun 26 04:54:46 PM PDT 24
Peak memory 201464 kb
Host smart-43a54068-d6ca-4602-8e05-9b1c2ddbe78f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386950299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_ultra_low_pwr.386950299
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.2893267853
Short name T297
Test name
Test status
Simulation time 2013824113 ps
CPU time 4.11 seconds
Started Jun 26 04:54:47 PM PDT 24
Finished Jun 26 04:54:54 PM PDT 24
Peak memory 201424 kb
Host smart-c7b52da1-aab4-4868-a948-94766917087f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893267853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_te
st.2893267853
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2989357273
Short name T745
Test name
Test status
Simulation time 3642263041 ps
CPU time 3.03 seconds
Started Jun 26 04:54:38 PM PDT 24
Finished Jun 26 04:54:44 PM PDT 24
Peak memory 201524 kb
Host smart-23d6b490-882a-4000-80eb-38a8a20aac97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989357273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.2
989357273
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.117866760
Short name T36
Test name
Test status
Simulation time 37695444824 ps
CPU time 26.63 seconds
Started Jun 26 04:54:38 PM PDT 24
Finished Jun 26 04:55:07 PM PDT 24
Peak memory 201752 kb
Host smart-fc6ee779-ec7a-4cca-9a3b-a9de702910f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117866760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_wi
th_pre_cond.117866760
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.3773180967
Short name T242
Test name
Test status
Simulation time 3375632831 ps
CPU time 2.58 seconds
Started Jun 26 04:54:47 PM PDT 24
Finished Jun 26 04:54:52 PM PDT 24
Peak memory 201508 kb
Host smart-4b00ea96-8d6d-4e11-ad46-4964a6c23bfb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773180967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ec_pwr_on_rst.3773180967
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.540637278
Short name T228
Test name
Test status
Simulation time 3944786214 ps
CPU time 2.57 seconds
Started Jun 26 04:54:35 PM PDT 24
Finished Jun 26 04:54:40 PM PDT 24
Peak memory 201392 kb
Host smart-033fd1a6-11c0-46ff-8401-a9bda29da0a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540637278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctr
l_edge_detect.540637278
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.2983060299
Short name T147
Test name
Test status
Simulation time 2612878847 ps
CPU time 7.1 seconds
Started Jun 26 04:54:47 PM PDT 24
Finished Jun 26 04:54:57 PM PDT 24
Peak memory 201516 kb
Host smart-a585691d-4f85-47d0-be2f-f7edc67d3bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983060299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.2983060299
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.2807216484
Short name T787
Test name
Test status
Simulation time 2482807490 ps
CPU time 3.91 seconds
Started Jun 26 04:54:35 PM PDT 24
Finished Jun 26 04:54:41 PM PDT 24
Peak memory 201424 kb
Host smart-c1120bf9-894c-450a-901d-88aa740299e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807216484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.2807216484
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.3303181196
Short name T492
Test name
Test status
Simulation time 2102136990 ps
CPU time 6.2 seconds
Started Jun 26 04:54:40 PM PDT 24
Finished Jun 26 04:54:49 PM PDT 24
Peak memory 201424 kb
Host smart-169a0e75-df52-40c7-a952-cca2716eca17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303181196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.3303181196
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.879273097
Short name T662
Test name
Test status
Simulation time 2537865394 ps
CPU time 2.24 seconds
Started Jun 26 04:54:35 PM PDT 24
Finished Jun 26 04:54:40 PM PDT 24
Peak memory 201336 kb
Host smart-f542719b-0d70-4d04-9d71-49c43809aa1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879273097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.879273097
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.2309826775
Short name T514
Test name
Test status
Simulation time 2117559292 ps
CPU time 3.53 seconds
Started Jun 26 04:54:39 PM PDT 24
Finished Jun 26 04:54:45 PM PDT 24
Peak memory 201376 kb
Host smart-4ac0d787-facd-467c-a85c-30b616e097df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309826775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.2309826775
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.385282071
Short name T705
Test name
Test status
Simulation time 14413835087 ps
CPU time 10.15 seconds
Started Jun 26 04:54:35 PM PDT 24
Finished Jun 26 04:54:49 PM PDT 24
Peak memory 201740 kb
Host smart-3a2518ed-e8ee-4d55-ac22-245d4e7eb0f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385282071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_st
ress_all.385282071
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2626308841
Short name T84
Test name
Test status
Simulation time 5001436189 ps
CPU time 8.04 seconds
Started Jun 26 04:54:36 PM PDT 24
Finished Jun 26 04:54:48 PM PDT 24
Peak memory 201508 kb
Host smart-d7668928-5b51-4637-993d-af4da44e142e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626308841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ultra_low_pwr.2626308841
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.3814952580
Short name T600
Test name
Test status
Simulation time 2018344777 ps
CPU time 3.14 seconds
Started Jun 26 04:54:50 PM PDT 24
Finished Jun 26 04:54:54 PM PDT 24
Peak memory 201528 kb
Host smart-e0bbe841-d48e-4525-af5c-d3f184f3b0c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814952580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te
st.3814952580
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.591946251
Short name T118
Test name
Test status
Simulation time 96688251260 ps
CPU time 237.26 seconds
Started Jun 26 04:54:33 PM PDT 24
Finished Jun 26 04:58:34 PM PDT 24
Peak memory 201636 kb
Host smart-dc7150fe-2e09-430a-b4bf-11280f3c3506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591946251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.591946251
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.833883401
Short name T220
Test name
Test status
Simulation time 48492560818 ps
CPU time 132.78 seconds
Started Jun 26 04:54:38 PM PDT 24
Finished Jun 26 04:56:54 PM PDT 24
Peak memory 201832 kb
Host smart-c500e8dd-5b53-4d51-93f4-7151b0ba7047
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833883401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_combo_detect.833883401
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2435572680
Short name T699
Test name
Test status
Simulation time 201030087560 ps
CPU time 131.72 seconds
Started Jun 26 04:54:36 PM PDT 24
Finished Jun 26 04:56:55 PM PDT 24
Peak memory 201820 kb
Host smart-3d40b772-00a8-4e8f-91ca-8a73913d1fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435572680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_w
ith_pre_cond.2435572680
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.754524874
Short name T455
Test name
Test status
Simulation time 3188347981 ps
CPU time 2.59 seconds
Started Jun 26 04:54:51 PM PDT 24
Finished Jun 26 04:54:55 PM PDT 24
Peak memory 201460 kb
Host smart-a3970a0f-17ec-495c-8fae-74a0ace136ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754524874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_ec_pwr_on_rst.754524874
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.1451910346
Short name T43
Test name
Test status
Simulation time 6185607894 ps
CPU time 1.51 seconds
Started Jun 26 04:54:41 PM PDT 24
Finished Jun 26 04:54:45 PM PDT 24
Peak memory 201492 kb
Host smart-f8449a32-025e-4ec3-923f-ec19314c8bb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451910346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.1451910346
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.1791705001
Short name T452
Test name
Test status
Simulation time 2617867609 ps
CPU time 4.28 seconds
Started Jun 26 04:54:49 PM PDT 24
Finished Jun 26 04:54:55 PM PDT 24
Peak memory 201532 kb
Host smart-4eb28e50-737f-4551-ba2f-60142a15109d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791705001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.1791705001
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.2149294556
Short name T188
Test name
Test status
Simulation time 2480621832 ps
CPU time 2.19 seconds
Started Jun 26 04:54:55 PM PDT 24
Finished Jun 26 04:54:59 PM PDT 24
Peak memory 201484 kb
Host smart-a14d66cb-0c60-4b03-8432-36f43c11777a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149294556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.2149294556
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.3998142466
Short name T532
Test name
Test status
Simulation time 2125733543 ps
CPU time 3.22 seconds
Started Jun 26 04:54:46 PM PDT 24
Finished Jun 26 04:54:52 PM PDT 24
Peak memory 201476 kb
Host smart-9cdb0f69-8828-4ee9-b3a8-5b8365be812c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998142466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.3998142466
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.4216119002
Short name T751
Test name
Test status
Simulation time 2512179308 ps
CPU time 7.21 seconds
Started Jun 26 04:54:36 PM PDT 24
Finished Jun 26 04:54:47 PM PDT 24
Peak memory 201516 kb
Host smart-7bd64dea-ac16-4a35-b2f3-4b5e61610d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216119002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.4216119002
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.4125411372
Short name T744
Test name
Test status
Simulation time 2110365138 ps
CPU time 5.48 seconds
Started Jun 26 04:54:37 PM PDT 24
Finished Jun 26 04:54:46 PM PDT 24
Peak memory 201428 kb
Host smart-f8af571f-b4e0-4043-9d37-fe7f735ab716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125411372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.4125411372
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.4226794911
Short name T571
Test name
Test status
Simulation time 8862533335 ps
CPU time 6.24 seconds
Started Jun 26 04:54:44 PM PDT 24
Finished Jun 26 04:54:52 PM PDT 24
Peak memory 201556 kb
Host smart-ee74a688-1b01-4b52-8727-7d5d28b4efc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226794911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_s
tress_all.4226794911
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.4103829459
Short name T168
Test name
Test status
Simulation time 2012518807 ps
CPU time 5.93 seconds
Started Jun 26 04:54:56 PM PDT 24
Finished Jun 26 04:55:04 PM PDT 24
Peak memory 201480 kb
Host smart-1187da5d-638a-4dec-8cf4-3417756ab311
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103829459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.4103829459
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.1731625347
Short name T456
Test name
Test status
Simulation time 3645551330 ps
CPU time 2.18 seconds
Started Jun 26 04:54:52 PM PDT 24
Finished Jun 26 04:54:56 PM PDT 24
Peak memory 201544 kb
Host smart-90d63ac4-c905-47de-bcf1-84be45b19c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731625347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.1
731625347
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.1126521260
Short name T261
Test name
Test status
Simulation time 103772144733 ps
CPU time 148.25 seconds
Started Jun 26 04:54:46 PM PDT 24
Finished Jun 26 04:57:16 PM PDT 24
Peak memory 201760 kb
Host smart-729c55de-0a69-4bfe-90d0-eab7a779e11c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126521260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.1126521260
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.3777937664
Short name T665
Test name
Test status
Simulation time 48136123077 ps
CPU time 117.51 seconds
Started Jun 26 04:54:52 PM PDT 24
Finished Jun 26 04:56:51 PM PDT 24
Peak memory 201824 kb
Host smart-54e42a18-f8b5-4a0d-8f70-494925921348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777937664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_w
ith_pre_cond.3777937664
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.535912913
Short name T681
Test name
Test status
Simulation time 3317531673 ps
CPU time 4.86 seconds
Started Jun 26 04:55:14 PM PDT 24
Finished Jun 26 04:55:23 PM PDT 24
Peak memory 201404 kb
Host smart-8c15ed3c-25f6-4ea1-a339-09a5fd63a234
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535912913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_ec_pwr_on_rst.535912913
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.3252841965
Short name T156
Test name
Test status
Simulation time 3469057582 ps
CPU time 9.39 seconds
Started Jun 26 04:54:49 PM PDT 24
Finished Jun 26 04:55:00 PM PDT 24
Peak memory 201484 kb
Host smart-cd3bc963-7c2a-4fc1-a679-8e28e8b1579c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252841965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_edge_detect.3252841965
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.4230021275
Short name T506
Test name
Test status
Simulation time 2615488108 ps
CPU time 3.87 seconds
Started Jun 26 04:54:37 PM PDT 24
Finished Jun 26 04:54:44 PM PDT 24
Peak memory 201516 kb
Host smart-3e325c33-6b0a-4f48-978d-5775d8fa9a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230021275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.4230021275
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.1631309636
Short name T656
Test name
Test status
Simulation time 2561545174 ps
CPU time 0.99 seconds
Started Jun 26 04:54:46 PM PDT 24
Finished Jun 26 04:54:49 PM PDT 24
Peak memory 201536 kb
Host smart-50b370c2-4c1a-4e49-a458-2a151936de91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631309636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.1631309636
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.318759602
Short name T748
Test name
Test status
Simulation time 2231938953 ps
CPU time 6.19 seconds
Started Jun 26 04:54:43 PM PDT 24
Finished Jun 26 04:54:51 PM PDT 24
Peak memory 201420 kb
Host smart-1a1b8935-64dc-4adb-a65c-9ac90425033d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318759602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.318759602
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.1269823826
Short name T205
Test name
Test status
Simulation time 2523701251 ps
CPU time 2.36 seconds
Started Jun 26 04:54:46 PM PDT 24
Finished Jun 26 04:54:50 PM PDT 24
Peak memory 201528 kb
Host smart-07d0cd2f-b3f0-4eb8-87f9-b46171f99051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269823826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.1269823826
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.1209299839
Short name T132
Test name
Test status
Simulation time 2132614656 ps
CPU time 1.83 seconds
Started Jun 26 04:54:33 PM PDT 24
Finished Jun 26 04:54:38 PM PDT 24
Peak memory 201408 kb
Host smart-d78eaf6a-7eee-4d77-a700-fd2164511d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209299839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.1209299839
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.846602828
Short name T313
Test name
Test status
Simulation time 7568678248 ps
CPU time 3.88 seconds
Started Jun 26 04:54:56 PM PDT 24
Finished Jun 26 04:55:02 PM PDT 24
Peak memory 201532 kb
Host smart-e564745f-ace7-4ba0-9bbd-49138b0e79b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846602828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_st
ress_all.846602828
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.1320664935
Short name T329
Test name
Test status
Simulation time 17781670046 ps
CPU time 24.12 seconds
Started Jun 26 04:54:52 PM PDT 24
Finished Jun 26 04:55:18 PM PDT 24
Peak memory 218160 kb
Host smart-63f900e3-cad5-42ff-8960-4b4298a1032e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320664935 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.1320664935
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.3762664104
Short name T401
Test name
Test status
Simulation time 513598120125 ps
CPU time 145.77 seconds
Started Jun 26 04:54:46 PM PDT 24
Finished Jun 26 04:57:14 PM PDT 24
Peak memory 201584 kb
Host smart-3b21fda2-12e9-491c-8145-805b3159adf6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762664104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.3762664104
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.1370205863
Short name T216
Test name
Test status
Simulation time 2037557792 ps
CPU time 2.11 seconds
Started Jun 26 04:53:43 PM PDT 24
Finished Jun 26 04:53:49 PM PDT 24
Peak memory 201508 kb
Host smart-63b8c34b-cfbd-4d46-a0fd-3654f4d6daef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370205863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.1370205863
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.843508508
Short name T734
Test name
Test status
Simulation time 3580193427 ps
CPU time 9.39 seconds
Started Jun 26 04:53:43 PM PDT 24
Finished Jun 26 04:53:56 PM PDT 24
Peak memory 201480 kb
Host smart-bfdee4af-793d-479a-afbf-2eedb7405c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843508508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.843508508
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.1342725107
Short name T678
Test name
Test status
Simulation time 45700255561 ps
CPU time 27.84 seconds
Started Jun 26 04:53:46 PM PDT 24
Finished Jun 26 04:54:18 PM PDT 24
Peak memory 201744 kb
Host smart-c288afce-26bd-45bb-9316-0a4f3dfb2658
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342725107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_combo_detect.1342725107
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.2844154941
Short name T567
Test name
Test status
Simulation time 2456734556 ps
CPU time 2.18 seconds
Started Jun 26 04:53:55 PM PDT 24
Finished Jun 26 04:54:00 PM PDT 24
Peak memory 201432 kb
Host smart-2530523b-c378-4897-bf3c-0bc4adbfbcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844154941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.2844154941
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3686114586
Short name T15
Test name
Test status
Simulation time 2365951095 ps
CPU time 2.15 seconds
Started Jun 26 04:53:44 PM PDT 24
Finished Jun 26 04:53:51 PM PDT 24
Peak memory 201468 kb
Host smart-23eebfd7-1b4e-49a7-a0cd-a5b5715b5c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686114586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3686114586
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.1043894324
Short name T552
Test name
Test status
Simulation time 2667507440 ps
CPU time 7.36 seconds
Started Jun 26 04:53:46 PM PDT 24
Finished Jun 26 04:53:57 PM PDT 24
Peak memory 201460 kb
Host smart-63d5bd1c-0b84-454d-9a2c-d6da9f5be638
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043894324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ec_pwr_on_rst.1043894324
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.689753450
Short name T162
Test name
Test status
Simulation time 3588359669 ps
CPU time 2.78 seconds
Started Jun 26 04:53:41 PM PDT 24
Finished Jun 26 04:53:53 PM PDT 24
Peak memory 201524 kb
Host smart-771fcdbe-b07e-48bd-89d5-8ac906252650
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689753450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_edge_detect.689753450
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.967659650
Short name T243
Test name
Test status
Simulation time 2613065469 ps
CPU time 7.49 seconds
Started Jun 26 04:53:51 PM PDT 24
Finished Jun 26 04:54:01 PM PDT 24
Peak memory 201436 kb
Host smart-940fc9e2-9752-4e34-94ca-58d28408bf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967659650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.967659650
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.198445074
Short name T25
Test name
Test status
Simulation time 2482456210 ps
CPU time 1.62 seconds
Started Jun 26 04:53:46 PM PDT 24
Finished Jun 26 04:53:52 PM PDT 24
Peak memory 201456 kb
Host smart-17909372-9f6a-48df-a4b2-7c8a43112058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198445074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.198445074
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.354615544
Short name T182
Test name
Test status
Simulation time 2167014901 ps
CPU time 2.09 seconds
Started Jun 26 04:53:44 PM PDT 24
Finished Jun 26 04:53:51 PM PDT 24
Peak memory 201476 kb
Host smart-6a8c2308-bfff-4bea-b053-ee59f186e3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354615544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.354615544
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.3553515130
Short name T615
Test name
Test status
Simulation time 2528654842 ps
CPU time 2.98 seconds
Started Jun 26 04:53:55 PM PDT 24
Finished Jun 26 04:54:00 PM PDT 24
Peak memory 201484 kb
Host smart-20eeae2b-6b1c-4a58-8085-3c0538f21f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553515130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.3553515130
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.1688762471
Short name T311
Test name
Test status
Simulation time 42107639986 ps
CPU time 27.49 seconds
Started Jun 26 04:53:58 PM PDT 24
Finished Jun 26 04:54:29 PM PDT 24
Peak memory 221360 kb
Host smart-2b0b4c6c-22cc-459e-bd29-6de01957c9c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688762471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.1688762471
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.2438633179
Short name T607
Test name
Test status
Simulation time 2129847226 ps
CPU time 1.97 seconds
Started Jun 26 04:53:50 PM PDT 24
Finished Jun 26 04:53:56 PM PDT 24
Peak memory 201404 kb
Host smart-db27f804-06e4-4e7d-9e93-b0b4f8717876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438633179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.2438633179
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.2526018541
Short name T258
Test name
Test status
Simulation time 83412441956 ps
CPU time 49.52 seconds
Started Jun 26 04:53:43 PM PDT 24
Finished Jun 26 04:54:36 PM PDT 24
Peak memory 201880 kb
Host smart-46a17d5a-d8f5-4c16-ac62-b9896080daf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526018541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_st
ress_all.2526018541
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.3001024026
Short name T154
Test name
Test status
Simulation time 27832030951 ps
CPU time 70.72 seconds
Started Jun 26 04:53:47 PM PDT 24
Finished Jun 26 04:55:02 PM PDT 24
Peak memory 210100 kb
Host smart-02078b0b-4834-4fb6-b077-fc67d9b3492d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001024026 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.3001024026
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.3385357283
Short name T423
Test name
Test status
Simulation time 4988372640 ps
CPU time 3.63 seconds
Started Jun 26 04:53:55 PM PDT 24
Finished Jun 26 04:54:02 PM PDT 24
Peak memory 201392 kb
Host smart-60658a61-bb8e-4b70-a5e0-e509e7bdd4a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385357283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.3385357283
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.3543738306
Short name T566
Test name
Test status
Simulation time 2014537095 ps
CPU time 5.81 seconds
Started Jun 26 04:54:54 PM PDT 24
Finished Jun 26 04:55:02 PM PDT 24
Peak memory 201416 kb
Host smart-0cb4a3b3-c00c-4e9e-9848-e846a09c82f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543738306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_te
st.3543738306
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.2079874984
Short name T484
Test name
Test status
Simulation time 3748118742 ps
CPU time 6.44 seconds
Started Jun 26 04:54:47 PM PDT 24
Finished Jun 26 04:54:56 PM PDT 24
Peak memory 201492 kb
Host smart-35139fb8-4a0a-479e-8e36-d212680f5207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079874984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.2
079874984
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.781969134
Short name T382
Test name
Test status
Simulation time 156123550132 ps
CPU time 302.26 seconds
Started Jun 26 04:54:46 PM PDT 24
Finished Jun 26 04:59:50 PM PDT 24
Peak memory 201764 kb
Host smart-e7d50e1f-2ed6-4d21-b0c6-504a868abcbb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781969134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_combo_detect.781969134
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.1120439922
Short name T248
Test name
Test status
Simulation time 34855772744 ps
CPU time 21.81 seconds
Started Jun 26 04:54:48 PM PDT 24
Finished Jun 26 04:55:12 PM PDT 24
Peak memory 201784 kb
Host smart-2303ad51-4011-4539-8324-7c5cb5095f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120439922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.1120439922
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.4075829543
Short name T752
Test name
Test status
Simulation time 3103975787 ps
CPU time 2.9 seconds
Started Jun 26 04:54:47 PM PDT 24
Finished Jun 26 04:54:52 PM PDT 24
Peak memory 201492 kb
Host smart-fe049639-6f73-4ea0-99f6-a5dc5120b7e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075829543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ec_pwr_on_rst.4075829543
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1681290603
Short name T554
Test name
Test status
Simulation time 2611868190 ps
CPU time 7.03 seconds
Started Jun 26 04:54:52 PM PDT 24
Finished Jun 26 04:55:01 PM PDT 24
Peak memory 201444 kb
Host smart-cb82c564-45c6-4e28-bf99-ffd28f337df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681290603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.1681290603
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.3374643712
Short name T780
Test name
Test status
Simulation time 2463586577 ps
CPU time 6.27 seconds
Started Jun 26 04:54:47 PM PDT 24
Finished Jun 26 04:54:56 PM PDT 24
Peak memory 201428 kb
Host smart-c322fd34-fe67-4350-a400-37884c635cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374643712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.3374643712
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.3076189372
Short name T592
Test name
Test status
Simulation time 2087684165 ps
CPU time 1.17 seconds
Started Jun 26 04:55:01 PM PDT 24
Finished Jun 26 04:55:06 PM PDT 24
Peak memory 201360 kb
Host smart-f378aa11-782a-4310-8a5b-c90ef1a344f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076189372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.3076189372
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.3319003632
Short name T742
Test name
Test status
Simulation time 2530559601 ps
CPU time 2.27 seconds
Started Jun 26 04:54:53 PM PDT 24
Finished Jun 26 04:54:57 PM PDT 24
Peak memory 201512 kb
Host smart-c4993710-c6f4-49e1-8722-188f132c757f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319003632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.3319003632
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.1694407143
Short name T457
Test name
Test status
Simulation time 2118010630 ps
CPU time 3.27 seconds
Started Jun 26 04:54:46 PM PDT 24
Finished Jun 26 04:54:50 PM PDT 24
Peak memory 201444 kb
Host smart-51d853d9-438a-4077-8b28-977651cab366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694407143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.1694407143
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.289573129
Short name T272
Test name
Test status
Simulation time 7233595800 ps
CPU time 13.38 seconds
Started Jun 26 04:54:54 PM PDT 24
Finished Jun 26 04:55:10 PM PDT 24
Peak memory 201472 kb
Host smart-dba3c71d-f489-47e7-aac6-450fcc71abdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289573129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_st
ress_all.289573129
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1226821041
Short name T396
Test name
Test status
Simulation time 21315871853 ps
CPU time 58.4 seconds
Started Jun 26 04:54:46 PM PDT 24
Finished Jun 26 04:55:46 PM PDT 24
Peak memory 210404 kb
Host smart-680ec888-acd9-4f6f-b329-b515c8b45cdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226821041 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.1226821041
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.3028207909
Short name T133
Test name
Test status
Simulation time 5610393687 ps
CPU time 2.93 seconds
Started Jun 26 04:54:59 PM PDT 24
Finished Jun 26 04:55:04 PM PDT 24
Peak memory 201552 kb
Host smart-811a6e2d-5934-4ff7-baff-71dc6d6a9995
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028207909 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ultra_low_pwr.3028207909
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.1276354737
Short name T403
Test name
Test status
Simulation time 2053363363 ps
CPU time 1.67 seconds
Started Jun 26 04:54:46 PM PDT 24
Finished Jun 26 04:54:50 PM PDT 24
Peak memory 201512 kb
Host smart-684be6a7-df14-4d4c-a0cf-b2d52e20f32c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276354737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_te
st.1276354737
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.540119283
Short name T48
Test name
Test status
Simulation time 3478268570 ps
CPU time 5.1 seconds
Started Jun 26 04:54:47 PM PDT 24
Finished Jun 26 04:54:54 PM PDT 24
Peak memory 201540 kb
Host smart-393ac999-ece1-47e0-825b-7519f905167f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540119283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.540119283
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.3310084268
Short name T199
Test name
Test status
Simulation time 193300844280 ps
CPU time 127.73 seconds
Started Jun 26 04:54:57 PM PDT 24
Finished Jun 26 04:57:07 PM PDT 24
Peak memory 201676 kb
Host smart-afbae85c-7457-4c33-95df-64d9aab5887d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310084268 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_combo_detect.3310084268
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.2998240779
Short name T373
Test name
Test status
Simulation time 95181440332 ps
CPU time 109.61 seconds
Started Jun 26 04:54:51 PM PDT 24
Finished Jun 26 04:56:43 PM PDT 24
Peak memory 201824 kb
Host smart-495c0e7c-9d03-41ed-91aa-49547074dd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998240779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_w
ith_pre_cond.2998240779
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.2037236852
Short name T588
Test name
Test status
Simulation time 2906046234 ps
CPU time 2.51 seconds
Started Jun 26 04:54:54 PM PDT 24
Finished Jun 26 04:54:59 PM PDT 24
Peak memory 201500 kb
Host smart-b148b49d-13ca-48af-a7f9-7bc8171f04da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037236852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ec_pwr_on_rst.2037236852
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.2961083136
Short name T1
Test name
Test status
Simulation time 2730395718 ps
CPU time 7.29 seconds
Started Jun 26 04:54:46 PM PDT 24
Finished Jun 26 04:54:55 PM PDT 24
Peak memory 201520 kb
Host smart-0a1d6849-9e45-4e7e-b5d7-62dc4d2c2733
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961083136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_edge_detect.2961083136
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.888139984
Short name T497
Test name
Test status
Simulation time 2684292707 ps
CPU time 1.35 seconds
Started Jun 26 04:54:57 PM PDT 24
Finished Jun 26 04:55:01 PM PDT 24
Peak memory 201432 kb
Host smart-11c988ad-db85-4f2a-8463-ac3c29d62576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888139984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.888139984
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.1916516665
Short name T322
Test name
Test status
Simulation time 2475835339 ps
CPU time 2.14 seconds
Started Jun 26 04:54:53 PM PDT 24
Finished Jun 26 04:54:56 PM PDT 24
Peak memory 201432 kb
Host smart-9090489b-dd51-44ff-a100-a23c1c9f0318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916516665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.1916516665
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.1987705708
Short name T712
Test name
Test status
Simulation time 2118016110 ps
CPU time 1.64 seconds
Started Jun 26 04:54:56 PM PDT 24
Finished Jun 26 04:55:00 PM PDT 24
Peak memory 201444 kb
Host smart-293b4dce-4005-424f-a83d-ba19e45efce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987705708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.1987705708
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.686641626
Short name T26
Test name
Test status
Simulation time 2537990654 ps
CPU time 1.8 seconds
Started Jun 26 04:54:40 PM PDT 24
Finished Jun 26 04:54:44 PM PDT 24
Peak memory 201480 kb
Host smart-3f2eeecb-081e-4077-a69f-25ea357730f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686641626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.686641626
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.956990603
Short name T529
Test name
Test status
Simulation time 2112969479 ps
CPU time 6.13 seconds
Started Jun 26 04:54:53 PM PDT 24
Finished Jun 26 04:55:01 PM PDT 24
Peak memory 201384 kb
Host smart-979da349-74dd-4588-a077-8048dafd26fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956990603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.956990603
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.43355450
Short name T785
Test name
Test status
Simulation time 13119025928 ps
CPU time 9.61 seconds
Started Jun 26 04:54:55 PM PDT 24
Finished Jun 26 04:55:07 PM PDT 24
Peak memory 201552 kb
Host smart-5cab0865-43be-4e67-b587-c1049f015970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43355450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_str
ess_all.43355450
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.4033451547
Short name T65
Test name
Test status
Simulation time 56484160603 ps
CPU time 33.3 seconds
Started Jun 26 04:54:40 PM PDT 24
Finished Jun 26 04:55:16 PM PDT 24
Peak memory 210236 kb
Host smart-82462a2e-59ce-47c2-a3e1-9a64f29a61f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033451547 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.4033451547
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.3825124048
Short name T128
Test name
Test status
Simulation time 5330790106 ps
CPU time 4.13 seconds
Started Jun 26 04:54:58 PM PDT 24
Finished Jun 26 04:55:04 PM PDT 24
Peak memory 201520 kb
Host smart-7abfb924-0c25-4773-93e9-9b6bb8ecbc82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825124048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.3825124048
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.143787651
Short name T453
Test name
Test status
Simulation time 2013634494 ps
CPU time 5.93 seconds
Started Jun 26 04:54:48 PM PDT 24
Finished Jun 26 04:54:56 PM PDT 24
Peak memory 201416 kb
Host smart-dc9cf554-8b94-4524-9b0b-5afefac5518e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143787651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_tes
t.143787651
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.422848301
Short name T103
Test name
Test status
Simulation time 3650099172 ps
CPU time 10.37 seconds
Started Jun 26 04:54:50 PM PDT 24
Finished Jun 26 04:55:02 PM PDT 24
Peak memory 201576 kb
Host smart-01f3e309-6c87-43c3-a604-2d90b84c3db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422848301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.422848301
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.3672195806
Short name T259
Test name
Test status
Simulation time 95407652486 ps
CPU time 64.64 seconds
Started Jun 26 04:54:56 PM PDT 24
Finished Jun 26 04:56:03 PM PDT 24
Peak memory 201684 kb
Host smart-3d8851d3-f08d-4124-b406-ca3e7c5338f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672195806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_combo_detect.3672195806
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.722877094
Short name T95
Test name
Test status
Simulation time 22097697736 ps
CPU time 24.61 seconds
Started Jun 26 04:54:53 PM PDT 24
Finished Jun 26 04:55:19 PM PDT 24
Peak memory 201748 kb
Host smart-9441e09d-8ff1-486d-aabe-f1859999cc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722877094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_wi
th_pre_cond.722877094
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.373444594
Short name T774
Test name
Test status
Simulation time 4465636119 ps
CPU time 6.77 seconds
Started Jun 26 04:54:57 PM PDT 24
Finished Jun 26 04:55:06 PM PDT 24
Peak memory 201560 kb
Host smart-a3981f15-271f-423b-9335-e46ca7cdcc3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373444594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_ec_pwr_on_rst.373444594
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.1966422188
Short name T176
Test name
Test status
Simulation time 3865884263 ps
CPU time 8.21 seconds
Started Jun 26 04:54:46 PM PDT 24
Finished Jun 26 04:54:55 PM PDT 24
Peak memory 201492 kb
Host smart-070de562-246a-47ff-8681-b2bde67e17e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966422188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.1966422188
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3795948934
Short name T510
Test name
Test status
Simulation time 2613472933 ps
CPU time 7.51 seconds
Started Jun 26 04:54:46 PM PDT 24
Finished Jun 26 04:54:55 PM PDT 24
Peak memory 201512 kb
Host smart-31162bff-5628-4c70-b493-aa64730bf6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795948934 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.3795948934
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.1842607136
Short name T62
Test name
Test status
Simulation time 2466817139 ps
CPU time 2.17 seconds
Started Jun 26 04:55:01 PM PDT 24
Finished Jun 26 04:55:08 PM PDT 24
Peak memory 201428 kb
Host smart-be748595-dd38-4ace-a0d9-be273cfccdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842607136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.1842607136
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.963817678
Short name T500
Test name
Test status
Simulation time 2106329956 ps
CPU time 5.85 seconds
Started Jun 26 04:54:53 PM PDT 24
Finished Jun 26 04:55:00 PM PDT 24
Peak memory 201412 kb
Host smart-fd5d443b-61a2-46b3-8e0b-952dc82a0fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963817678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.963817678
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.3130827712
Short name T172
Test name
Test status
Simulation time 2515035676 ps
CPU time 7.02 seconds
Started Jun 26 04:54:48 PM PDT 24
Finished Jun 26 04:54:57 PM PDT 24
Peak memory 201424 kb
Host smart-e92a5b22-97f5-4b30-951c-038451d90d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130827712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.3130827712
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.3700102608
Short name T674
Test name
Test status
Simulation time 2136904026 ps
CPU time 1.96 seconds
Started Jun 26 04:54:48 PM PDT 24
Finished Jun 26 04:54:52 PM PDT 24
Peak memory 201364 kb
Host smart-deee9a40-071e-4cfa-8ff5-84131d48c4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700102608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.3700102608
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.3760302677
Short name T791
Test name
Test status
Simulation time 12243697379 ps
CPU time 14.91 seconds
Started Jun 26 04:55:06 PM PDT 24
Finished Jun 26 04:55:26 PM PDT 24
Peak memory 201460 kb
Host smart-6379f3e3-f86c-4c79-a717-ce7045dd0478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760302677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_s
tress_all.3760302677
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.187202731
Short name T397
Test name
Test status
Simulation time 88177847128 ps
CPU time 46.1 seconds
Started Jun 26 04:54:52 PM PDT 24
Finished Jun 26 04:55:39 PM PDT 24
Peak memory 210116 kb
Host smart-8cd4d20b-693b-4dd4-907c-13bccd3e1bb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187202731 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.187202731
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.2399581817
Short name T60
Test name
Test status
Simulation time 3324867059 ps
CPU time 1.89 seconds
Started Jun 26 04:54:58 PM PDT 24
Finished Jun 26 04:55:03 PM PDT 24
Peak memory 201460 kb
Host smart-4614a181-5f19-41ec-8558-ddd974dfb6ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399581817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ultra_low_pwr.2399581817
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.3997297275
Short name T17
Test name
Test status
Simulation time 2056104695 ps
CPU time 1.16 seconds
Started Jun 26 04:54:57 PM PDT 24
Finished Jun 26 04:55:00 PM PDT 24
Peak memory 201496 kb
Host smart-5e65db14-d903-419f-89d7-b0e00f81cd82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997297275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.3997297275
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.978854747
Short name T124
Test name
Test status
Simulation time 3174355404 ps
CPU time 8.28 seconds
Started Jun 26 04:55:04 PM PDT 24
Finished Jun 26 04:55:17 PM PDT 24
Peak memory 201552 kb
Host smart-3c388ed0-59c2-474b-84d8-ec00945e1c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978854747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.978854747
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.4194670216
Short name T108
Test name
Test status
Simulation time 79829961916 ps
CPU time 108.26 seconds
Started Jun 26 04:54:55 PM PDT 24
Finished Jun 26 04:56:46 PM PDT 24
Peak memory 201728 kb
Host smart-e779b23a-3cfb-4f59-8629-91ea2b1b432b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194670216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.4194670216
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.1949917556
Short name T357
Test name
Test status
Simulation time 76039227169 ps
CPU time 97.96 seconds
Started Jun 26 04:55:21 PM PDT 24
Finished Jun 26 04:57:02 PM PDT 24
Peak memory 202028 kb
Host smart-4c1fc0f6-461c-4566-9e9c-fc91b6fcd8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949917556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.1949917556
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.2387581832
Short name T197
Test name
Test status
Simulation time 4878150310 ps
CPU time 13.69 seconds
Started Jun 26 04:55:00 PM PDT 24
Finished Jun 26 04:55:17 PM PDT 24
Peak memory 201456 kb
Host smart-f20de21e-1c18-41b7-9ec2-23ebbfa5b27c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387581832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.2387581832
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.3742241853
Short name T800
Test name
Test status
Simulation time 4156717088 ps
CPU time 3.53 seconds
Started Jun 26 04:55:01 PM PDT 24
Finished Jun 26 04:55:07 PM PDT 24
Peak memory 201440 kb
Host smart-28179ac7-add2-4937-ad6d-d934963ca033
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742241853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_edge_detect.3742241853
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.2681242671
Short name T550
Test name
Test status
Simulation time 2628819541 ps
CPU time 2.3 seconds
Started Jun 26 04:54:53 PM PDT 24
Finished Jun 26 04:54:57 PM PDT 24
Peak memory 201472 kb
Host smart-15fb12ba-86a5-48d7-9b25-0696ce059e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681242671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.2681242671
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.2075736469
Short name T200
Test name
Test status
Simulation time 2475077790 ps
CPU time 4.14 seconds
Started Jun 26 04:54:59 PM PDT 24
Finished Jun 26 04:55:07 PM PDT 24
Peak memory 201512 kb
Host smart-0b79310f-a30b-49b2-b966-f80ca3d041ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075736469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.2075736469
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.3032288519
Short name T686
Test name
Test status
Simulation time 2183950485 ps
CPU time 6.17 seconds
Started Jun 26 04:54:53 PM PDT 24
Finished Jun 26 04:55:01 PM PDT 24
Peak memory 201520 kb
Host smart-fcbb636e-63b0-414b-8fde-9dca741ecdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032288519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.3032288519
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.1481051736
Short name T327
Test name
Test status
Simulation time 2520857152 ps
CPU time 2.33 seconds
Started Jun 26 04:55:01 PM PDT 24
Finished Jun 26 04:55:06 PM PDT 24
Peak memory 201492 kb
Host smart-3fa7017e-e085-49b3-baac-17cddc6f7141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481051736 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.1481051736
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.2760246014
Short name T165
Test name
Test status
Simulation time 2112676583 ps
CPU time 6.12 seconds
Started Jun 26 04:54:49 PM PDT 24
Finished Jun 26 04:54:57 PM PDT 24
Peak memory 201352 kb
Host smart-447c1dea-df5d-4e16-ac05-26b639a9b653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760246014 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.2760246014
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.413298200
Short name T759
Test name
Test status
Simulation time 16987115518 ps
CPU time 43.02 seconds
Started Jun 26 04:54:49 PM PDT 24
Finished Jun 26 04:55:34 PM PDT 24
Peak memory 201608 kb
Host smart-507fd567-875e-477a-b6d8-836f94addca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413298200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_st
ress_all.413298200
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.231061676
Short name T138
Test name
Test status
Simulation time 8393737998 ps
CPU time 4.2 seconds
Started Jun 26 04:54:55 PM PDT 24
Finished Jun 26 04:55:02 PM PDT 24
Peak memory 201556 kb
Host smart-a574758b-52d5-4536-9556-4226f2e162ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231061676 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_ultra_low_pwr.231061676
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.92573633
Short name T511
Test name
Test status
Simulation time 2026484995 ps
CPU time 1.89 seconds
Started Jun 26 04:54:55 PM PDT 24
Finished Jun 26 04:54:59 PM PDT 24
Peak memory 201416 kb
Host smart-94ec6dfc-fe47-4580-b46e-baeb2fc57dcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92573633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_test
.92573633
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.24053170
Short name T183
Test name
Test status
Simulation time 3395038142 ps
CPU time 4.29 seconds
Started Jun 26 04:54:55 PM PDT 24
Finished Jun 26 04:55:01 PM PDT 24
Peak memory 201592 kb
Host smart-22b7c206-3e4b-4ba1-a8b0-818dbfa8163d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24053170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.24053170
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.1264039646
Short name T101
Test name
Test status
Simulation time 152161762732 ps
CPU time 386.95 seconds
Started Jun 26 04:54:57 PM PDT 24
Finished Jun 26 05:01:26 PM PDT 24
Peak memory 201676 kb
Host smart-eaa42878-782c-4f2f-aaf5-bc1763f8b86d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264039646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_combo_detect.1264039646
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.1117526455
Short name T802
Test name
Test status
Simulation time 45227121618 ps
CPU time 12.63 seconds
Started Jun 26 04:54:54 PM PDT 24
Finished Jun 26 04:55:09 PM PDT 24
Peak memory 201796 kb
Host smart-be40973b-fedc-4c40-b99b-4977cf029467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117526455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_w
ith_pre_cond.1117526455
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2738091626
Short name T424
Test name
Test status
Simulation time 3899489505 ps
CPU time 4.39 seconds
Started Jun 26 04:55:05 PM PDT 24
Finished Jun 26 04:55:15 PM PDT 24
Peak memory 201392 kb
Host smart-80afdc23-fbce-4bdd-b247-bbd38c70c45d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738091626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ec_pwr_on_rst.2738091626
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.2229939133
Short name T643
Test name
Test status
Simulation time 5664627905 ps
CPU time 1.13 seconds
Started Jun 26 04:54:57 PM PDT 24
Finished Jun 26 04:55:00 PM PDT 24
Peak memory 201560 kb
Host smart-2d83b589-b964-48a1-995f-37ee62859920
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229939133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.2229939133
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.101175328
Short name T422
Test name
Test status
Simulation time 2609838865 ps
CPU time 7.24 seconds
Started Jun 26 04:55:01 PM PDT 24
Finished Jun 26 04:55:11 PM PDT 24
Peak memory 201428 kb
Host smart-0debe52b-f14c-469a-976c-9769569f79f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101175328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.101175328
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.2747202159
Short name T641
Test name
Test status
Simulation time 2464063243 ps
CPU time 3.43 seconds
Started Jun 26 04:54:55 PM PDT 24
Finished Jun 26 04:55:00 PM PDT 24
Peak memory 201428 kb
Host smart-3bd80ca7-393b-45f1-916b-8d0904d9e2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747202159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.2747202159
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.1930103473
Short name T620
Test name
Test status
Simulation time 2204786571 ps
CPU time 6.7 seconds
Started Jun 26 04:54:56 PM PDT 24
Finished Jun 26 04:55:05 PM PDT 24
Peak memory 201420 kb
Host smart-d0a7898e-0c49-4a88-a9dc-ddff0acb4ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930103473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.1930103473
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.1775884062
Short name T273
Test name
Test status
Simulation time 2512783551 ps
CPU time 6.67 seconds
Started Jun 26 04:54:51 PM PDT 24
Finished Jun 26 04:55:00 PM PDT 24
Peak memory 201424 kb
Host smart-9a94c6d3-833e-4e82-830b-c54d03124126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775884062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.1775884062
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.2620121082
Short name T210
Test name
Test status
Simulation time 2111317452 ps
CPU time 6.21 seconds
Started Jun 26 04:54:57 PM PDT 24
Finished Jun 26 04:55:06 PM PDT 24
Peak memory 201340 kb
Host smart-03a00305-8639-42b9-852e-be71c6932bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620121082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.2620121082
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.2494079243
Short name T531
Test name
Test status
Simulation time 14611411138 ps
CPU time 10.26 seconds
Started Jun 26 04:55:01 PM PDT 24
Finished Jun 26 04:55:15 PM PDT 24
Peak memory 201548 kb
Host smart-07b02ce9-05c9-465e-9606-2452dafb1073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494079243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s
tress_all.2494079243
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.3366146697
Short name T226
Test name
Test status
Simulation time 47359520830 ps
CPU time 111 seconds
Started Jun 26 04:55:11 PM PDT 24
Finished Jun 26 04:57:07 PM PDT 24
Peak memory 210448 kb
Host smart-524c4d74-b793-4489-ae0c-91b984db4686
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366146697 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.3366146697
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2363939309
Short name T553
Test name
Test status
Simulation time 6988720189 ps
CPU time 4.08 seconds
Started Jun 26 04:55:00 PM PDT 24
Finished Jun 26 04:55:07 PM PDT 24
Peak memory 201492 kb
Host smart-7adb5650-e093-4ece-96f9-dc107f11834a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363939309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ultra_low_pwr.2363939309
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.4274620389
Short name T595
Test name
Test status
Simulation time 2013337152 ps
CPU time 5.4 seconds
Started Jun 26 04:55:03 PM PDT 24
Finished Jun 26 04:55:12 PM PDT 24
Peak memory 201416 kb
Host smart-46f4dc84-ff12-4ffa-b18c-0813637d6d98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274620389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te
st.4274620389
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.2067003001
Short name T670
Test name
Test status
Simulation time 3999438360 ps
CPU time 11.39 seconds
Started Jun 26 04:54:56 PM PDT 24
Finished Jun 26 04:55:10 PM PDT 24
Peak memory 201492 kb
Host smart-7c808689-9ec8-4817-a350-78350518f3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067003001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.2
067003001
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.646977268
Short name T33
Test name
Test status
Simulation time 88407822348 ps
CPU time 32.61 seconds
Started Jun 26 04:54:58 PM PDT 24
Finished Jun 26 04:55:32 PM PDT 24
Peak memory 201672 kb
Host smart-50396678-6222-4b0b-8e05-95d22f908719
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646977268 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_combo_detect.646977268
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1285379077
Short name T374
Test name
Test status
Simulation time 52126783812 ps
CPU time 34.33 seconds
Started Jun 26 04:54:55 PM PDT 24
Finished Jun 26 04:55:31 PM PDT 24
Peak memory 201760 kb
Host smart-be4440a7-d99d-478b-be11-abb2df5b26b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285379077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_w
ith_pre_cond.1285379077
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.550377943
Short name T739
Test name
Test status
Simulation time 3464176354 ps
CPU time 8.82 seconds
Started Jun 26 04:55:00 PM PDT 24
Finished Jun 26 04:55:12 PM PDT 24
Peak memory 201464 kb
Host smart-c4806c14-c37d-4a16-9389-0103b60dc834
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550377943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_ec_pwr_on_rst.550377943
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.180391744
Short name T195
Test name
Test status
Simulation time 3224666350 ps
CPU time 9.27 seconds
Started Jun 26 04:54:57 PM PDT 24
Finished Jun 26 04:55:08 PM PDT 24
Peak memory 201440 kb
Host smart-e176eed3-2f3e-4dbd-a943-4ddd18938e48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180391744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctr
l_edge_detect.180391744
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.3445169686
Short name T421
Test name
Test status
Simulation time 2620001459 ps
CPU time 4.27 seconds
Started Jun 26 04:54:57 PM PDT 24
Finished Jun 26 04:55:03 PM PDT 24
Peak memory 201508 kb
Host smart-9f2ac38b-f94d-4d39-9eb7-c57f4559d5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445169686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.3445169686
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.2746284645
Short name T675
Test name
Test status
Simulation time 2450296952 ps
CPU time 7.3 seconds
Started Jun 26 04:55:06 PM PDT 24
Finished Jun 26 04:55:18 PM PDT 24
Peak memory 201420 kb
Host smart-4f56a26f-721e-4294-98c5-5e31477d1d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746284645 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.2746284645
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.414680052
Short name T459
Test name
Test status
Simulation time 2175189753 ps
CPU time 2.02 seconds
Started Jun 26 04:55:02 PM PDT 24
Finished Jun 26 04:55:07 PM PDT 24
Peak memory 201496 kb
Host smart-38a8bcd4-7506-43cc-b74a-14a571e0d3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414680052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.414680052
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.326754912
Short name T526
Test name
Test status
Simulation time 2514419992 ps
CPU time 6.65 seconds
Started Jun 26 04:54:59 PM PDT 24
Finished Jun 26 04:55:08 PM PDT 24
Peak memory 201508 kb
Host smart-da2363da-7739-408a-8729-0d38148de772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326754912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.326754912
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.3561632897
Short name T602
Test name
Test status
Simulation time 2112173844 ps
CPU time 3.25 seconds
Started Jun 26 04:54:59 PM PDT 24
Finished Jun 26 04:55:05 PM PDT 24
Peak memory 201340 kb
Host smart-5ee940b7-5398-447e-b96a-e7ca06910704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561632897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.3561632897
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.708072410
Short name T454
Test name
Test status
Simulation time 6863296485 ps
CPU time 4.92 seconds
Started Jun 26 04:54:56 PM PDT 24
Finished Jun 26 04:55:03 PM PDT 24
Peak memory 201464 kb
Host smart-0e0fde7e-c619-4a32-8b7f-43595f2dfc59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708072410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_st
ress_all.708072410
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.305281155
Short name T59
Test name
Test status
Simulation time 1006634590931 ps
CPU time 160.08 seconds
Started Jun 26 04:55:01 PM PDT 24
Finished Jun 26 04:57:45 PM PDT 24
Peak memory 201532 kb
Host smart-03e925b6-872b-42ed-92b7-ee9c23ed7e25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305281155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_ultra_low_pwr.305281155
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.932158056
Short name T440
Test name
Test status
Simulation time 2026449980 ps
CPU time 2.33 seconds
Started Jun 26 04:55:05 PM PDT 24
Finished Jun 26 04:55:12 PM PDT 24
Peak memory 201420 kb
Host smart-8a0f56bc-c9ad-4d8a-b536-3d87b63fb674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932158056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_tes
t.932158056
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3491561112
Short name T541
Test name
Test status
Simulation time 34190231271 ps
CPU time 91.07 seconds
Started Jun 26 04:54:59 PM PDT 24
Finished Jun 26 04:56:33 PM PDT 24
Peak memory 201688 kb
Host smart-f5b51a6b-a2e8-4f58-a497-0442d89c9cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491561112 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.3
491561112
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.2648954914
Short name T257
Test name
Test status
Simulation time 34141856047 ps
CPU time 20.66 seconds
Started Jun 26 04:55:07 PM PDT 24
Finished Jun 26 04:55:32 PM PDT 24
Peak memory 201820 kb
Host smart-426944a2-870f-4c4e-b312-4429009ad757
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648954914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_combo_detect.2648954914
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.1685083579
Short name T737
Test name
Test status
Simulation time 3182568568 ps
CPU time 2.65 seconds
Started Jun 26 04:55:01 PM PDT 24
Finished Jun 26 04:55:08 PM PDT 24
Peak memory 201392 kb
Host smart-82bcfe3d-4a7f-4503-951d-f300fc4916a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685083579 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ec_pwr_on_rst.1685083579
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.1162019850
Short name T178
Test name
Test status
Simulation time 4797582147 ps
CPU time 3.29 seconds
Started Jun 26 04:55:04 PM PDT 24
Finished Jun 26 04:55:13 PM PDT 24
Peak memory 201456 kb
Host smart-f39e356f-ab64-4d6a-8379-20cecbcf94d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162019850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.1162019850
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.1894700776
Short name T437
Test name
Test status
Simulation time 2617684312 ps
CPU time 4.06 seconds
Started Jun 26 04:54:51 PM PDT 24
Finished Jun 26 04:54:56 PM PDT 24
Peak memory 201428 kb
Host smart-fbdaae09-707b-48bb-8942-1a6d2750ad43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894700776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.1894700776
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.2054328077
Short name T690
Test name
Test status
Simulation time 2474386888 ps
CPU time 2.41 seconds
Started Jun 26 04:56:25 PM PDT 24
Finished Jun 26 04:56:30 PM PDT 24
Peak memory 201536 kb
Host smart-557d8d01-bdf5-48bd-8578-ae3245d4dd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054328077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.2054328077
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.955469215
Short name T789
Test name
Test status
Simulation time 2250719736 ps
CPU time 2.63 seconds
Started Jun 26 04:54:58 PM PDT 24
Finished Jun 26 04:55:02 PM PDT 24
Peak memory 201416 kb
Host smart-84fafb73-01b5-42b4-aa7a-e1cc3da43e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955469215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.955469215
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.2447069483
Short name T112
Test name
Test status
Simulation time 2566449864 ps
CPU time 1.52 seconds
Started Jun 26 04:54:59 PM PDT 24
Finished Jun 26 04:55:03 PM PDT 24
Peak memory 201532 kb
Host smart-e60e2181-920b-49b3-876f-5d13b12960b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447069483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.2447069483
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.4025380878
Short name T92
Test name
Test status
Simulation time 2112160529 ps
CPU time 6.01 seconds
Started Jun 26 04:55:05 PM PDT 24
Finished Jun 26 04:55:16 PM PDT 24
Peak memory 201448 kb
Host smart-30bff6a0-907e-4727-8853-1b99f08861ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025380878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.4025380878
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.2896240826
Short name T263
Test name
Test status
Simulation time 88525408932 ps
CPU time 213.45 seconds
Started Jun 26 04:55:05 PM PDT 24
Finished Jun 26 04:58:44 PM PDT 24
Peak memory 201856 kb
Host smart-4345b848-43c5-4fc7-925e-0268c7bf920c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896240826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_s
tress_all.2896240826
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.2407646365
Short name T145
Test name
Test status
Simulation time 4213025178 ps
CPU time 1.72 seconds
Started Jun 26 04:55:01 PM PDT 24
Finished Jun 26 04:55:06 PM PDT 24
Peak memory 201492 kb
Host smart-81924feb-d9ac-4ab0-a994-e17ebdcdaa9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407646365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ultra_low_pwr.2407646365
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.1631259015
Short name T725
Test name
Test status
Simulation time 2032566110 ps
CPU time 1.87 seconds
Started Jun 26 04:55:02 PM PDT 24
Finished Jun 26 04:55:08 PM PDT 24
Peak memory 201432 kb
Host smart-d4b2569f-878f-4185-a786-80dd11baed94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631259015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.1631259015
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.1178948100
Short name T52
Test name
Test status
Simulation time 3433339682 ps
CPU time 2.77 seconds
Started Jun 26 04:54:57 PM PDT 24
Finished Jun 26 04:55:02 PM PDT 24
Peak memory 201492 kb
Host smart-3b4d48a0-7a11-47f2-b8af-1a8dc47cd174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178948100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.1
178948100
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.2441229633
Short name T211
Test name
Test status
Simulation time 50310261879 ps
CPU time 17.72 seconds
Started Jun 26 04:55:04 PM PDT 24
Finished Jun 26 04:55:27 PM PDT 24
Peak memory 201740 kb
Host smart-401fd1e2-6a5a-46f0-bb70-992084bdc77f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441229633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_combo_detect.2441229633
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.827867262
Short name T505
Test name
Test status
Simulation time 41214141124 ps
CPU time 20.63 seconds
Started Jun 26 04:55:02 PM PDT 24
Finished Jun 26 04:55:27 PM PDT 24
Peak memory 201764 kb
Host smart-9f5248ef-e294-41eb-bee9-2c9dbf26ec41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827867262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_wi
th_pre_cond.827867262
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.413699372
Short name T801
Test name
Test status
Simulation time 4193481037 ps
CPU time 1.6 seconds
Started Jun 26 04:55:03 PM PDT 24
Finished Jun 26 04:55:10 PM PDT 24
Peak memory 201492 kb
Host smart-32c84a33-8ba3-4b13-b7d8-c3722ce578df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413699372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_ec_pwr_on_rst.413699372
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.516553876
Short name T37
Test name
Test status
Simulation time 3607851666 ps
CPU time 7.69 seconds
Started Jun 26 04:55:04 PM PDT 24
Finished Jun 26 04:55:17 PM PDT 24
Peak memory 201408 kb
Host smart-6cdb88cb-f95e-4a15-b7cc-869dac885033
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516553876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctr
l_edge_detect.516553876
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.2053033742
Short name T495
Test name
Test status
Simulation time 2619205900 ps
CPU time 3.76 seconds
Started Jun 26 04:55:04 PM PDT 24
Finished Jun 26 04:55:12 PM PDT 24
Peak memory 201480 kb
Host smart-486c0889-607b-4ac6-b0d9-8f0ebbd1ebd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053033742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.2053033742
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.3962661263
Short name T24
Test name
Test status
Simulation time 2489006214 ps
CPU time 2.3 seconds
Started Jun 26 04:55:04 PM PDT 24
Finished Jun 26 04:55:12 PM PDT 24
Peak memory 201516 kb
Host smart-961ad82d-563d-47dd-9dc1-c0d26ded4be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962661263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.3962661263
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.1540546777
Short name T468
Test name
Test status
Simulation time 2194480799 ps
CPU time 2.01 seconds
Started Jun 26 04:54:58 PM PDT 24
Finished Jun 26 04:55:03 PM PDT 24
Peak memory 201504 kb
Host smart-59c2c494-8950-46ae-af58-157f4af549ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540546777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.1540546777
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.1308239193
Short name T13
Test name
Test status
Simulation time 2510386338 ps
CPU time 6.9 seconds
Started Jun 26 04:55:05 PM PDT 24
Finished Jun 26 04:55:17 PM PDT 24
Peak memory 201428 kb
Host smart-b993428e-7543-46b3-9b5f-882e7d932b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308239193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.1308239193
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.3078691662
Short name T198
Test name
Test status
Simulation time 2110084607 ps
CPU time 5.84 seconds
Started Jun 26 04:55:06 PM PDT 24
Finished Jun 26 04:55:17 PM PDT 24
Peak memory 201356 kb
Host smart-11f57f28-8489-4087-84d0-42b8a8a3a1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078691662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.3078691662
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.637803433
Short name T107
Test name
Test status
Simulation time 121413556589 ps
CPU time 150.84 seconds
Started Jun 26 04:54:59 PM PDT 24
Finished Jun 26 04:57:33 PM PDT 24
Peak memory 201852 kb
Host smart-10eb2ce8-eb6e-49a4-98df-f44cd7fb2006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637803433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_st
ress_all.637803433
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.129848169
Short name T221
Test name
Test status
Simulation time 16090112705 ps
CPU time 41.04 seconds
Started Jun 26 04:55:03 PM PDT 24
Finished Jun 26 04:55:49 PM PDT 24
Peak memory 201912 kb
Host smart-9f0bdb89-cfc4-4b40-9c8a-df753578a5f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129848169 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.129848169
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.2514556993
Short name T125
Test name
Test status
Simulation time 7432022604 ps
CPU time 4.7 seconds
Started Jun 26 04:55:03 PM PDT 24
Finished Jun 26 04:55:12 PM PDT 24
Peak memory 201464 kb
Host smart-e24d618d-04d4-4f89-90eb-5cbe366d8e8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514556993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ultra_low_pwr.2514556993
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.1851658961
Short name T204
Test name
Test status
Simulation time 2066440945 ps
CPU time 1.35 seconds
Started Jun 26 04:55:08 PM PDT 24
Finished Jun 26 04:55:14 PM PDT 24
Peak memory 201508 kb
Host smart-2fc35922-c3b1-4be5-844a-fe7070402f09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851658961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_te
st.1851658961
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.1516091301
Short name T499
Test name
Test status
Simulation time 3818077321 ps
CPU time 10.54 seconds
Started Jun 26 04:55:02 PM PDT 24
Finished Jun 26 04:55:17 PM PDT 24
Peak memory 201504 kb
Host smart-5f181888-ae4f-442a-a7cc-6c3046aa5586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516091301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.1
516091301
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.2722138863
Short name T677
Test name
Test status
Simulation time 96994970075 ps
CPU time 232.26 seconds
Started Jun 26 04:54:57 PM PDT 24
Finished Jun 26 04:58:51 PM PDT 24
Peak memory 201728 kb
Host smart-1099f3ed-d957-4bdf-857e-937d47490527
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722138863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_combo_detect.2722138863
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.120923402
Short name T574
Test name
Test status
Simulation time 4329305315 ps
CPU time 3.64 seconds
Started Jun 26 04:55:01 PM PDT 24
Finished Jun 26 04:55:09 PM PDT 24
Peak memory 201456 kb
Host smart-0adb860c-2b75-4eb3-805a-1084a1763932
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120923402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_ec_pwr_on_rst.120923402
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.1732953011
Short name T157
Test name
Test status
Simulation time 5394482706 ps
CPU time 6.57 seconds
Started Jun 26 04:55:05 PM PDT 24
Finished Jun 26 04:55:17 PM PDT 24
Peak memory 201548 kb
Host smart-a568b2e0-9acb-42f1-aa9f-1617fa38b79e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732953011 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_edge_detect.1732953011
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.3566816301
Short name T412
Test name
Test status
Simulation time 2630394697 ps
CPU time 2.36 seconds
Started Jun 26 04:55:10 PM PDT 24
Finished Jun 26 04:55:17 PM PDT 24
Peak memory 201744 kb
Host smart-543d98eb-9fd8-4b61-a8a2-079d756f84c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566816301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.3566816301
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.1023394925
Short name T786
Test name
Test status
Simulation time 2496406304 ps
CPU time 2.52 seconds
Started Jun 26 04:55:04 PM PDT 24
Finished Jun 26 04:55:12 PM PDT 24
Peak memory 201444 kb
Host smart-0b7b363f-f185-4d89-8333-172653f285a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023394925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.1023394925
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.2048986647
Short name T14
Test name
Test status
Simulation time 2083732539 ps
CPU time 2.73 seconds
Started Jun 26 04:55:05 PM PDT 24
Finished Jun 26 04:55:13 PM PDT 24
Peak memory 201424 kb
Host smart-da417e45-4d8c-4a5f-9150-e3625bc7fd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048986647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.2048986647
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.3229547709
Short name T539
Test name
Test status
Simulation time 2576323723 ps
CPU time 1.2 seconds
Started Jun 26 04:55:04 PM PDT 24
Finished Jun 26 04:55:11 PM PDT 24
Peak memory 201524 kb
Host smart-00655fab-e68f-4ef7-9531-30545ee98401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229547709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.3229547709
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.986868748
Short name T206
Test name
Test status
Simulation time 2116646047 ps
CPU time 3.29 seconds
Started Jun 26 04:55:04 PM PDT 24
Finished Jun 26 04:55:12 PM PDT 24
Peak memory 201444 kb
Host smart-bab6f3a9-a90a-4dae-adf0-c8a184d13f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986868748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.986868748
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.917320038
Short name T166
Test name
Test status
Simulation time 11270083122 ps
CPU time 24.48 seconds
Started Jun 26 04:55:03 PM PDT 24
Finished Jun 26 04:55:33 PM PDT 24
Peak memory 201456 kb
Host smart-4bd7d034-bbc7-43ef-b66e-142d4a8d9ab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917320038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_st
ress_all.917320038
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.553169188
Short name T319
Test name
Test status
Simulation time 45412415297 ps
CPU time 55.23 seconds
Started Jun 26 04:55:00 PM PDT 24
Finished Jun 26 04:55:58 PM PDT 24
Peak memory 210252 kb
Host smart-d6a29f75-c33b-4203-9c80-ac5791ccef0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553169188 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.553169188
Directory /workspace/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.4279798642
Short name T433
Test name
Test status
Simulation time 5463520939 ps
CPU time 3.84 seconds
Started Jun 26 04:55:04 PM PDT 24
Finished Jun 26 04:55:13 PM PDT 24
Peak memory 201772 kb
Host smart-74700cbf-e8a4-4d89-8b09-71ee0f499802
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279798642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ultra_low_pwr.4279798642
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.1113422809
Short name T149
Test name
Test status
Simulation time 2028975244 ps
CPU time 1.92 seconds
Started Jun 26 04:55:05 PM PDT 24
Finished Jun 26 04:55:12 PM PDT 24
Peak memory 201500 kb
Host smart-1fc408ef-e743-4986-a428-c3df5dc35c11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113422809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te
st.1113422809
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.3671648900
Short name T673
Test name
Test status
Simulation time 2992704379 ps
CPU time 1.51 seconds
Started Jun 26 04:55:11 PM PDT 24
Finished Jun 26 04:55:17 PM PDT 24
Peak memory 201804 kb
Host smart-c516ff2e-dbdf-42fe-aa69-28ab2a7a165c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671648900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.3
671648900
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.1582187061
Short name T106
Test name
Test status
Simulation time 27784922594 ps
CPU time 77.62 seconds
Started Jun 26 04:55:03 PM PDT 24
Finished Jun 26 04:56:24 PM PDT 24
Peak memory 202004 kb
Host smart-5395a351-b638-475e-8ed9-39c6dd3f314c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582187061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.1582187061
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.2036501478
Short name T599
Test name
Test status
Simulation time 3159891941 ps
CPU time 2.46 seconds
Started Jun 26 04:55:00 PM PDT 24
Finished Jun 26 04:55:06 PM PDT 24
Peak memory 201488 kb
Host smart-ca9c3779-b4b3-4cf3-928b-e3f37b0b3b2e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036501478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.2036501478
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.1772949407
Short name T177
Test name
Test status
Simulation time 2448838930 ps
CPU time 2.07 seconds
Started Jun 26 04:55:00 PM PDT 24
Finished Jun 26 04:55:05 PM PDT 24
Peak memory 201484 kb
Host smart-f58ac0ca-09d1-40a4-8626-9744ab0599aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772949407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ct
rl_edge_detect.1772949407
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.2070414635
Short name T432
Test name
Test status
Simulation time 2624368877 ps
CPU time 2.53 seconds
Started Jun 26 04:55:01 PM PDT 24
Finished Jun 26 04:55:08 PM PDT 24
Peak memory 201424 kb
Host smart-5687a1e3-3530-42b1-885c-a668e41d7f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070414635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.2070414635
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.3296370688
Short name T684
Test name
Test status
Simulation time 2454679025 ps
CPU time 3.87 seconds
Started Jun 26 04:55:04 PM PDT 24
Finished Jun 26 04:55:13 PM PDT 24
Peak memory 201716 kb
Host smart-2dd1570e-4f1e-4076-bb5b-a2a19acb18ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296370688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.3296370688
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.3049954963
Short name T660
Test name
Test status
Simulation time 2198075217 ps
CPU time 6.5 seconds
Started Jun 26 04:55:04 PM PDT 24
Finished Jun 26 04:55:16 PM PDT 24
Peak memory 201424 kb
Host smart-98d8b619-1ac9-40ab-a4b4-7170171b55c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049954963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.3049954963
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.272209127
Short name T193
Test name
Test status
Simulation time 2598963867 ps
CPU time 1.23 seconds
Started Jun 26 04:55:06 PM PDT 24
Finished Jun 26 04:55:12 PM PDT 24
Peak memory 201496 kb
Host smart-338772e8-b435-4878-8c88-1697b0d3c15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272209127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.272209127
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.3874067895
Short name T645
Test name
Test status
Simulation time 2171186210 ps
CPU time 1 seconds
Started Jun 26 04:55:03 PM PDT 24
Finished Jun 26 04:55:09 PM PDT 24
Peak memory 201412 kb
Host smart-94bbed6a-f520-4d37-8f23-ca0c5de65135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874067895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.3874067895
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.3082081160
Short name T191
Test name
Test status
Simulation time 39647546529 ps
CPU time 101.07 seconds
Started Jun 26 04:55:11 PM PDT 24
Finished Jun 26 04:56:56 PM PDT 24
Peak memory 201756 kb
Host smart-744c87f7-feb7-4b7d-bc50-9c7cef33a259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082081160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.3082081160
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.2626947076
Short name T27
Test name
Test status
Simulation time 14809009096 ps
CPU time 21.74 seconds
Started Jun 26 04:55:03 PM PDT 24
Finished Jun 26 04:55:30 PM PDT 24
Peak memory 201744 kb
Host smart-51874821-2c72-43db-a758-5cd83814a627
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626947076 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.2626947076
Directory /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.3835760363
Short name T91
Test name
Test status
Simulation time 9392112495 ps
CPU time 8.97 seconds
Started Jun 26 04:55:05 PM PDT 24
Finished Jun 26 04:55:19 PM PDT 24
Peak memory 201520 kb
Host smart-2c1602ff-1e89-4b82-a861-197a4da5c474
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835760363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.3835760363
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.926271307
Short name T546
Test name
Test status
Simulation time 2038077828 ps
CPU time 1.94 seconds
Started Jun 26 04:54:08 PM PDT 24
Finished Jun 26 04:54:13 PM PDT 24
Peak memory 201420 kb
Host smart-92aa5c22-d612-4480-88e9-7f2ea0619158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926271307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test
.926271307
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.3130221197
Short name T625
Test name
Test status
Simulation time 3295679053 ps
CPU time 2.09 seconds
Started Jun 26 04:54:08 PM PDT 24
Finished Jun 26 04:54:12 PM PDT 24
Peak memory 201576 kb
Host smart-48fb3b33-4e7c-48f7-84f3-3e81c2c605de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130221197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.3130221197
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.1860049627
Short name T386
Test name
Test status
Simulation time 71674313813 ps
CPU time 48.58 seconds
Started Jun 26 04:53:49 PM PDT 24
Finished Jun 26 04:54:42 PM PDT 24
Peak memory 201672 kb
Host smart-933380aa-604b-402c-9329-969851ffa8c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860049627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_combo_detect.1860049627
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.325887374
Short name T689
Test name
Test status
Simulation time 2429411909 ps
CPU time 2.12 seconds
Started Jun 26 04:53:46 PM PDT 24
Finished Jun 26 04:53:52 PM PDT 24
Peak memory 201484 kb
Host smart-a7975487-ae65-449f-b70e-36fb714b2ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325887374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.325887374
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1194464773
Short name T236
Test name
Test status
Simulation time 2531138410 ps
CPU time 7.76 seconds
Started Jun 26 04:53:56 PM PDT 24
Finished Jun 26 04:54:06 PM PDT 24
Peak memory 201492 kb
Host smart-b2c37561-2e61-4629-a229-3639e2434cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194464773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1194464773
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3216074570
Short name T768
Test name
Test status
Simulation time 33406150058 ps
CPU time 85.87 seconds
Started Jun 26 04:53:49 PM PDT 24
Finished Jun 26 04:55:18 PM PDT 24
Peak memory 201860 kb
Host smart-2622c75b-0119-462a-bbce-2169e69871d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216074570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wi
th_pre_cond.3216074570
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1438616925
Short name T594
Test name
Test status
Simulation time 3811302068 ps
CPU time 3.15 seconds
Started Jun 26 04:53:50 PM PDT 24
Finished Jun 26 04:53:57 PM PDT 24
Peak memory 201400 kb
Host smart-9dd9e7ba-acad-4e88-bb3d-1c6d6b8217a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438616925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ec_pwr_on_rst.1438616925
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.3650069140
Short name T150
Test name
Test status
Simulation time 4197846551 ps
CPU time 2.09 seconds
Started Jun 26 04:53:53 PM PDT 24
Finished Jun 26 04:53:58 PM PDT 24
Peak memory 201416 kb
Host smart-0918665d-a4f5-4a77-8282-2d4c5b10a320
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650069140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.3650069140
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2247879133
Short name T538
Test name
Test status
Simulation time 2611352348 ps
CPU time 7.48 seconds
Started Jun 26 04:53:51 PM PDT 24
Finished Jun 26 04:54:02 PM PDT 24
Peak memory 201480 kb
Host smart-66229bdf-6041-42e2-b3da-2b094dd04b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247879133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.2247879133
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.1383980980
Short name T482
Test name
Test status
Simulation time 2501367508 ps
CPU time 1.83 seconds
Started Jun 26 04:53:43 PM PDT 24
Finished Jun 26 04:53:49 PM PDT 24
Peak memory 201492 kb
Host smart-a401bf34-faac-4079-960f-2e780b1ad039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383980980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.1383980980
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.3033956304
Short name T472
Test name
Test status
Simulation time 2028323123 ps
CPU time 5.64 seconds
Started Jun 26 04:53:44 PM PDT 24
Finished Jun 26 04:53:54 PM PDT 24
Peak memory 201448 kb
Host smart-be0d5c15-1c61-4d86-bba9-9f3874dddb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033956304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.3033956304
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.459447270
Short name T326
Test name
Test status
Simulation time 2529617890 ps
CPU time 2.34 seconds
Started Jun 26 04:53:49 PM PDT 24
Finished Jun 26 04:53:55 PM PDT 24
Peak memory 201432 kb
Host smart-8d54b482-da81-4a2c-a99a-4ac850d345a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459447270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.459447270
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.1011733682
Short name T286
Test name
Test status
Simulation time 22015538150 ps
CPU time 30.45 seconds
Started Jun 26 04:53:55 PM PDT 24
Finished Jun 26 04:54:28 PM PDT 24
Peak memory 221216 kb
Host smart-a42670db-2770-4ee4-a029-39a6fb9c57fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011733682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.1011733682
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.1501351067
Short name T54
Test name
Test status
Simulation time 2111275254 ps
CPU time 6.01 seconds
Started Jun 26 04:53:55 PM PDT 24
Finished Jun 26 04:54:04 PM PDT 24
Peak memory 201360 kb
Host smart-675be81e-5a49-4198-9267-e20a4b567996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501351067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.1501351067
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.2866364562
Short name T268
Test name
Test status
Simulation time 48061798808 ps
CPU time 17.66 seconds
Started Jun 26 04:54:07 PM PDT 24
Finished Jun 26 04:54:28 PM PDT 24
Peak memory 201748 kb
Host smart-92f5062e-26b0-4668-a8a1-35301e415b0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866364562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_st
ress_all.2866364562
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1165363048
Short name T741
Test name
Test status
Simulation time 6221368905 ps
CPU time 17.58 seconds
Started Jun 26 04:53:56 PM PDT 24
Finished Jun 26 04:54:17 PM PDT 24
Peak memory 201708 kb
Host smart-6ca34120-8b8c-48df-86fe-6c7fec062e10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165363048 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.1165363048
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.909237696
Short name T611
Test name
Test status
Simulation time 7593530262 ps
CPU time 7.08 seconds
Started Jun 26 04:54:06 PM PDT 24
Finished Jun 26 04:54:16 PM PDT 24
Peak memory 201508 kb
Host smart-6f3b9c8f-d070-403b-bcb8-a180c5664638
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909237696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_ultra_low_pwr.909237696
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.977515279
Short name T613
Test name
Test status
Simulation time 2049863189 ps
CPU time 1.25 seconds
Started Jun 26 04:55:28 PM PDT 24
Finished Jun 26 04:55:35 PM PDT 24
Peak memory 201504 kb
Host smart-ad738fd7-a154-43ad-ace7-920b9e4e79a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977515279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_tes
t.977515279
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.393934848
Short name T746
Test name
Test status
Simulation time 106451421158 ps
CPU time 98.57 seconds
Started Jun 26 04:55:04 PM PDT 24
Finished Jun 26 04:56:47 PM PDT 24
Peak memory 201560 kb
Host smart-660c95a8-d1da-4155-8a9f-d23357545b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393934848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.393934848
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.3798554500
Short name T387
Test name
Test status
Simulation time 137924524673 ps
CPU time 357.64 seconds
Started Jun 26 04:55:12 PM PDT 24
Finished Jun 26 05:01:14 PM PDT 24
Peak memory 201724 kb
Host smart-50ff0378-88b9-473b-a2fc-77a63a773a25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798554500 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.3798554500
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.3472369496
Short name T732
Test name
Test status
Simulation time 32735390908 ps
CPU time 50.87 seconds
Started Jun 26 04:55:07 PM PDT 24
Finished Jun 26 04:56:02 PM PDT 24
Peak memory 201792 kb
Host smart-52e3da07-bb6a-4ab3-80bf-daeeacc30889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472369496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w
ith_pre_cond.3472369496
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.1319980890
Short name T657
Test name
Test status
Simulation time 3032000592 ps
CPU time 6.63 seconds
Started Jun 26 04:55:03 PM PDT 24
Finished Jun 26 04:55:14 PM PDT 24
Peak memory 201388 kb
Host smart-26c0158b-452a-41bd-8a96-bf0f9260824b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319980890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ec_pwr_on_rst.1319980890
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.141471803
Short name T227
Test name
Test status
Simulation time 4579030889 ps
CPU time 1.49 seconds
Started Jun 26 04:55:09 PM PDT 24
Finished Jun 26 04:55:15 PM PDT 24
Peak memory 201552 kb
Host smart-62c1346e-7c91-4051-95d0-aad7eaf6cf52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141471803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctr
l_edge_detect.141471803
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3731945323
Short name T769
Test name
Test status
Simulation time 2609960007 ps
CPU time 7.39 seconds
Started Jun 26 04:55:09 PM PDT 24
Finished Jun 26 04:55:21 PM PDT 24
Peak memory 201508 kb
Host smart-89cdb68d-6721-4c64-8a2e-5f60ded2d5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731945323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.3731945323
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.1369980750
Short name T797
Test name
Test status
Simulation time 2445488343 ps
CPU time 4.88 seconds
Started Jun 26 04:55:13 PM PDT 24
Finished Jun 26 04:55:22 PM PDT 24
Peak memory 201488 kb
Host smart-953b00f8-5396-4511-bb45-ac658145f33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369980750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.1369980750
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.1222444319
Short name T543
Test name
Test status
Simulation time 2082580993 ps
CPU time 5.86 seconds
Started Jun 26 04:55:05 PM PDT 24
Finished Jun 26 04:55:16 PM PDT 24
Peak memory 201416 kb
Host smart-e4ac4a05-8cee-4a00-89df-53f1329ac753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222444319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.1222444319
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.1616550228
Short name T428
Test name
Test status
Simulation time 2525654126 ps
CPU time 2.39 seconds
Started Jun 26 04:55:09 PM PDT 24
Finished Jun 26 04:55:16 PM PDT 24
Peak memory 201480 kb
Host smart-99b92f66-840b-41a7-b4b0-2a68d379023e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616550228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.1616550228
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.746822585
Short name T714
Test name
Test status
Simulation time 2121976267 ps
CPU time 3.37 seconds
Started Jun 26 04:55:00 PM PDT 24
Finished Jun 26 04:55:06 PM PDT 24
Peak memory 201436 kb
Host smart-b2c19758-69ad-43d2-8db2-a1cb198a6ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746822585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.746822585
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.1216641404
Short name T415
Test name
Test status
Simulation time 6149269941 ps
CPU time 8.44 seconds
Started Jun 26 04:55:13 PM PDT 24
Finished Jun 26 04:55:26 PM PDT 24
Peak memory 201516 kb
Host smart-df192414-1d10-483c-b5f6-c1890254b475
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216641404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_s
tress_all.1216641404
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.41937526
Short name T726
Test name
Test status
Simulation time 2558771085 ps
CPU time 3.36 seconds
Started Jun 26 04:55:12 PM PDT 24
Finished Jun 26 04:55:19 PM PDT 24
Peak memory 201500 kb
Host smart-8ff7cf0f-c7ee-4b5f-85a0-2f1e21cdbef9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41937526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_ultra_low_pwr.41937526
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.379295384
Short name T171
Test name
Test status
Simulation time 2022321658 ps
CPU time 1.91 seconds
Started Jun 26 04:55:30 PM PDT 24
Finished Jun 26 04:55:39 PM PDT 24
Peak memory 201372 kb
Host smart-3b1aefb3-da7b-4584-a465-e105548727c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379295384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_tes
t.379295384
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.226924483
Short name T515
Test name
Test status
Simulation time 3253237265 ps
CPU time 2.81 seconds
Started Jun 26 04:55:09 PM PDT 24
Finished Jun 26 04:55:17 PM PDT 24
Peak memory 201532 kb
Host smart-e4ab9183-ebce-4fde-baa5-6220fa80965c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226924483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.226924483
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.3903501361
Short name T362
Test name
Test status
Simulation time 109660844370 ps
CPU time 286.58 seconds
Started Jun 26 04:55:11 PM PDT 24
Finished Jun 26 05:00:02 PM PDT 24
Peak memory 201748 kb
Host smart-c732cd2b-78c9-45e7-adbd-bad0763c95bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903501361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_combo_detect.3903501361
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2693411225
Short name T246
Test name
Test status
Simulation time 23833908224 ps
CPU time 66.41 seconds
Started Jun 26 04:55:16 PM PDT 24
Finished Jun 26 04:56:26 PM PDT 24
Peak memory 201848 kb
Host smart-634921a7-0960-4cc2-a4db-06b444849041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693411225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_w
ith_pre_cond.2693411225
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.4017911504
Short name T486
Test name
Test status
Simulation time 5151228947 ps
CPU time 13.36 seconds
Started Jun 26 04:55:06 PM PDT 24
Finished Jun 26 04:55:24 PM PDT 24
Peak memory 201460 kb
Host smart-e0893fbb-521e-4e16-ad0d-a3be116d0324
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017911504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ec_pwr_on_rst.4017911504
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.2687668884
Short name T11
Test name
Test status
Simulation time 1204366458771 ps
CPU time 3033.63 seconds
Started Jun 26 04:55:30 PM PDT 24
Finished Jun 26 05:46:11 PM PDT 24
Peak memory 201392 kb
Host smart-c7e986c2-4f27-4644-b800-4ba0273c552e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687668884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_edge_detect.2687668884
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2938985221
Short name T5
Test name
Test status
Simulation time 2607810467 ps
CPU time 7.06 seconds
Started Jun 26 04:55:10 PM PDT 24
Finished Jun 26 04:55:21 PM PDT 24
Peak memory 201412 kb
Host smart-d6600edf-399f-48b4-be6c-b89430adb1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938985221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.2938985221
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.163867505
Short name T575
Test name
Test status
Simulation time 2489185650 ps
CPU time 2.26 seconds
Started Jun 26 04:55:23 PM PDT 24
Finished Jun 26 04:55:30 PM PDT 24
Peak memory 201492 kb
Host smart-a9031f5b-7408-4e3d-8e18-f36db0cd30b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163867505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.163867505
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.914794883
Short name T685
Test name
Test status
Simulation time 2161664753 ps
CPU time 6.43 seconds
Started Jun 26 04:55:21 PM PDT 24
Finished Jun 26 04:55:30 PM PDT 24
Peak memory 201516 kb
Host smart-db3a9961-b722-43c4-883e-34b5ea35e607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914794883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.914794883
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.3424846856
Short name T444
Test name
Test status
Simulation time 2510342480 ps
CPU time 7.07 seconds
Started Jun 26 04:55:28 PM PDT 24
Finished Jun 26 04:55:41 PM PDT 24
Peak memory 201508 kb
Host smart-1c28664d-21b8-4009-940f-a7b1cfa5dac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424846856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.3424846856
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.3202575979
Short name T487
Test name
Test status
Simulation time 2132529779 ps
CPU time 1.96 seconds
Started Jun 26 04:55:07 PM PDT 24
Finished Jun 26 04:55:14 PM PDT 24
Peak memory 201360 kb
Host smart-fcd7fdf6-833d-4b17-a7c0-4f899c85a539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202575979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.3202575979
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.575657715
Short name T544
Test name
Test status
Simulation time 14589859112 ps
CPU time 15.97 seconds
Started Jun 26 04:55:12 PM PDT 24
Finished Jun 26 04:55:33 PM PDT 24
Peak memory 201788 kb
Host smart-0ae3cc3b-377a-47a0-94c3-553131c82c42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575657715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_st
ress_all.575657715
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.3692392919
Short name T302
Test name
Test status
Simulation time 29744087642 ps
CPU time 75.19 seconds
Started Jun 26 04:55:15 PM PDT 24
Finished Jun 26 04:56:34 PM PDT 24
Peak memory 218216 kb
Host smart-245b8e65-d866-4c16-8d03-9dd9ed451696
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692392919 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.3692392919
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3031201214
Short name T562
Test name
Test status
Simulation time 6496513998 ps
CPU time 2.5 seconds
Started Jun 26 04:55:08 PM PDT 24
Finished Jun 26 04:55:15 PM PDT 24
Peak memory 201500 kb
Host smart-2f890534-6e32-4156-85f2-0b85f47b2506
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031201214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ultra_low_pwr.3031201214
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.3165453264
Short name T114
Test name
Test status
Simulation time 2029740191 ps
CPU time 1.85 seconds
Started Jun 26 04:55:16 PM PDT 24
Finished Jun 26 04:55:22 PM PDT 24
Peak memory 201236 kb
Host smart-4e16b7ae-f437-4def-bb2f-7e082a64710a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165453264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_te
st.3165453264
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3056506543
Short name T507
Test name
Test status
Simulation time 3888502831 ps
CPU time 3.21 seconds
Started Jun 26 04:55:09 PM PDT 24
Finished Jun 26 04:55:17 PM PDT 24
Peak memory 201500 kb
Host smart-9213a201-54a7-494d-b234-6f3fa40a8196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056506543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.3
056506543
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.1043466267
Short name T116
Test name
Test status
Simulation time 131544847092 ps
CPU time 320.58 seconds
Started Jun 26 04:55:26 PM PDT 24
Finished Jun 26 05:00:52 PM PDT 24
Peak memory 201780 kb
Host smart-eff97976-3800-4591-8fab-20cfa3904f4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043466267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.1043466267
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2131696040
Short name T380
Test name
Test status
Simulation time 81625244763 ps
CPU time 100.52 seconds
Started Jun 26 04:55:10 PM PDT 24
Finished Jun 26 04:56:55 PM PDT 24
Peak memory 201832 kb
Host smart-2f462e3e-e7a2-4c36-a862-3e59f1a63343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131696040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_w
ith_pre_cond.2131696040
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.268896136
Short name T409
Test name
Test status
Simulation time 3771964388 ps
CPU time 5.75 seconds
Started Jun 26 04:55:09 PM PDT 24
Finished Jun 26 04:55:19 PM PDT 24
Peak memory 201492 kb
Host smart-6e141816-35ca-4629-9969-d68d99afd2fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268896136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_ec_pwr_on_rst.268896136
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.1008646056
Short name T153
Test name
Test status
Simulation time 4804864449 ps
CPU time 10.12 seconds
Started Jun 26 04:55:05 PM PDT 24
Finished Jun 26 04:55:24 PM PDT 24
Peak memory 201508 kb
Host smart-de266064-a280-4d5a-9ee8-1e4e175aa0f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008646056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_edge_detect.1008646056
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.956725613
Short name T208
Test name
Test status
Simulation time 2633182226 ps
CPU time 2.3 seconds
Started Jun 26 04:55:16 PM PDT 24
Finished Jun 26 04:55:22 PM PDT 24
Peak memory 201528 kb
Host smart-79f5a293-939c-4f58-a2f3-c4d11faf11ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956725613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.956725613
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.4128752852
Short name T669
Test name
Test status
Simulation time 2552039571 ps
CPU time 0.97 seconds
Started Jun 26 04:55:10 PM PDT 24
Finished Jun 26 04:55:15 PM PDT 24
Peak memory 201484 kb
Host smart-7dcbcd48-3bcc-4966-9c82-bd728288d35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128752852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.4128752852
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.1904024791
Short name T110
Test name
Test status
Simulation time 2082951713 ps
CPU time 6.33 seconds
Started Jun 26 04:55:08 PM PDT 24
Finished Jun 26 04:55:19 PM PDT 24
Peak memory 201364 kb
Host smart-8e9feef9-9e46-4a83-bedd-d7fd26af7388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904024791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.1904024791
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.4185450464
Short name T696
Test name
Test status
Simulation time 2510703109 ps
CPU time 7.2 seconds
Started Jun 26 04:55:11 PM PDT 24
Finished Jun 26 04:55:23 PM PDT 24
Peak memory 201472 kb
Host smart-e3138633-96be-43aa-9925-6b5eaa8541da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185450464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.4185450464
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.4048966142
Short name T561
Test name
Test status
Simulation time 2113196160 ps
CPU time 3.38 seconds
Started Jun 26 04:55:29 PM PDT 24
Finished Jun 26 04:55:39 PM PDT 24
Peak memory 201444 kb
Host smart-0f2bd764-a6d3-4a79-a827-3d7bd678755b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048966142 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.4048966142
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.1919890778
Short name T542
Test name
Test status
Simulation time 9433559716 ps
CPU time 23.58 seconds
Started Jun 26 04:55:22 PM PDT 24
Finished Jun 26 04:55:48 PM PDT 24
Peak memory 201592 kb
Host smart-3ac2cffe-8de2-4a3a-90dd-9f9a45647d99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919890778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_s
tress_all.1919890778
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.3835138029
Short name T127
Test name
Test status
Simulation time 46074105497 ps
CPU time 109.01 seconds
Started Jun 26 04:55:26 PM PDT 24
Finished Jun 26 04:57:20 PM PDT 24
Peak memory 210476 kb
Host smart-a446faab-b0ef-4c9a-966e-552185073c5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835138029 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.3835138029
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.11179852
Short name T137
Test name
Test status
Simulation time 8417716369 ps
CPU time 7.12 seconds
Started Jun 26 04:55:08 PM PDT 24
Finished Jun 26 04:55:20 PM PDT 24
Peak memory 201552 kb
Host smart-0d86b5f0-6b26-4b2d-a5f1-febaf7d61317
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11179852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_ultra_low_pwr.11179852
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.2069820739
Short name T593
Test name
Test status
Simulation time 2019245439 ps
CPU time 3.92 seconds
Started Jun 26 04:55:09 PM PDT 24
Finished Jun 26 04:55:18 PM PDT 24
Peak memory 201480 kb
Host smart-3e26c7b3-40f2-4ebf-97aa-e93883f2342b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069820739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_te
st.2069820739
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1553697019
Short name T49
Test name
Test status
Simulation time 2978250803 ps
CPU time 8.38 seconds
Started Jun 26 04:55:07 PM PDT 24
Finished Jun 26 04:55:20 PM PDT 24
Peak memory 201492 kb
Host smart-8f28d6d7-d6f2-4c2e-b44c-d63b445c94a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553697019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.1
553697019
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.1764490826
Short name T328
Test name
Test status
Simulation time 135374541560 ps
CPU time 175.95 seconds
Started Jun 26 04:55:16 PM PDT 24
Finished Jun 26 04:58:16 PM PDT 24
Peak memory 201540 kb
Host smart-d35355a5-c2d0-4f4a-b9c9-22b990453fc3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764490826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.1764490826
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.4262053161
Short name T722
Test name
Test status
Simulation time 3382633106 ps
CPU time 1.6 seconds
Started Jun 26 04:55:12 PM PDT 24
Finished Jun 26 04:55:18 PM PDT 24
Peak memory 201468 kb
Host smart-a89fb667-1fa8-4c2a-ab78-6ca546a49a30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262053161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.4262053161
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.2994413067
Short name T336
Test name
Test status
Simulation time 4658839726 ps
CPU time 10.14 seconds
Started Jun 26 04:55:16 PM PDT 24
Finished Jun 26 04:55:30 PM PDT 24
Peak memory 201536 kb
Host smart-25e3bede-3b18-41b3-991b-7d525648088b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994413067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_edge_detect.2994413067
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2315713536
Short name T130
Test name
Test status
Simulation time 2628301880 ps
CPU time 2.5 seconds
Started Jun 26 04:55:05 PM PDT 24
Finished Jun 26 04:55:13 PM PDT 24
Peak memory 201508 kb
Host smart-1bafcc8b-61a6-4f59-9003-9e140d324d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315713536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.2315713536
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.2325487968
Short name T580
Test name
Test status
Simulation time 2465709213 ps
CPU time 2.2 seconds
Started Jun 26 04:55:05 PM PDT 24
Finished Jun 26 04:55:13 PM PDT 24
Peak memory 201512 kb
Host smart-14e330bb-26d5-428e-8fe6-6e9852ecf97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325487968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.2325487968
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.4238061597
Short name T196
Test name
Test status
Simulation time 2110940011 ps
CPU time 6.09 seconds
Started Jun 26 04:55:06 PM PDT 24
Finished Jun 26 04:55:17 PM PDT 24
Peak memory 201376 kb
Host smart-1698e807-524a-41f7-90e3-a41e13411962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238061597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.4238061597
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.598970319
Short name T798
Test name
Test status
Simulation time 2512151895 ps
CPU time 7.22 seconds
Started Jun 26 04:55:30 PM PDT 24
Finished Jun 26 04:55:44 PM PDT 24
Peak memory 201412 kb
Host smart-44d21065-6de7-4d3a-a4f4-2e31acfcbf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598970319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.598970319
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.2293690675
Short name T170
Test name
Test status
Simulation time 2127546115 ps
CPU time 1.58 seconds
Started Jun 26 04:55:06 PM PDT 24
Finished Jun 26 04:55:12 PM PDT 24
Peak memory 201396 kb
Host smart-b9d98ce5-a526-4f4d-b24c-11b0a8ad798a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293690675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.2293690675
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.3655293885
Short name T46
Test name
Test status
Simulation time 15164243822 ps
CPU time 10.44 seconds
Started Jun 26 04:55:14 PM PDT 24
Finished Jun 26 04:55:29 PM PDT 24
Peak memory 201576 kb
Host smart-25f2b347-f617-495e-bd36-3174df2bfce6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655293885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_s
tress_all.3655293885
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2270156452
Short name T738
Test name
Test status
Simulation time 57026308766 ps
CPU time 33.8 seconds
Started Jun 26 04:55:18 PM PDT 24
Finished Jun 26 04:55:55 PM PDT 24
Peak memory 217988 kb
Host smart-8706db02-e1d9-4a0f-99c9-96edf9a70dcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270156452 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.2270156452
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1431912707
Short name T123
Test name
Test status
Simulation time 2722057344311 ps
CPU time 325.83 seconds
Started Jun 26 04:55:10 PM PDT 24
Finished Jun 26 05:00:40 PM PDT 24
Peak memory 201796 kb
Host smart-eb490eec-03a2-4b58-b481-5c69346cabf9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431912707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ultra_low_pwr.1431912707
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.2117042138
Short name T441
Test name
Test status
Simulation time 2013171997 ps
CPU time 5.5 seconds
Started Jun 26 04:55:23 PM PDT 24
Finished Jun 26 04:55:34 PM PDT 24
Peak memory 201412 kb
Host smart-1f6b8076-4864-40d1-8501-df927ce8cc7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117042138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_te
st.2117042138
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1385898151
Short name T524
Test name
Test status
Simulation time 3647267194 ps
CPU time 3.06 seconds
Started Jun 26 04:55:13 PM PDT 24
Finished Jun 26 04:55:21 PM PDT 24
Peak memory 201584 kb
Host smart-a3c72e1a-764e-461e-8b19-e51a72fbedba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385898151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.1
385898151
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.462065930
Short name T100
Test name
Test status
Simulation time 143817255882 ps
CPU time 344.45 seconds
Started Jun 26 04:55:30 PM PDT 24
Finished Jun 26 05:01:22 PM PDT 24
Peak memory 201624 kb
Host smart-42b64578-8a1c-45f8-a9b8-e7262213050e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462065930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_combo_detect.462065930
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2259818612
Short name T186
Test name
Test status
Simulation time 106268422154 ps
CPU time 74.01 seconds
Started Jun 26 04:55:25 PM PDT 24
Finished Jun 26 04:56:44 PM PDT 24
Peak memory 201740 kb
Host smart-a3eca608-bc5e-41f1-9825-41a98db0d42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259818612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_w
ith_pre_cond.2259818612
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1660027343
Short name T493
Test name
Test status
Simulation time 2644775007 ps
CPU time 7.25 seconds
Started Jun 26 04:55:30 PM PDT 24
Finished Jun 26 04:55:44 PM PDT 24
Peak memory 201480 kb
Host smart-0e441071-4bcc-44bb-9121-3b19a4b134e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660027343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ec_pwr_on_rst.1660027343
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.1533916289
Short name T87
Test name
Test status
Simulation time 2733402771 ps
CPU time 3.8 seconds
Started Jun 26 04:55:31 PM PDT 24
Finished Jun 26 04:55:42 PM PDT 24
Peak memory 201372 kb
Host smart-79a8109e-0588-4866-8c98-c5d2b9d3bc61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533916289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.1533916289
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2261581939
Short name T565
Test name
Test status
Simulation time 2637863927 ps
CPU time 2.41 seconds
Started Jun 26 04:55:38 PM PDT 24
Finished Jun 26 04:55:44 PM PDT 24
Peak memory 200864 kb
Host smart-1f0140e3-c0d8-4fd9-aa08-f92710052b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261581939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.2261581939
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.1637582398
Short name T634
Test name
Test status
Simulation time 2460554144 ps
CPU time 2.2 seconds
Started Jun 26 04:55:30 PM PDT 24
Finished Jun 26 04:55:40 PM PDT 24
Peak memory 201332 kb
Host smart-6ece8001-f4c4-4fc7-bbdf-985aad905561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637582398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.1637582398
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.745546976
Short name T716
Test name
Test status
Simulation time 2117543718 ps
CPU time 2 seconds
Started Jun 26 04:55:22 PM PDT 24
Finished Jun 26 04:55:26 PM PDT 24
Peak memory 201448 kb
Host smart-2034d0e8-95f9-4e19-8368-36caf81286e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745546976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.745546976
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2088984282
Short name T67
Test name
Test status
Simulation time 2591907797 ps
CPU time 1.24 seconds
Started Jun 26 04:55:20 PM PDT 24
Finished Jun 26 04:55:23 PM PDT 24
Peak memory 201528 kb
Host smart-9622c2c9-d39c-4a9b-9758-c91ef86109a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088984282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.2088984282
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.3119542313
Short name T517
Test name
Test status
Simulation time 2113132257 ps
CPU time 5.95 seconds
Started Jun 26 04:55:13 PM PDT 24
Finished Jun 26 04:55:24 PM PDT 24
Peak memory 201408 kb
Host smart-34b2f3f0-123a-4d73-85e8-184a3e1407f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119542313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.3119542313
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.1260020109
Short name T174
Test name
Test status
Simulation time 95876189632 ps
CPU time 114.24 seconds
Started Jun 26 04:55:22 PM PDT 24
Finished Jun 26 04:57:19 PM PDT 24
Peak memory 201204 kb
Host smart-0e6fd41f-d13d-48e9-a009-3ebf105fdede
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260020109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.1260020109
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2265897495
Short name T795
Test name
Test status
Simulation time 5689431126 ps
CPU time 1.1 seconds
Started Jun 26 04:55:15 PM PDT 24
Finished Jun 26 04:55:20 PM PDT 24
Peak memory 201468 kb
Host smart-e555766d-64b3-45b4-8661-6c7c71df8a71
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265897495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ultra_low_pwr.2265897495
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.1365587482
Short name T773
Test name
Test status
Simulation time 2035918291 ps
CPU time 1.96 seconds
Started Jun 26 04:55:27 PM PDT 24
Finished Jun 26 04:55:35 PM PDT 24
Peak memory 201500 kb
Host smart-df5ba5c1-b30f-42b6-883e-1849769bf14f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365587482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_te
st.1365587482
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.4071275342
Short name T316
Test name
Test status
Simulation time 222729034242 ps
CPU time 137.51 seconds
Started Jun 26 04:55:31 PM PDT 24
Finished Jun 26 04:57:56 PM PDT 24
Peak memory 201332 kb
Host smart-103f12d7-eae2-449d-82f3-2b4559755b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071275342 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.4
071275342
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.3631405371
Short name T265
Test name
Test status
Simulation time 83350335552 ps
CPU time 198.75 seconds
Started Jun 26 04:55:15 PM PDT 24
Finished Jun 26 04:58:38 PM PDT 24
Peak memory 201792 kb
Host smart-e8e08275-92e5-4689-88a7-a18cd7d29aa4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631405371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.3631405371
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.119588065
Short name T254
Test name
Test status
Simulation time 54364347333 ps
CPU time 53.86 seconds
Started Jun 26 04:55:13 PM PDT 24
Finished Jun 26 04:56:11 PM PDT 24
Peak memory 201792 kb
Host smart-e969ed82-e05b-47f1-8232-8ad65dcd0e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119588065 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_wi
th_pre_cond.119588065
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.322155146
Short name T621
Test name
Test status
Simulation time 4101195809 ps
CPU time 11.05 seconds
Started Jun 26 04:55:14 PM PDT 24
Finished Jun 26 04:55:29 PM PDT 24
Peak memory 201488 kb
Host smart-0347c2c1-01ae-409e-a914-f46d713074ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322155146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_ec_pwr_on_rst.322155146
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.2091328941
Short name T700
Test name
Test status
Simulation time 3170959628 ps
CPU time 2.11 seconds
Started Jun 26 04:55:31 PM PDT 24
Finished Jun 26 04:55:41 PM PDT 24
Peak memory 201332 kb
Host smart-aca6a162-5870-4f97-981a-ffb99560ee13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091328941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_edge_detect.2091328941
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.165218800
Short name T238
Test name
Test status
Simulation time 2627549321 ps
CPU time 2.43 seconds
Started Jun 26 04:55:14 PM PDT 24
Finished Jun 26 04:55:21 PM PDT 24
Peak memory 201424 kb
Host smart-494ae7f7-8ffe-4435-b730-c52d44b93d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165218800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.165218800
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.2054594692
Short name T431
Test name
Test status
Simulation time 2525223557 ps
CPU time 1.15 seconds
Started Jun 26 04:55:30 PM PDT 24
Finished Jun 26 04:55:39 PM PDT 24
Peak memory 201340 kb
Host smart-411c884d-591c-45b3-a015-553e494081bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054594692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.2054594692
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.1475846993
Short name T516
Test name
Test status
Simulation time 2246467319 ps
CPU time 6.75 seconds
Started Jun 26 04:55:31 PM PDT 24
Finished Jun 26 04:55:45 PM PDT 24
Peak memory 201380 kb
Host smart-f95669dc-3352-4a04-aa38-6cef81083056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475846993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.1475846993
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.2256118973
Short name T628
Test name
Test status
Simulation time 2511302515 ps
CPU time 7.52 seconds
Started Jun 26 04:55:25 PM PDT 24
Finished Jun 26 04:55:37 PM PDT 24
Peak memory 201516 kb
Host smart-c9db0031-4b92-4320-b2e0-1f2b96facaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256118973 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.2256118973
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.4293871796
Short name T540
Test name
Test status
Simulation time 2110395670 ps
CPU time 5.6 seconds
Started Jun 26 04:55:13 PM PDT 24
Finished Jun 26 04:55:23 PM PDT 24
Peak memory 201352 kb
Host smart-9bb8f573-5197-43c9-9b53-b32290d2b632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293871796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.4293871796
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.1172630352
Short name T173
Test name
Test status
Simulation time 34939756471 ps
CPU time 93.77 seconds
Started Jun 26 04:55:17 PM PDT 24
Finished Jun 26 04:56:54 PM PDT 24
Peak memory 210208 kb
Host smart-aaf5ee01-657d-4d41-b337-de5e74911a01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172630352 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.1172630352
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2255567920
Short name T570
Test name
Test status
Simulation time 3035458149 ps
CPU time 2.11 seconds
Started Jun 26 04:55:24 PM PDT 24
Finished Jun 26 04:55:31 PM PDT 24
Peak memory 201440 kb
Host smart-4e8752e5-bb9e-4cb4-82cc-082234747a15
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255567920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ultra_low_pwr.2255567920
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.2294311043
Short name T446
Test name
Test status
Simulation time 2031390041 ps
CPU time 2.37 seconds
Started Jun 26 04:55:25 PM PDT 24
Finished Jun 26 04:55:32 PM PDT 24
Peak memory 201448 kb
Host smart-0744c9e6-04f1-4297-acc3-af2e86ac4b53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294311043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.2294311043
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.806165590
Short name T223
Test name
Test status
Simulation time 3186949152 ps
CPU time 8.75 seconds
Started Jun 26 04:55:15 PM PDT 24
Finished Jun 26 04:55:28 PM PDT 24
Peak memory 201532 kb
Host smart-a11bb9e0-af2d-474b-9337-38d1f32b6bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806165590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.806165590
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.2937936570
Short name T280
Test name
Test status
Simulation time 172457223462 ps
CPU time 439.85 seconds
Started Jun 26 04:55:30 PM PDT 24
Finished Jun 26 05:02:57 PM PDT 24
Peak memory 201676 kb
Host smart-fbd75659-e912-4ab3-95e0-18d579149952
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937936570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_combo_detect.2937936570
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1230689236
Short name T756
Test name
Test status
Simulation time 3581478658 ps
CPU time 1.95 seconds
Started Jun 26 04:55:22 PM PDT 24
Finished Jun 26 04:55:27 PM PDT 24
Peak memory 201120 kb
Host smart-1d6a45b2-0fd0-4e68-904e-2bbd431b44c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230689236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ec_pwr_on_rst.1230689236
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.2736225494
Short name T765
Test name
Test status
Simulation time 2621253803 ps
CPU time 2.45 seconds
Started Jun 26 04:55:28 PM PDT 24
Finished Jun 26 04:55:36 PM PDT 24
Peak memory 201400 kb
Host smart-73d07070-b1ee-4cab-b473-f098bd7b919a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736225494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.2736225494
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.963764398
Short name T772
Test name
Test status
Simulation time 2615238412 ps
CPU time 3.76 seconds
Started Jun 26 04:55:31 PM PDT 24
Finished Jun 26 04:55:42 PM PDT 24
Peak memory 201416 kb
Host smart-85ad2566-fde4-4bb1-9e79-28e3818a8884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963764398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.963764398
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3205677719
Short name T323
Test name
Test status
Simulation time 2460036906 ps
CPU time 2.95 seconds
Started Jun 26 04:55:27 PM PDT 24
Finished Jun 26 04:55:36 PM PDT 24
Peak memory 201516 kb
Host smart-f16d330b-8a51-44a6-8295-090d5eaac745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205677719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.3205677719
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.567086051
Short name T234
Test name
Test status
Simulation time 2187314677 ps
CPU time 3.39 seconds
Started Jun 26 04:55:29 PM PDT 24
Finished Jun 26 04:55:39 PM PDT 24
Peak memory 201416 kb
Host smart-f7aeec3d-a0f9-44a6-afc0-4c16ceaa7dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567086051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.567086051
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1439206392
Short name T528
Test name
Test status
Simulation time 2534107888 ps
CPU time 2.38 seconds
Started Jun 26 04:55:31 PM PDT 24
Finished Jun 26 04:55:41 PM PDT 24
Peak memory 201344 kb
Host smart-a75fc3e6-d4a1-42e7-be6c-99fab49f4bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439206392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.1439206392
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.1477400327
Short name T591
Test name
Test status
Simulation time 2111791801 ps
CPU time 5.79 seconds
Started Jun 26 04:55:13 PM PDT 24
Finished Jun 26 04:55:24 PM PDT 24
Peak memory 201408 kb
Host smart-dbaeb348-edc1-4150-ab56-418e7a53c254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477400327 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.1477400327
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.4290014570
Short name T586
Test name
Test status
Simulation time 10174867247 ps
CPU time 6.59 seconds
Started Jun 26 04:55:33 PM PDT 24
Finished Jun 26 04:55:46 PM PDT 24
Peak memory 201476 kb
Host smart-b54fa4ea-d7c6-436f-a560-42645480d1e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290014570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_s
tress_all.4290014570
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1073398728
Short name T717
Test name
Test status
Simulation time 33564253001 ps
CPU time 41.15 seconds
Started Jun 26 04:55:29 PM PDT 24
Finished Jun 26 04:56:16 PM PDT 24
Peak memory 210120 kb
Host smart-9a732813-0ae8-4150-bdec-e9f58eb2fadb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073398728 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.1073398728
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3799466220
Short name T89
Test name
Test status
Simulation time 6974124280 ps
CPU time 4.51 seconds
Started Jun 26 04:55:31 PM PDT 24
Finished Jun 26 04:55:43 PM PDT 24
Peak memory 201320 kb
Host smart-d80c976b-dda1-43ac-bbb4-b9b980a96914
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799466220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ultra_low_pwr.3799466220
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.3378822805
Short name T577
Test name
Test status
Simulation time 2009044499 ps
CPU time 5.59 seconds
Started Jun 26 04:55:22 PM PDT 24
Finished Jun 26 04:55:30 PM PDT 24
Peak memory 201424 kb
Host smart-5605d750-b103-4fd1-9617-0958b131dee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378822805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.3378822805
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2474394082
Short name T28
Test name
Test status
Simulation time 3447196858 ps
CPU time 2.06 seconds
Started Jun 26 04:55:28 PM PDT 24
Finished Jun 26 04:55:36 PM PDT 24
Peak memory 201580 kb
Host smart-834662c4-c549-4690-8469-6c8a434e0748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474394082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.2
474394082
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.287790376
Short name T502
Test name
Test status
Simulation time 114899431162 ps
CPU time 288.63 seconds
Started Jun 26 04:55:21 PM PDT 24
Finished Jun 26 05:00:12 PM PDT 24
Peak memory 201772 kb
Host smart-01f94db7-4c54-4d88-8b16-30434ed45771
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287790376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ct
rl_combo_detect.287790376
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2955671546
Short name T377
Test name
Test status
Simulation time 59606730030 ps
CPU time 76.06 seconds
Started Jun 26 04:55:27 PM PDT 24
Finished Jun 26 04:56:53 PM PDT 24
Peak memory 201720 kb
Host smart-52eb8e8c-0a4a-4f9b-aef2-8425d2c5602e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955671546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_w
ith_pre_cond.2955671546
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.691808887
Short name T411
Test name
Test status
Simulation time 4457869508 ps
CPU time 3.34 seconds
Started Jun 26 04:55:21 PM PDT 24
Finished Jun 26 04:55:27 PM PDT 24
Peak memory 201464 kb
Host smart-2c2823f0-7786-4635-b5df-fef9f8b13774
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691808887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_ec_pwr_on_rst.691808887
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.544206334
Short name T160
Test name
Test status
Simulation time 4194972435 ps
CPU time 3.46 seconds
Started Jun 26 04:55:29 PM PDT 24
Finished Jun 26 04:55:39 PM PDT 24
Peak memory 201448 kb
Host smart-6a7c7be5-66cb-4fcb-9b19-5be7bf4d3a4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544206334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctr
l_edge_detect.544206334
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1698831270
Short name T597
Test name
Test status
Simulation time 2617961855 ps
CPU time 4.56 seconds
Started Jun 26 04:55:27 PM PDT 24
Finished Jun 26 04:55:36 PM PDT 24
Peak memory 201440 kb
Host smart-a05b7342-f0ad-444b-978e-9bcfa241e1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698831270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.1698831270
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2869702452
Short name T749
Test name
Test status
Simulation time 2455371495 ps
CPU time 7.14 seconds
Started Jun 26 04:55:27 PM PDT 24
Finished Jun 26 04:55:38 PM PDT 24
Peak memory 201436 kb
Host smart-318e6e04-ce1c-47cc-8a25-735cc7116e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869702452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.2869702452
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.200693948
Short name T623
Test name
Test status
Simulation time 2281371284 ps
CPU time 2.13 seconds
Started Jun 26 04:55:23 PM PDT 24
Finished Jun 26 04:55:29 PM PDT 24
Peak memory 201428 kb
Host smart-094886cc-85af-42fb-beb9-caa1398092b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200693948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.200693948
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1209485799
Short name T640
Test name
Test status
Simulation time 2578440319 ps
CPU time 1.2 seconds
Started Jun 26 04:55:22 PM PDT 24
Finished Jun 26 04:55:25 PM PDT 24
Peak memory 201428 kb
Host smart-b1861d26-95bf-4b95-b548-ec4ded12e139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209485799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.1209485799
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.3430117671
Short name T563
Test name
Test status
Simulation time 2113546836 ps
CPU time 5.63 seconds
Started Jun 26 04:55:22 PM PDT 24
Finished Jun 26 04:55:31 PM PDT 24
Peak memory 201412 kb
Host smart-e7586c06-c7e6-44cb-a6f2-a236a90c8f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430117671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.3430117671
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.897802894
Short name T230
Test name
Test status
Simulation time 11155327271 ps
CPU time 30.48 seconds
Started Jun 26 04:55:28 PM PDT 24
Finished Jun 26 04:56:05 PM PDT 24
Peak memory 201464 kb
Host smart-e8b5b248-7007-4d48-8fde-4ec8401f4c89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897802894 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_st
ress_all.897802894
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.701659428
Short name T724
Test name
Test status
Simulation time 1880555976449 ps
CPU time 105.02 seconds
Started Jun 26 04:55:31 PM PDT 24
Finished Jun 26 04:57:24 PM PDT 24
Peak memory 201588 kb
Host smart-286f94ea-9d8e-469d-8028-b7e5ad491b95
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701659428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_ultra_low_pwr.701659428
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.1172474690
Short name T728
Test name
Test status
Simulation time 2033067488 ps
CPU time 2.23 seconds
Started Jun 26 04:55:30 PM PDT 24
Finished Jun 26 04:55:39 PM PDT 24
Peak memory 201504 kb
Host smart-0e822fa6-5fdd-4382-99b4-f2d96f1d5294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172474690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.1172474690
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3381216882
Short name T480
Test name
Test status
Simulation time 3373869812 ps
CPU time 2.85 seconds
Started Jun 26 04:55:27 PM PDT 24
Finished Jun 26 04:55:34 PM PDT 24
Peak memory 201516 kb
Host smart-fb278107-759f-49df-9b46-23ceef8d2cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381216882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.3
381216882
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.847550776
Short name T715
Test name
Test status
Simulation time 128299177465 ps
CPU time 346.81 seconds
Started Jun 26 04:55:24 PM PDT 24
Finished Jun 26 05:01:15 PM PDT 24
Peak memory 201752 kb
Host smart-2a670af6-2b56-4571-9168-d4cd61950895
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847550776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_combo_detect.847550776
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3533685619
Short name T525
Test name
Test status
Simulation time 32756126238 ps
CPU time 40.43 seconds
Started Jun 26 04:55:30 PM PDT 24
Finished Jun 26 04:56:18 PM PDT 24
Peak memory 201696 kb
Host smart-10b72c19-04fa-49ab-8f84-62319b24583e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533685619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w
ith_pre_cond.3533685619
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3725201594
Short name T476
Test name
Test status
Simulation time 4994758515 ps
CPU time 12.65 seconds
Started Jun 26 04:55:23 PM PDT 24
Finished Jun 26 04:55:40 PM PDT 24
Peak memory 201464 kb
Host smart-010f274e-abf8-4205-a571-dfe4ef755a55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725201594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ec_pwr_on_rst.3725201594
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.1668369005
Short name T70
Test name
Test status
Simulation time 2359971659 ps
CPU time 3.02 seconds
Started Jun 26 04:55:30 PM PDT 24
Finished Jun 26 04:55:39 PM PDT 24
Peak memory 201408 kb
Host smart-729c7f0a-3fca-4482-b021-55131646a15f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668369005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.1668369005
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.4062147614
Short name T109
Test name
Test status
Simulation time 2629318164 ps
CPU time 2.43 seconds
Started Jun 26 04:55:31 PM PDT 24
Finished Jun 26 04:55:41 PM PDT 24
Peak memory 201428 kb
Host smart-53480471-d688-48a8-b601-51fe58bfcc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062147614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.4062147614
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.3393706731
Short name T501
Test name
Test status
Simulation time 2478284605 ps
CPU time 2.44 seconds
Started Jun 26 04:55:21 PM PDT 24
Finished Jun 26 04:55:26 PM PDT 24
Peak memory 201536 kb
Host smart-b0600948-212e-45c6-bc80-5596dd54e8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393706731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.3393706731
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.1997016536
Short name T460
Test name
Test status
Simulation time 2047498195 ps
CPU time 5.96 seconds
Started Jun 26 04:55:37 PM PDT 24
Finished Jun 26 04:55:48 PM PDT 24
Peak memory 201356 kb
Host smart-17165806-a712-4eb6-999a-1ad65aa2aeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997016536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.1997016536
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.1232081089
Short name T143
Test name
Test status
Simulation time 2509799813 ps
CPU time 6.96 seconds
Started Jun 26 04:55:28 PM PDT 24
Finished Jun 26 04:55:41 PM PDT 24
Peak memory 201432 kb
Host smart-ecc928f1-e749-453e-883d-2f5e8788a8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232081089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.1232081089
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.3093949437
Short name T783
Test name
Test status
Simulation time 2120559031 ps
CPU time 2.76 seconds
Started Jun 26 04:55:31 PM PDT 24
Finished Jun 26 04:55:41 PM PDT 24
Peak memory 201368 kb
Host smart-968bf06c-3dc2-4709-a39e-a23581df3d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093949437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.3093949437
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.584462051
Short name T126
Test name
Test status
Simulation time 14138810838 ps
CPU time 28.14 seconds
Started Jun 26 04:55:29 PM PDT 24
Finished Jun 26 04:56:04 PM PDT 24
Peak memory 201468 kb
Host smart-1163b5c2-3a79-4f52-bc7e-afaf920ede84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584462051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_st
ress_all.584462051
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2471561632
Short name T475
Test name
Test status
Simulation time 6936743198 ps
CPU time 4.39 seconds
Started Jun 26 04:55:29 PM PDT 24
Finished Jun 26 04:55:40 PM PDT 24
Peak memory 201520 kb
Host smart-73584ac2-295c-4819-a383-589c315f4f87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471561632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.2471561632
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.2385430035
Short name T416
Test name
Test status
Simulation time 2029430510 ps
CPU time 1.95 seconds
Started Jun 26 04:55:32 PM PDT 24
Finished Jun 26 04:55:41 PM PDT 24
Peak memory 201416 kb
Host smart-6b52b505-2f52-4d10-92b2-5610156c6ad7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385430035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.2385430035
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.4259989589
Short name T312
Test name
Test status
Simulation time 3546442688 ps
CPU time 10.09 seconds
Started Jun 26 04:55:31 PM PDT 24
Finished Jun 26 04:55:49 PM PDT 24
Peak memory 201620 kb
Host smart-68a18811-477d-4e14-8a92-e461324f2cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259989589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.4
259989589
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.1543587625
Short name T35
Test name
Test status
Simulation time 125931188549 ps
CPU time 86.14 seconds
Started Jun 26 04:55:29 PM PDT 24
Finished Jun 26 04:57:02 PM PDT 24
Peak memory 201736 kb
Host smart-25b902d0-7e32-448f-afe1-db2f07cb2914
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543587625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_combo_detect.1543587625
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1627460788
Short name T614
Test name
Test status
Simulation time 3752365512 ps
CPU time 10.36 seconds
Started Jun 26 04:55:29 PM PDT 24
Finished Jun 26 04:55:45 PM PDT 24
Peak memory 201408 kb
Host smart-ac3c83f2-f240-452b-9850-380fbac77b3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627460788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ec_pwr_on_rst.1627460788
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.954136557
Short name T161
Test name
Test status
Simulation time 2690757871 ps
CPU time 5.85 seconds
Started Jun 26 04:55:31 PM PDT 24
Finished Jun 26 04:55:44 PM PDT 24
Peak memory 201484 kb
Host smart-4796eec4-8818-40ea-8446-f4a8254693f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954136557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctr
l_edge_detect.954136557
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.4211892925
Short name T784
Test name
Test status
Simulation time 2641696572 ps
CPU time 2.02 seconds
Started Jun 26 04:55:29 PM PDT 24
Finished Jun 26 04:55:37 PM PDT 24
Peak memory 201432 kb
Host smart-6134491a-c03d-43d4-b9b4-a67007a3e5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211892925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.4211892925
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.2328679133
Short name T635
Test name
Test status
Simulation time 2453880793 ps
CPU time 3.66 seconds
Started Jun 26 04:55:23 PM PDT 24
Finished Jun 26 04:55:31 PM PDT 24
Peak memory 201484 kb
Host smart-adbd7d78-aa73-41a9-a981-5d74fd0be698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328679133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.2328679133
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.89949235
Short name T667
Test name
Test status
Simulation time 2278591598 ps
CPU time 2.06 seconds
Started Jun 26 04:55:33 PM PDT 24
Finished Jun 26 04:55:41 PM PDT 24
Peak memory 201504 kb
Host smart-57d44873-6c41-42a2-86f6-64bd24eea9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89949235 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.89949235
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.579445448
Short name T590
Test name
Test status
Simulation time 2518249624 ps
CPU time 3.76 seconds
Started Jun 26 04:55:23 PM PDT 24
Finished Jun 26 04:55:31 PM PDT 24
Peak memory 201524 kb
Host smart-b6a88f8b-8111-4d29-9930-7bbf600c02a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579445448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.579445448
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.3806686673
Short name T793
Test name
Test status
Simulation time 2112195081 ps
CPU time 3.27 seconds
Started Jun 26 04:55:22 PM PDT 24
Finished Jun 26 04:55:29 PM PDT 24
Peak memory 201408 kb
Host smart-41debf13-a52a-48f8-bbd2-e841c0a5d248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806686673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.3806686673
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.1202462999
Short name T485
Test name
Test status
Simulation time 6621307647 ps
CPU time 16.25 seconds
Started Jun 26 04:55:29 PM PDT 24
Finished Jun 26 04:55:52 PM PDT 24
Peak memory 201464 kb
Host smart-bf7bce7d-e788-49d2-8c04-38cf99e18c1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202462999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_s
tress_all.1202462999
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.1397225943
Short name T129
Test name
Test status
Simulation time 403072222748 ps
CPU time 244.84 seconds
Started Jun 26 04:55:31 PM PDT 24
Finished Jun 26 04:59:42 PM PDT 24
Peak memory 210148 kb
Host smart-b3dbaa9a-9a46-46c9-b56c-2ad75d0fd452
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397225943 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.1397225943
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3828210067
Short name T425
Test name
Test status
Simulation time 5193150076 ps
CPU time 2.12 seconds
Started Jun 26 04:55:29 PM PDT 24
Finished Jun 26 04:55:37 PM PDT 24
Peak memory 201504 kb
Host smart-5da86eab-f123-4dc4-8d21-10070a929f74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828210067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.3828210067
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.1327593724
Short name T405
Test name
Test status
Simulation time 2009831170 ps
CPU time 6.1 seconds
Started Jun 26 04:54:02 PM PDT 24
Finished Jun 26 04:54:11 PM PDT 24
Peak memory 201528 kb
Host smart-84dcef12-d11b-4bfb-85df-c89671db50bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327593724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.1327593724
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2771801484
Short name T207
Test name
Test status
Simulation time 243919751996 ps
CPU time 61.67 seconds
Started Jun 26 04:53:56 PM PDT 24
Finished Jun 26 04:55:00 PM PDT 24
Peak memory 201636 kb
Host smart-46b64ed5-aa39-44ce-97ac-e99804726153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771801484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.2771801484
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.3279725394
Short name T53
Test name
Test status
Simulation time 1405454521797 ps
CPU time 884.46 seconds
Started Jun 26 04:53:51 PM PDT 24
Finished Jun 26 05:08:39 PM PDT 24
Peak memory 201460 kb
Host smart-2eaa58ff-a295-49aa-aa72-c981676fa5e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279725394 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ec_pwr_on_rst.3279725394
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.806099535
Short name T736
Test name
Test status
Simulation time 3486124539 ps
CPU time 9.36 seconds
Started Jun 26 04:53:49 PM PDT 24
Finished Jun 26 04:54:02 PM PDT 24
Peak memory 201524 kb
Host smart-4204ac3d-80ad-48be-ba68-fd58a040896d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806099535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl
_edge_detect.806099535
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2453261030
Short name T406
Test name
Test status
Simulation time 2610624301 ps
CPU time 7.16 seconds
Started Jun 26 04:53:45 PM PDT 24
Finished Jun 26 04:53:57 PM PDT 24
Peak memory 201432 kb
Host smart-f131887e-44ac-4789-a06b-04a6438c6f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453261030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.2453261030
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.515611749
Short name T325
Test name
Test status
Simulation time 2481183378 ps
CPU time 1.74 seconds
Started Jun 26 04:53:56 PM PDT 24
Finished Jun 26 04:54:00 PM PDT 24
Peak memory 201484 kb
Host smart-6113f14e-a5a7-4428-a649-e7f7f2a0ecc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515611749 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.515611749
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.4076578923
Short name T461
Test name
Test status
Simulation time 2232512051 ps
CPU time 3.42 seconds
Started Jun 26 04:53:56 PM PDT 24
Finished Jun 26 04:54:02 PM PDT 24
Peak memory 201516 kb
Host smart-4b2d298a-a81b-43d7-999c-1d501374137f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076578923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.4076578923
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.106517024
Short name T547
Test name
Test status
Simulation time 2533093019 ps
CPU time 2.39 seconds
Started Jun 26 04:54:03 PM PDT 24
Finished Jun 26 04:54:09 PM PDT 24
Peak memory 201528 kb
Host smart-21929389-e670-415d-a142-e172210e89f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106517024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.106517024
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.502334279
Short name T483
Test name
Test status
Simulation time 2119387640 ps
CPU time 2.28 seconds
Started Jun 26 04:53:52 PM PDT 24
Finished Jun 26 04:53:57 PM PDT 24
Peak memory 201448 kb
Host smart-ab726950-f80e-4152-a0e6-5579c2fe1e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502334279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.502334279
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.1800952826
Short name T638
Test name
Test status
Simulation time 11058229381 ps
CPU time 28.82 seconds
Started Jun 26 04:53:59 PM PDT 24
Finished Jun 26 04:54:31 PM PDT 24
Peak memory 201560 kb
Host smart-c2322d20-8629-4ce9-b554-a647705e3bb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800952826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st
ress_all.1800952826
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.4282789888
Short name T735
Test name
Test status
Simulation time 4555617142716 ps
CPU time 162.92 seconds
Started Jun 26 04:53:54 PM PDT 24
Finished Jun 26 04:56:44 PM PDT 24
Peak memory 201464 kb
Host smart-cecb0f6d-f287-49b5-b743-2fa2740af7ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282789888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.4282789888
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1528833079
Short name T97
Test name
Test status
Simulation time 65475912828 ps
CPU time 177.39 seconds
Started Jun 26 04:55:29 PM PDT 24
Finished Jun 26 04:58:38 PM PDT 24
Peak memory 201812 kb
Host smart-861a3623-1492-45d7-b9f1-fae5f60d0b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528833079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_w
ith_pre_cond.1528833079
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.2506579004
Short name T668
Test name
Test status
Simulation time 26580731936 ps
CPU time 67.62 seconds
Started Jun 26 04:55:27 PM PDT 24
Finished Jun 26 04:56:39 PM PDT 24
Peak memory 201780 kb
Host smart-7fd512c4-dfe3-48cc-aa8c-c8c4437944d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506579004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_w
ith_pre_cond.2506579004
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2068193192
Short name T231
Test name
Test status
Simulation time 153887105250 ps
CPU time 373.33 seconds
Started Jun 26 04:55:33 PM PDT 24
Finished Jun 26 05:01:53 PM PDT 24
Peak memory 201860 kb
Host smart-c33633e8-5d5e-4d69-92a6-1bc39b90a94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068193192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_w
ith_pre_cond.2068193192
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1656085557
Short name T99
Test name
Test status
Simulation time 27580992322 ps
CPU time 75.27 seconds
Started Jun 26 04:55:27 PM PDT 24
Finished Jun 26 04:56:46 PM PDT 24
Peak memory 201688 kb
Host smart-da531be0-c508-49e8-8074-b919ff177f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656085557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_w
ith_pre_cond.1656085557
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1999282721
Short name T379
Test name
Test status
Simulation time 89153434123 ps
CPU time 222.59 seconds
Started Jun 26 04:55:34 PM PDT 24
Finished Jun 26 04:59:22 PM PDT 24
Peak memory 201740 kb
Host smart-e0ffe362-de10-4791-bf8d-e0727e4fbe7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999282721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_w
ith_pre_cond.1999282721
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3422196539
Short name T682
Test name
Test status
Simulation time 25332096979 ps
CPU time 67.26 seconds
Started Jun 26 04:55:31 PM PDT 24
Finished Jun 26 04:56:45 PM PDT 24
Peak memory 201748 kb
Host smart-652e2b6c-1164-4db6-8914-c3db20857830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422196539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_w
ith_pre_cond.3422196539
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3020222429
Short name T366
Test name
Test status
Simulation time 96320103753 ps
CPU time 137.04 seconds
Started Jun 26 04:55:30 PM PDT 24
Finished Jun 26 04:57:53 PM PDT 24
Peak memory 201708 kb
Host smart-d1e11b15-8a2b-4fa5-b440-e4cf3dd14cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020222429 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_w
ith_pre_cond.3020222429
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.3993963967
Short name T408
Test name
Test status
Simulation time 2024686117 ps
CPU time 3.31 seconds
Started Jun 26 04:54:00 PM PDT 24
Finished Jun 26 04:54:07 PM PDT 24
Peak memory 201420 kb
Host smart-88f2c8e1-3771-4580-a1a8-5cb7ccfec624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993963967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_tes
t.3993963967
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.2990325820
Short name T702
Test name
Test status
Simulation time 3477134015 ps
CPU time 1.18 seconds
Started Jun 26 04:53:50 PM PDT 24
Finished Jun 26 04:53:54 PM PDT 24
Peak memory 201504 kb
Host smart-c12fd9fd-fe84-4656-8244-1ecdebe93a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990325820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.2990325820
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1809128561
Short name T608
Test name
Test status
Simulation time 31294157813 ps
CPU time 22.1 seconds
Started Jun 26 04:53:50 PM PDT 24
Finished Jun 26 04:54:16 PM PDT 24
Peak memory 201852 kb
Host smart-6f2e1c3b-924a-4107-b719-c98e0c1783f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809128561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_wi
th_pre_cond.1809128561
Directory /workspace/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2411482031
Short name T672
Test name
Test status
Simulation time 198814678189 ps
CPU time 47.36 seconds
Started Jun 26 04:53:57 PM PDT 24
Finished Jun 26 04:54:48 PM PDT 24
Peak memory 201564 kb
Host smart-95a6f3f6-7dde-4172-9584-0b3282e0a34c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411482031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.2411482031
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.1790526007
Short name T175
Test name
Test status
Simulation time 5155908667 ps
CPU time 4.41 seconds
Started Jun 26 04:53:58 PM PDT 24
Finished Jun 26 04:54:05 PM PDT 24
Peak memory 201564 kb
Host smart-aa449c96-4f1b-4b92-8295-e3ea626740e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790526007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_edge_detect.1790526007
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3401844452
Short name T334
Test name
Test status
Simulation time 2636960179 ps
CPU time 2.16 seconds
Started Jun 26 04:53:49 PM PDT 24
Finished Jun 26 04:53:55 PM PDT 24
Peak memory 201476 kb
Host smart-b687e373-6def-49d8-b4ee-ab726a6b9788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401844452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.3401844452
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.2467994744
Short name T66
Test name
Test status
Simulation time 2496324030 ps
CPU time 1.86 seconds
Started Jun 26 04:53:51 PM PDT 24
Finished Jun 26 04:53:56 PM PDT 24
Peak memory 201484 kb
Host smart-dc139c98-cd70-459d-8a4b-128ccb9931e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467994744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.2467994744
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.3200104025
Short name T274
Test name
Test status
Simulation time 2074091200 ps
CPU time 1.84 seconds
Started Jun 26 04:53:59 PM PDT 24
Finished Jun 26 04:54:04 PM PDT 24
Peak memory 201460 kb
Host smart-41162fb2-098c-48b1-8793-205fc08f9444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200104025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.3200104025
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.2689489468
Short name T655
Test name
Test status
Simulation time 2531173012 ps
CPU time 2.19 seconds
Started Jun 26 04:54:03 PM PDT 24
Finished Jun 26 04:54:08 PM PDT 24
Peak memory 201428 kb
Host smart-bc22dbf8-b37c-4efb-927e-bf7289cd6002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689489468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.2689489468
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.424934863
Short name T530
Test name
Test status
Simulation time 2114935961 ps
CPU time 3.29 seconds
Started Jun 26 04:54:00 PM PDT 24
Finished Jun 26 04:54:06 PM PDT 24
Peak memory 201448 kb
Host smart-5c6365e9-e71b-4f20-86fd-ed1593e30e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424934863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.424934863
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.460990861
Short name T141
Test name
Test status
Simulation time 13682392989 ps
CPU time 9.74 seconds
Started Jun 26 04:54:06 PM PDT 24
Finished Jun 26 04:54:19 PM PDT 24
Peak memory 201552 kb
Host smart-fadf785c-6f39-4065-b273-27cab0a7901a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460990861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_str
ess_all.460990861
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.650741446
Short name T256
Test name
Test status
Simulation time 66119677650 ps
CPU time 38.6 seconds
Started Jun 26 04:53:58 PM PDT 24
Finished Jun 26 04:54:40 PM PDT 24
Peak memory 210180 kb
Host smart-f096058f-0d36-438f-b6d1-53693d255f0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650741446 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.650741446
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.480187448
Short name T583
Test name
Test status
Simulation time 5705571049 ps
CPU time 6.59 seconds
Started Jun 26 04:54:01 PM PDT 24
Finished Jun 26 04:54:11 PM PDT 24
Peak memory 201524 kb
Host smart-d6211753-3e20-4192-89f7-f80f9ab20d9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480187448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_ultra_low_pwr.480187448
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.897817714
Short name T372
Test name
Test status
Simulation time 82990828012 ps
CPU time 206.24 seconds
Started Jun 26 04:55:27 PM PDT 24
Finished Jun 26 04:58:57 PM PDT 24
Peak memory 201788 kb
Host smart-5c3a4220-4090-48d4-adaa-f03741943972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897817714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_wi
th_pre_cond.897817714
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1983939848
Short name T96
Test name
Test status
Simulation time 25083141037 ps
CPU time 69.32 seconds
Started Jun 26 04:55:28 PM PDT 24
Finished Jun 26 04:56:44 PM PDT 24
Peak memory 201760 kb
Host smart-b336c7e1-19b1-4ada-9ebd-d49ddcfc2416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983939848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_w
ith_pre_cond.1983939848
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2655398059
Short name T698
Test name
Test status
Simulation time 71070689801 ps
CPU time 98.41 seconds
Started Jun 26 04:55:31 PM PDT 24
Finished Jun 26 04:57:16 PM PDT 24
Peak memory 201784 kb
Host smart-6305a2f0-af3d-46e2-8703-106814728cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655398059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_w
ith_pre_cond.2655398059
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.4106645340
Short name T9
Test name
Test status
Simulation time 48430403289 ps
CPU time 127.76 seconds
Started Jun 26 04:55:22 PM PDT 24
Finished Jun 26 04:57:33 PM PDT 24
Peak memory 201784 kb
Host smart-391d93d9-7b81-4966-b230-1b90e2a9d6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106645340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_w
ith_pre_cond.4106645340
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1825786633
Short name T704
Test name
Test status
Simulation time 61378214387 ps
CPU time 43.06 seconds
Started Jun 26 04:55:30 PM PDT 24
Finished Jun 26 04:56:21 PM PDT 24
Peak memory 201720 kb
Host smart-126739e9-31e5-4e5d-8993-6cee6ab39e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825786633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_w
ith_pre_cond.1825786633
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.2664638415
Short name T375
Test name
Test status
Simulation time 69244231406 ps
CPU time 48.61 seconds
Started Jun 26 04:55:49 PM PDT 24
Finished Jun 26 04:56:40 PM PDT 24
Peak memory 201868 kb
Host smart-1f2564d7-f8ee-4d09-820e-e8ed3a6bdea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664638415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_w
ith_pre_cond.2664638415
Directory /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3030496660
Short name T393
Test name
Test status
Simulation time 78415247530 ps
CPU time 191.67 seconds
Started Jun 26 04:55:48 PM PDT 24
Finished Jun 26 04:59:03 PM PDT 24
Peak memory 201832 kb
Host smart-2e250e03-1e6c-4212-bd4a-9d0ab41fc3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030496660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_w
ith_pre_cond.3030496660
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.1871388196
Short name T240
Test name
Test status
Simulation time 2019586055 ps
CPU time 3.18 seconds
Started Jun 26 04:54:03 PM PDT 24
Finished Jun 26 04:54:09 PM PDT 24
Peak memory 201508 kb
Host smart-2da03b23-14d1-45cc-89c3-ad7b12922391
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871388196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_tes
t.1871388196
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1950784886
Short name T555
Test name
Test status
Simulation time 3386187428 ps
CPU time 8.72 seconds
Started Jun 26 04:53:55 PM PDT 24
Finished Jun 26 04:54:07 PM PDT 24
Peak memory 201580 kb
Host smart-16f81b27-fac0-4944-af4b-426269c7dfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950784886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.1950784886
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.1813678462
Short name T34
Test name
Test status
Simulation time 101935378755 ps
CPU time 142.11 seconds
Started Jun 26 04:53:58 PM PDT 24
Finished Jun 26 04:56:23 PM PDT 24
Peak memory 201776 kb
Host smart-0f1acb81-3647-41e3-a397-e13bc72aa65f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813678462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_combo_detect.1813678462
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.120154287
Short name T642
Test name
Test status
Simulation time 31014122089 ps
CPU time 22.24 seconds
Started Jun 26 04:53:45 PM PDT 24
Finished Jun 26 04:54:11 PM PDT 24
Peak memory 201776 kb
Host smart-3551bcc7-edeb-4e10-b14f-2ecf7ff6f414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120154287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wit
h_pre_cond.120154287
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1805199952
Short name T701
Test name
Test status
Simulation time 5383968777 ps
CPU time 15.44 seconds
Started Jun 26 04:53:50 PM PDT 24
Finished Jun 26 04:54:09 PM PDT 24
Peak memory 201500 kb
Host smart-72868976-c5f4-4328-9344-44c263a510dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805199952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ec_pwr_on_rst.1805199952
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.3550440808
Short name T111
Test name
Test status
Simulation time 3040583271 ps
CPU time 7.94 seconds
Started Jun 26 04:54:09 PM PDT 24
Finished Jun 26 04:54:20 PM PDT 24
Peak memory 201396 kb
Host smart-cec67202-0720-4b19-9c17-23ba0fe727a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550440808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.3550440808
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.4220715018
Short name T504
Test name
Test status
Simulation time 2615952122 ps
CPU time 5.67 seconds
Started Jun 26 04:53:54 PM PDT 24
Finished Jun 26 04:54:02 PM PDT 24
Peak memory 201440 kb
Host smart-86032d83-392b-4f72-bdec-d12a75bac6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220715018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.4220715018
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.3437138223
Short name T633
Test name
Test status
Simulation time 2506676527 ps
CPU time 1.68 seconds
Started Jun 26 04:53:56 PM PDT 24
Finished Jun 26 04:54:00 PM PDT 24
Peak memory 201516 kb
Host smart-cc31f921-a9f0-4b1c-a97b-a47e308c2d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437138223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.3437138223
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1986835727
Short name T758
Test name
Test status
Simulation time 2184426581 ps
CPU time 5.99 seconds
Started Jun 26 04:53:50 PM PDT 24
Finished Jun 26 04:53:59 PM PDT 24
Peak memory 201484 kb
Host smart-d3b48d7b-bb26-4cd7-8304-877de425cd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986835727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.1986835727
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.4069246140
Short name T616
Test name
Test status
Simulation time 2532637613 ps
CPU time 2.33 seconds
Started Jun 26 04:53:58 PM PDT 24
Finished Jun 26 04:54:04 PM PDT 24
Peak memory 201528 kb
Host smart-750c3651-cd46-48e0-83fd-f529ad6c5082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069246140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.4069246140
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.1565215053
Short name T419
Test name
Test status
Simulation time 2113464558 ps
CPU time 6.12 seconds
Started Jun 26 04:53:51 PM PDT 24
Finished Jun 26 04:54:01 PM PDT 24
Peak memory 201260 kb
Host smart-06afd972-6d47-453a-aaff-98a7eae30f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565215053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.1565215053
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.2039577149
Short name T520
Test name
Test status
Simulation time 6909754171 ps
CPU time 14.88 seconds
Started Jun 26 04:53:59 PM PDT 24
Finished Jun 26 04:54:17 PM PDT 24
Peak memory 201556 kb
Host smart-ff3046df-3092-4ad1-877f-13aa3ed44d3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039577149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.2039577149
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2967141267
Short name T626
Test name
Test status
Simulation time 54564804480 ps
CPU time 71.03 seconds
Started Jun 26 04:55:35 PM PDT 24
Finished Jun 26 04:56:51 PM PDT 24
Peak memory 201900 kb
Host smart-291985e8-93af-4183-94e5-54d7639c29b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967141267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_w
ith_pre_cond.2967141267
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.3880411301
Short name T253
Test name
Test status
Simulation time 65676859679 ps
CPU time 33.59 seconds
Started Jun 26 04:55:30 PM PDT 24
Finished Jun 26 04:56:11 PM PDT 24
Peak memory 201728 kb
Host smart-b58b19de-354a-478c-9ab2-9ed42b9cbde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880411301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w
ith_pre_cond.3880411301
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2893853637
Short name T652
Test name
Test status
Simulation time 51254652800 ps
CPU time 55.73 seconds
Started Jun 26 04:55:49 PM PDT 24
Finished Jun 26 04:56:48 PM PDT 24
Peak memory 201604 kb
Host smart-293b2d75-4cfd-45c6-adad-2fc63d3379cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893853637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_w
ith_pre_cond.2893853637
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.502968503
Short name T518
Test name
Test status
Simulation time 49656303806 ps
CPU time 33.67 seconds
Started Jun 26 04:55:51 PM PDT 24
Finished Jun 26 04:56:27 PM PDT 24
Peak memory 201788 kb
Host smart-4a6d7279-b3af-4af3-9180-24b5984ebef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502968503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_wi
th_pre_cond.502968503
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3435057725
Short name T252
Test name
Test status
Simulation time 65513828297 ps
CPU time 161.9 seconds
Started Jun 26 04:55:46 PM PDT 24
Finished Jun 26 04:58:31 PM PDT 24
Peak memory 201852 kb
Host smart-500c1289-ea53-452a-8e8e-79cce60290e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435057725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_w
ith_pre_cond.3435057725
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.3087306198
Short name T790
Test name
Test status
Simulation time 65353914671 ps
CPU time 30.14 seconds
Started Jun 26 04:55:41 PM PDT 24
Finished Jun 26 04:56:14 PM PDT 24
Peak memory 201764 kb
Host smart-fd76d820-16d1-49fa-be24-72797a19fd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087306198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_w
ith_pre_cond.3087306198
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.390400160
Short name T45
Test name
Test status
Simulation time 42752744668 ps
CPU time 28.35 seconds
Started Jun 26 04:55:29 PM PDT 24
Finished Jun 26 04:56:05 PM PDT 24
Peak memory 201708 kb
Host smart-2610af8f-60a3-439a-bb67-08f22dc274ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390400160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_wi
th_pre_cond.390400160
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.3243688766
Short name T605
Test name
Test status
Simulation time 34629258198 ps
CPU time 43.24 seconds
Started Jun 26 04:55:36 PM PDT 24
Finished Jun 26 04:56:24 PM PDT 24
Peak memory 201784 kb
Host smart-cb25001c-e63c-4042-b181-eb229b2d7d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243688766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_w
ith_pre_cond.3243688766
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.114675770
Short name T381
Test name
Test status
Simulation time 70736883633 ps
CPU time 27.62 seconds
Started Jun 26 04:55:34 PM PDT 24
Finished Jun 26 04:56:08 PM PDT 24
Peak memory 201796 kb
Host smart-9e3f53b7-8f8a-4d59-985e-96ebd874eb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114675770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_wi
th_pre_cond.114675770
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.321389978
Short name T622
Test name
Test status
Simulation time 23349671107 ps
CPU time 17.4 seconds
Started Jun 26 04:55:32 PM PDT 24
Finished Jun 26 04:55:56 PM PDT 24
Peak memory 201860 kb
Host smart-a5ea23eb-6f03-4bbd-998f-1f57d62d27b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321389978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_wi
th_pre_cond.321389978
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.2886827559
Short name T271
Test name
Test status
Simulation time 2047539902 ps
CPU time 2.06 seconds
Started Jun 26 04:53:51 PM PDT 24
Finished Jun 26 04:53:56 PM PDT 24
Peak memory 201412 kb
Host smart-d945b7d0-70d6-4187-9f38-88638bbfe43c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886827559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.2886827559
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.4123666451
Short name T644
Test name
Test status
Simulation time 96032522509 ps
CPU time 263.34 seconds
Started Jun 26 04:54:05 PM PDT 24
Finished Jun 26 04:58:32 PM PDT 24
Peak memory 201552 kb
Host smart-8779abf8-c6b0-4d20-936a-f67d1de85464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123666451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.4123666451
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.327530856
Short name T521
Test name
Test status
Simulation time 176095216316 ps
CPU time 77.38 seconds
Started Jun 26 04:54:03 PM PDT 24
Finished Jun 26 04:55:24 PM PDT 24
Peak memory 201840 kb
Host smart-ec20bb85-dade-48c4-ae52-2dc333ba7869
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327530856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_combo_detect.327530856
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.800957546
Short name T426
Test name
Test status
Simulation time 2606219845 ps
CPU time 2.17 seconds
Started Jun 26 04:54:02 PM PDT 24
Finished Jun 26 04:54:07 PM PDT 24
Peak memory 201412 kb
Host smart-4075a9d6-5bd7-4d1e-bdcb-aadf1399fa26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800957546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_ec_pwr_on_rst.800957546
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.3337457921
Short name T142
Test name
Test status
Simulation time 3951214812 ps
CPU time 2.11 seconds
Started Jun 26 04:54:13 PM PDT 24
Finished Jun 26 04:54:17 PM PDT 24
Peak memory 201736 kb
Host smart-64564fd6-462c-434b-b700-9a4cefd0f792
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337457921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_edge_detect.3337457921
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.4024940941
Short name T548
Test name
Test status
Simulation time 2614778585 ps
CPU time 7.18 seconds
Started Jun 26 04:53:57 PM PDT 24
Finished Jun 26 04:54:07 PM PDT 24
Peak memory 201508 kb
Host smart-e3a7f0cb-0362-46b0-a225-dca1d025c72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024940941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.4024940941
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2965372741
Short name T687
Test name
Test status
Simulation time 2569783166 ps
CPU time 1.19 seconds
Started Jun 26 04:53:51 PM PDT 24
Finished Jun 26 04:53:55 PM PDT 24
Peak memory 201432 kb
Host smart-1c962887-26df-4d26-817a-4d04582f1f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965372741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.2965372741
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3264499964
Short name T658
Test name
Test status
Simulation time 2109419307 ps
CPU time 1.77 seconds
Started Jun 26 04:54:01 PM PDT 24
Finished Jun 26 04:54:06 PM PDT 24
Peak memory 201372 kb
Host smart-69d63cca-55a9-4294-b03b-d6ac2bb5bdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264499964 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.3264499964
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.1283215837
Short name T119
Test name
Test status
Simulation time 2517122531 ps
CPU time 3.9 seconds
Started Jun 26 04:54:06 PM PDT 24
Finished Jun 26 04:54:13 PM PDT 24
Peak memory 201480 kb
Host smart-a0cf7b0f-1293-4a6f-bac2-852084c7f2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283215837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.1283215837
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.3116144779
Short name T187
Test name
Test status
Simulation time 2151303164 ps
CPU time 1.64 seconds
Started Jun 26 04:54:03 PM PDT 24
Finished Jun 26 04:54:08 PM PDT 24
Peak memory 201432 kb
Host smart-f6583800-fc6f-409e-8049-e6df794b03a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116144779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.3116144779
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.2475737052
Short name T212
Test name
Test status
Simulation time 7304243035 ps
CPU time 19.86 seconds
Started Jun 26 04:54:02 PM PDT 24
Finished Jun 26 04:54:25 PM PDT 24
Peak memory 201508 kb
Host smart-373becf9-8abd-4535-8d21-0fa87bc14ad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475737052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_st
ress_all.2475737052
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3554005493
Short name T41
Test name
Test status
Simulation time 22146093486 ps
CPU time 49.58 seconds
Started Jun 26 04:54:03 PM PDT 24
Finished Jun 26 04:54:56 PM PDT 24
Peak memory 210120 kb
Host smart-ec6e7ad3-d5f0-47e0-944b-3f3ddffc3a51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554005493 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.3554005493
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.372419511
Short name T76
Test name
Test status
Simulation time 1337697065547 ps
CPU time 53.04 seconds
Started Jun 26 04:54:03 PM PDT 24
Finished Jun 26 04:55:00 PM PDT 24
Peak memory 201504 kb
Host smart-6f661ee9-abd1-4243-ad4d-c1bf87bd0307
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372419511 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_ultra_low_pwr.372419511
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2026885788
Short name T399
Test name
Test status
Simulation time 67001576274 ps
CPU time 167.61 seconds
Started Jun 26 04:55:34 PM PDT 24
Finished Jun 26 04:58:27 PM PDT 24
Peak memory 201840 kb
Host smart-9c8c38da-9fe9-4022-986f-b0e5e6e00f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026885788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_w
ith_pre_cond.2026885788
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.4229972233
Short name T247
Test name
Test status
Simulation time 22581159801 ps
CPU time 62.22 seconds
Started Jun 26 04:55:47 PM PDT 24
Finished Jun 26 04:56:53 PM PDT 24
Peak memory 201760 kb
Host smart-85dbe3c1-aeb6-4796-b708-a5c50303e1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229972233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_w
ith_pre_cond.4229972233
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.130069095
Short name T251
Test name
Test status
Simulation time 51017231140 ps
CPU time 120.35 seconds
Started Jun 26 04:55:54 PM PDT 24
Finished Jun 26 04:57:57 PM PDT 24
Peak memory 201764 kb
Host smart-cbba7a50-bae1-419a-b1be-6c83cac012f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130069095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_wi
th_pre_cond.130069095
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.3766878583
Short name T711
Test name
Test status
Simulation time 87601237255 ps
CPU time 104.61 seconds
Started Jun 26 04:55:34 PM PDT 24
Finished Jun 26 04:57:27 PM PDT 24
Peak memory 201864 kb
Host smart-4a4aa1a8-1b81-46ee-b865-e84ec97c689d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766878583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_w
ith_pre_cond.3766878583
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1335780624
Short name T564
Test name
Test status
Simulation time 47335760499 ps
CPU time 31.48 seconds
Started Jun 26 04:55:34 PM PDT 24
Finished Jun 26 04:56:12 PM PDT 24
Peak memory 201768 kb
Host smart-f9c029e7-eb86-44f0-bd13-bd329443e704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335780624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_w
ith_pre_cond.1335780624
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.4280547145
Short name T249
Test name
Test status
Simulation time 51533030625 ps
CPU time 130.6 seconds
Started Jun 26 04:55:33 PM PDT 24
Finished Jun 26 04:57:50 PM PDT 24
Peak memory 201824 kb
Host smart-d733e26c-d4c7-4f07-96da-dcd4c41f560d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280547145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_w
ith_pre_cond.4280547145
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2174122577
Short name T365
Test name
Test status
Simulation time 66702119737 ps
CPU time 18.54 seconds
Started Jun 26 04:55:42 PM PDT 24
Finished Jun 26 04:56:02 PM PDT 24
Peak memory 201776 kb
Host smart-1fb6c390-6aa4-4705-9bb1-80177de1cf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174122577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_w
ith_pre_cond.2174122577
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1557720364
Short name T275
Test name
Test status
Simulation time 37625911200 ps
CPU time 18.4 seconds
Started Jun 26 04:55:32 PM PDT 24
Finished Jun 26 04:55:57 PM PDT 24
Peak memory 201768 kb
Host smart-7ca8aeae-424a-4dbc-9509-9f3024713591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557720364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.1557720364
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.3008897930
Short name T707
Test name
Test status
Simulation time 2019767173 ps
CPU time 3.36 seconds
Started Jun 26 04:53:53 PM PDT 24
Finished Jun 26 04:53:59 PM PDT 24
Peak memory 201720 kb
Host smart-02b3ad56-2a19-4ae6-a51e-fd3f63b6c5c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008897930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_tes
t.3008897930
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.348481068
Short name T235
Test name
Test status
Simulation time 3827297300 ps
CPU time 5.85 seconds
Started Jun 26 04:53:51 PM PDT 24
Finished Jun 26 04:54:00 PM PDT 24
Peak memory 201492 kb
Host smart-98a5b43a-fccf-44d8-8f21-d77844fcbac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348481068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.348481068
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.335156369
Short name T267
Test name
Test status
Simulation time 126256656902 ps
CPU time 27.78 seconds
Started Jun 26 04:53:56 PM PDT 24
Finished Jun 26 04:54:27 PM PDT 24
Peak memory 201728 kb
Host smart-818c9271-dd2d-40e9-a69d-2c6ca7f2235c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335156369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_combo_detect.335156369
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3250942951
Short name T276
Test name
Test status
Simulation time 68669647467 ps
CPU time 42.89 seconds
Started Jun 26 04:54:08 PM PDT 24
Finished Jun 26 04:54:53 PM PDT 24
Peak memory 201812 kb
Host smart-cc5407b0-e89d-4357-b799-f3075d4e7945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250942951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wi
th_pre_cond.3250942951
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3618095181
Short name T333
Test name
Test status
Simulation time 2690209304 ps
CPU time 7.58 seconds
Started Jun 26 04:54:01 PM PDT 24
Finished Jun 26 04:54:11 PM PDT 24
Peak memory 201480 kb
Host smart-5525e095-c9f3-45ae-82f0-8654da6f8f51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618095181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ec_pwr_on_rst.3618095181
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.1142119941
Short name T152
Test name
Test status
Simulation time 2779804398 ps
CPU time 6.6 seconds
Started Jun 26 04:53:57 PM PDT 24
Finished Jun 26 04:54:06 PM PDT 24
Peak memory 201496 kb
Host smart-e582c81d-3dc3-4c64-87fc-c67aebf4b6a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142119941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.1142119941
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.601046039
Short name T458
Test name
Test status
Simulation time 2645299276 ps
CPU time 1.95 seconds
Started Jun 26 04:54:00 PM PDT 24
Finished Jun 26 04:54:05 PM PDT 24
Peak memory 201432 kb
Host smart-ea4e43e4-70d8-4798-89f3-d410774e29ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601046039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.601046039
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.293690270
Short name T569
Test name
Test status
Simulation time 2507415887 ps
CPU time 1.67 seconds
Started Jun 26 04:54:01 PM PDT 24
Finished Jun 26 04:54:06 PM PDT 24
Peak memory 201524 kb
Host smart-570c6802-2203-4c6f-8779-7b94651dcecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293690270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.293690270
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.1511732634
Short name T192
Test name
Test status
Simulation time 2113059831 ps
CPU time 2.02 seconds
Started Jun 26 04:54:08 PM PDT 24
Finished Jun 26 04:54:12 PM PDT 24
Peak memory 201364 kb
Host smart-86f860d3-4191-48bc-8665-8feb71ac315a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511732634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.1511732634
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3004825465
Short name T750
Test name
Test status
Simulation time 2514069236 ps
CPU time 6.05 seconds
Started Jun 26 04:53:52 PM PDT 24
Finished Jun 26 04:54:01 PM PDT 24
Peak memory 201340 kb
Host smart-24b80e27-6c4c-4317-8b4f-bb7bd0674786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004825465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.3004825465
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.4191857802
Short name T169
Test name
Test status
Simulation time 2190300978 ps
CPU time 1.13 seconds
Started Jun 26 04:53:59 PM PDT 24
Finished Jun 26 04:54:03 PM PDT 24
Peak memory 201484 kb
Host smart-10a4a8b7-54f3-42f8-ac43-b4b0524c4643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191857802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.4191857802
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2962743014
Short name T315
Test name
Test status
Simulation time 21459721508 ps
CPU time 56.83 seconds
Started Jun 26 04:54:02 PM PDT 24
Finished Jun 26 04:55:02 PM PDT 24
Peak memory 201684 kb
Host smart-511a6f8c-9a5e-402f-b00f-5437236b61e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962743014 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.2962743014
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.289810008
Short name T579
Test name
Test status
Simulation time 7624526069 ps
CPU time 2.18 seconds
Started Jun 26 04:53:50 PM PDT 24
Finished Jun 26 04:53:55 PM PDT 24
Peak memory 201556 kb
Host smart-fdfefe2e-ea0c-43bc-8abe-8936c5010f2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289810008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_ultra_low_pwr.289810008
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2180613991
Short name T44
Test name
Test status
Simulation time 57736335482 ps
CPU time 40.67 seconds
Started Jun 26 04:55:45 PM PDT 24
Finished Jun 26 04:56:28 PM PDT 24
Peak memory 201848 kb
Host smart-916ddf32-c88f-4a9d-8eee-61ba67309b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180613991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.2180613991
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.4039535891
Short name T120
Test name
Test status
Simulation time 32835318668 ps
CPU time 88.19 seconds
Started Jun 26 04:55:36 PM PDT 24
Finished Jun 26 04:57:09 PM PDT 24
Peak memory 201804 kb
Host smart-19ba0c53-f6b8-4895-be32-393ac28b491e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039535891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_w
ith_pre_cond.4039535891
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1358016686
Short name T695
Test name
Test status
Simulation time 70666956625 ps
CPU time 50.31 seconds
Started Jun 26 04:55:35 PM PDT 24
Finished Jun 26 04:56:31 PM PDT 24
Peak memory 201712 kb
Host smart-c7918841-32bd-4982-980c-7891f63af701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358016686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_w
ith_pre_cond.1358016686
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.473100325
Short name T721
Test name
Test status
Simulation time 113152526044 ps
CPU time 282.65 seconds
Started Jun 26 04:55:34 PM PDT 24
Finished Jun 26 05:00:22 PM PDT 24
Peak memory 201856 kb
Host smart-a24e022c-27d1-4d2a-9f0e-160902e37288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473100325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_wi
th_pre_cond.473100325
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.927744277
Short name T364
Test name
Test status
Simulation time 77832262691 ps
CPU time 30.96 seconds
Started Jun 26 04:55:31 PM PDT 24
Finished Jun 26 04:56:09 PM PDT 24
Peak memory 201796 kb
Host smart-c1157d45-d77c-46b2-a9e4-89946dde6f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927744277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_wi
th_pre_cond.927744277
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3953858089
Short name T584
Test name
Test status
Simulation time 27085144473 ps
CPU time 33.85 seconds
Started Jun 26 04:55:36 PM PDT 24
Finished Jun 26 04:56:15 PM PDT 24
Peak memory 201740 kb
Host smart-0ec505f2-4d28-4337-b9c4-a93c4ee98fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953858089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_w
ith_pre_cond.3953858089
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1569398085
Short name T718
Test name
Test status
Simulation time 53292694433 ps
CPU time 70.49 seconds
Started Jun 26 04:55:57 PM PDT 24
Finished Jun 26 04:57:16 PM PDT 24
Peak memory 201888 kb
Host smart-6baf08fb-321c-4325-b88b-ccf278e3fe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569398085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.1569398085
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.2518359622
Short name T146
Test name
Test status
Simulation time 57764529479 ps
CPU time 72.01 seconds
Started Jun 26 04:55:30 PM PDT 24
Finished Jun 26 04:56:49 PM PDT 24
Peak memory 201776 kb
Host smart-ab197e32-7a07-48f1-8bc9-23ead55efe0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518359622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_w
ith_pre_cond.2518359622
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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