SYSRST_CTRL Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: `be1c4a4f52`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.210s	2.111ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	7.890s	2.472ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	3.510s	2.222ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	7.760s	2.531ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	15.170s	6.012ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.150s	2.066ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	4.139m	53.947ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	9.580s	3.196ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.610s	2.120ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.150s	2.066ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	9.580s	3.196ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	7.331m	172.457ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	6.222m	153.887ms	93	100	93.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	4.389m	96.033ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	50.561m	1.204s	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.520s	2.511ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.820s	2.201ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	14.741m	1.405s	50	50	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	7.510s	2.613ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	5.430m	2.722s	47	50	94.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.395m	30.810ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	18.015m	686.303ms	47	50	94.00
V2	alert_test	sysrst_ctrl_alert_test	6.200s	2.012ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	5.990s	2.012ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	7.260s	2.065ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	7.260s	2.065ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	15.170s	6.012ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.150s	2.066ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	9.580s	3.196ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	35.230s	10.219ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	15.170s	6.012ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.150s	2.066ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	9.580s	3.196ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	35.230s	10.219ms	20	20	100.00
V2		TOTAL			679	692	98.12
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.765m	42.012ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.939m	42.373ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.939m	42.373ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	7.278m	980.229ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			916	932	98.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.74	99.31	96.36	100.00	96.79	98.74	99.52	93.49

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 7 failures:

Test sysrst_ctrl_ultra_low_pwr has 3 failures.

7.sysrst_ctrl_ultra_low_pwr.11590630355396166534414955008767212833606009269243170265375853059022778800193
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2315534165 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 2563034165 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 5323034165 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 5334785269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.sysrst_ctrl_ultra_low_pwr.101024796070839972512552429850747496505416015882080200953374612600866681258230
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2189330964 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 2346830964 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
  UVM_INFO @ 3626830964 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 7811830964 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 7823258865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 1 more failures.

Test sysrst_ctrl_stress_all has 3 failures.

9.sysrst_ctrl_stress_all.32085426325856748460799501987951869256437720795777239765702643866258428621785
Line 559, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 4481448072 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 651678948072 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 651678948072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.sysrst_ctrl_stress_all.113113264382716598782726118031514492739491128564084877522369913825747958130031
Line 559, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 4232514241 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 55190014241 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 237270014241 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 237296108833 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_pin_access_vseq
  UVM_INFO @ 239295428833 ps: (sysrst_ctrl_pin_access_vseq.sv:17) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Starting the body from pin_access_vseq

... and 1 more failures.

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

27.sysrst_ctrl_stress_all_with_rand_reset.66858942845462218188946017818256568838266868169638386978883839702044829616343
Line 666, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 64337751804 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 64560251804 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 121450251804 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 121479827427 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_combo_detect_ec_rst_vseq
  UVM_INFO @ 123475301724 ps: (sysrst_ctrl_combo_detect_ec_rst_vseq.sv:44) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_ec_rst_vseq] Starting the body from combo detect ec_rst

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 3 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 3 failures.

8.sysrst_ctrl_combo_detect_with_pre_cond.53890326540054738595666539869034647162741796621262210417851644690004991000899
Line 590, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 57503831799 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 57503831799 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 57503831799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.sysrst_ctrl_combo_detect_with_pre_cond.108753859513883196367827372630589125519513339500168531306235142253463035577743
Line 583, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 27731779823 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 27826779823 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == 1) Unexpected L2H transition of ec_rst_l_o
  UVM_INFO @ 27826779823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

3.sysrst_ctrl_combo_detect_with_pre_cond.99362649384260746437227015057559935830848589935833395376064906911747699755576
Line 579, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 26085117778 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 26150117778 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 26170117778 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_ERROR @ 26315168060 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 4 [0x4])
  UVM_INFO @ 26315168060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(5) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

19.sysrst_ctrl_combo_detect_with_pre_cond.63972266821277184958158120026944135164580705384821203408550311379876602168311
Line 566, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 13448125804 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(5) +/-4
  UVM_ERROR @ 13448125804 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(5) +/-4
  UVM_INFO @ 13448125804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == *) Unexpected L2H transition of ec_rst_l_o has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

22.sysrst_ctrl_combo_detect_with_pre_cond.9316944737279200104411732904558369878039843610120559463938879932552211718889
Line 586, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 25311425232 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == 1) Unexpected L2H transition of ec_rst_l_o
  UVM_INFO @ 25386425232 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 25406425232 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_ERROR @ 25506499411 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (1 [0x1] vs 5 [0x5])
  UVM_INFO @ 25506499411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:116) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key0_out_value == cfg.vif.key0_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

33.sysrst_ctrl_stress_all_with_rand_reset.8645822119349692644891229815246126981298771938317572235404208690731566374502
Line 569, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13742317934 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:116) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key0_out_value == cfg.vif.key0_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 13843070696 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 9c24
  UVM_INFO @ 30568271906 ps: (cip_base_vseq.sv:756) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 30598271906 ps: (cip_base_vseq.sv:763) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:115) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

48.sysrst_ctrl_stress_all_with_rand_reset.113291897777686767934194004593932256533061339635646092169656771067720628760782
Line 621, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 31472818347 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 31480910192 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_pin_access_vseq
  UVM_INFO @ 31498712183 ps: (cip_base_vseq.sv:763) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 6/10
  UVM_INFO @ 31499442035 ps: (dv_base_reg.sv:325) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

52.sysrst_ctrl_combo_detect_with_pre_cond.60075947018403044310109877853831339138502367890785834125180892347536327710186
Line 619, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/52.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 75934304683 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 86220940325 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x29
  UVM_INFO @ 86221017249 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x25
  UVM_INFO @ 86669791865 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3
  UVM_INFO @ 86684304683 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 1d