Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1440

1

T1

14

T3

3

T4

11

auto[1]

1842

1

T3

14

T4

16

T19

13

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2766

1

T1

14

T3

17

T4

26

auto[1]

516

1

T4

1

T8

4

T40

3

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3111

1

T1

14

T3

17

T4

27

auto[1]

171

1

T25

16

T26

2

T27

1

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3117

1

T1

14

T3

17

T4

24

auto[1]

165

1

T4

3

T11

1

T24

2

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3105

1

T1

13

T3

14

T4

23

auto[1]

177

1

T1

1

T3

3

T4

4

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2187

1

T1

5

T3

17

T4

20

auto[1]

1095

1

T1

9

T4

7

T8

21

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1350

1

T1

3

T3

1

T4

27

auto[1]

1932

1

T1

11

T3

16

T19

6

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1279

1

T1

1

T3

17

T4

15

auto[1]

2003

1

T1

13

T4

12

T19

8

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1451

1

T1

1

T3

17

T4

21

auto[1]

1831

1

T1

13

T4

6

T19

6

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1363

1

T1

2

T3

4

T4

11

auto[1]

1919

1

T1

12

T3

13

T4

16

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

48

1

T3

1

T40

2

T24

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

11

1

T26

1

T348

1

T316

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

48

1

T4

2

T19

3

T20

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T26

1

T132

1

T282

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

45

1

T4

2

T19

2

T74

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

13

1

T26

1

T27

1

T132

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

62

1

T4

5

T19

1

T11

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T4

1

T349

1

T80

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

66

1

T1

1

T4

4

T40

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T27

2

T282

1

T348

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

38

1

T40

1

T74

1

T93

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T26

2

T282

1

T195

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

58

1

T20

2

T74

1

T93

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

11

1

T26

1

T27

1

T348

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

50

1

T19

1

T10

1

T93

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

18

1

T132

1

T63

1

T316

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

76

1

T1

1

T4

2

T19

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

13

1

T27

1

T282

2

T348

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T4

1

T19

1

T20

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

10

1

T24

1

T282

1

T349

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

42

1

T4

1

T19

2

T74

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

15

1

T8

2

T282

1

T349

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

49

1

T4

2

T40

1

T74

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T4

4

T27

1

T244

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T4

1

T20

2

T52

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T4

1

T26

1

T27

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

44

1

T19

1

T20

1

T52

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T27

2

T63

8

T80

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

43

1

T1

1

T20

3

T40

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

28

1

T8

1

T27

1

T244

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

71

1

T19

1

T24

1

T94

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

46

1

T348

1

T316

1

T80

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

52

1

T3

1

T19

1

T11

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

13

1

T282

1

T348

1

T316

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

53

1

T3

2

T11

3

T74

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

13

1

T26

1

T27

2

T217

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T3

1

T11

1

T40

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T8

1

T348

2

T349

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

56

1

T3

12

T19

2

T20

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

15

1

T26

3

T348

1

T316

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

35

1

T27

1

T77

1

T280

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T282

1

T348

1

T122

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

44

1

T19

1

T24

1

T52

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T8

2

T26

1

T282

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

40

1

T40

1

T74

1

T76

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

30

1

T27

1

T122

2

T316

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

76

1

T19

1

T40

1

T37

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

38

1

T8

1

T27

1

T132

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

71

1

T20

2

T24

1

T74

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

12

1

T8

1

T349

1

T80

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

70

1

T20

1

T40

1

T24

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T122

1

T349

1

T316

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

73

1

T52

1

T74

1

T94

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T8

3

T27

1

T122

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

96

1

T20

1

T11

6

T24

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

63

1

T8

3

T24

3

T26

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

65

1

T10

1

T52

1

T33

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T8

1

T132

3

T282

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

59

1

T19

1

T20

1

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

45

1

T8

1

T24

4

T26

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

78

1

T1

2

T93

1

T76

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

71

1

T1

9

T132

1

T348

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

257

1

T20

2

T40

4

T52

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

15

1

T8

1

T132

1

T282

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

6

1

T122

1

T80

1

T221

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T132

1

T321

1

T195

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T349

1

T140

1

T350

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T4

1

T316

1

T321

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

5

1

T349

2

T224

1

T100

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T27

1

T321

1

T195

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T132

1

T326

1

T100

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T80

1

T321

1

T221

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T132

1

T321

1

T326

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

3

1

T321

1

T140

1

T350

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T26

1

T321

1

T100

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T282

1

T244

2

T277

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

4

1

T282

1

T321

1

T351

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T80

1

T321

1

T326

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T282

1

T122

1

T349

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T24

1

T26

2

T348

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T321

2

T140

3

T350

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T132

1

T282

1

T348

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T80

2

T100

1

T352

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T352

2

T353

4

T354

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

3

1

T132

1

T122

1

T326

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T276

1

T100

2

T355

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T26

1

T132

1

T80

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T8

1

T122

1

T355

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

5

1

T356

1

T194

1

T326

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

9

1

T27

1

T132

2

T356

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

10

1

T326

1

T253

1

T277

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13

1

T348

1

T349

1

T326

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

11

1

T27

1

T348

1

T122

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T282

1

T100

1

T357

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T8

1

T132

1

T348

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

121

1

T8

2

T132

11

T282

5

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	29	67	69.79	29
Automatically Generated Cross Bins	96	29	67	69.79	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

52

1

T3

1

T40

2

T24

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T26

1

T348

1

T122

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

50

1

T4

2

T19

3

T20

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T26

1

T132

2

T282

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T4

2

T19

2

T74

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T26

1

T27

1

T132

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

64

1

T4

5

T19

1

T11

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T4

2

T349

1

T316

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

72

1

T1

1

T4

4

T40

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T27

2

T282

1

T348

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

45

1

T40

1

T52

1

T74

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

20

1

T26

2

T27

1

T282

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

60

1

T20

2

T74

1

T93

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T26

1

T27

1

T132

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

47

1

T19

1

T10

1

T93

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

24

1

T132

1

T63

1

T316

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

77

1

T1

1

T4

2

T19

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T27

1

T132

1

T282

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

63

1

T4

1

T19

1

T20

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

13

1

T24

1

T282

1

T349

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

42

1

T4

1

T19

2

T74

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T8

2

T26

1

T282

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

49

1

T4

2

T40

1

T74

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

50

1

T4

4

T27

1

T282

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

54

1

T4

1

T20

2

T52

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T4

1

T26

1

T27

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

48

1

T19

1

T20

1

T52

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

41

1

T27

2

T63

8

T80

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T1

1

T20

3

T40

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

42

1

T8

1

T27

1

T282

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

74

1

T19

1

T24

1

T94

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

55

1

T24

1

T26

2

T348

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

55

1

T3

1

T19

1

T11

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T282

1

T348

1

T316

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

63

1

T3

2

T11

3

T74

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

18

1

T26

1

T27

2

T132

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

56

1

T3

1

T11

1

T40

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T8

1

T348

2

T349

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

54

1

T3

12

T19

2

T20

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

19

1

T26

3

T348

1

T316

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

44

1

T52

1

T27

1

T76

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T132

1

T282

1

T348

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

45

1

T19

1

T24

1

T52

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T8

2

T26

1

T282

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

44

1

T40

2

T74

1

T76

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

38

1

T26

1

T27

1

T132

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

78

1

T19

1

T40

1

T25

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

43

1

T8

2

T27

1

T132

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

79

1

T20

2

T24

1

T74

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T8

1

T349

1

T356

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

76

1

T20

1

T40

1

T24

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

29

1

T27

1

T132

2

T122

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

78

1

T52

1

T74

1

T94

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

33

1

T8

3

T27

1

T122

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

98

1

T20

1

T11

6

T24

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

76

1

T8

3

T24

3

T26

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

70

1

T10

1

T52

1

T33

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T8

1

T27

1

T132

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

54

1

T19

1

T20

1

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

49

1

T8

1

T24

4

T26

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

81

1

T1

2

T93

1

T25

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

79

1

T1

9

T8

1

T132

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

168

1

T20

2

T40

5

T52

7

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

120

1

T8

3

T132

12

T282

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T358

2

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

3

1

T353

3

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

16

1

T348

1

T316

3

T321

2

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	30	66	68.75	30
Automatically Generated Cross Bins	96	30	66	68.75	30
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

52

1

T3

1

T40

2

T24

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T26

1

T348

1

T122

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

50

1

T4

2

T19

3

T20

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

19

1

T26

1

T132

2

T282

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T4

2

T19

2

T74

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T26

1

T27

1

T132

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

62

1

T4

3

T19

1

T11

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T4

2

T349

1

T316

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

73

1

T1

1

T4

3

T40

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T27

2

T282

1

T348

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

45

1

T40

1

T52

1

T74

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

20

1

T26

2

T27

1

T282

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

60

1

T20

2

T74

1

T93

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T26

1

T27

1

T132

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

49

1

T19

1

T10

1

T93

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

26

1

T132

1

T63

1

T316

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

80

1

T1

1

T4

2

T19

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T27

1

T132

1

T282

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

63

1

T4

1

T19

1

T20

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

13

1

T24

1

T282

1

T349

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

43

1

T4

1

T19

2

T74

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T8

2

T26

1

T282

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

51

1

T4

2

T40

1

T74

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

50

1

T4

4

T27

1

T282

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

54

1

T4

1

T20

2

T52

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T4

1

T26

1

T27

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

49

1

T19

1

T20

1

T52

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

41

1

T27

2

T63

8

T80

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T1

1

T20

3

T40

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

42

1

T8

1

T27

1

T282

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

74

1

T19

1

T24

1

T94

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

55

1

T24

1

T26

2

T348

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

56

1

T3

1

T19

1

T11

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T282

1

T348

1

T316

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

61

1

T3

2

T11

3

T74

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

18

1

T26

1

T27

2

T132

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

54

1

T3

1

T11

1

T40

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T8

1

T348

2

T349

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

54

1

T3

12

T19

2

T20

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

22

1

T26

3

T348

1

T316

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

44

1

T52

1

T27

1

T76

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T132

1

T282

1

T348

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

42

1

T19

1

T24

1

T52

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T8

2

T26

1

T282

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

47

1

T40

2

T74

1

T76

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

38

1

T26

1

T27

1

T132

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

75

1

T19

1

T40

1

T25

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

43

1

T8

2

T27

1

T132

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

74

1

T20

2

T24

1

T74

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T8

1

T349

1

T356

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

70

1

T20

1

T40

1

T74

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

29

1

T27

1

T132

2

T122

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

77

1

T52

1

T74

1

T94

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

33

1

T8

3

T27

1

T122

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

104

1

T20

1

T11

6

T24

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

76

1

T8

3

T24

3

T26

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

72

1

T10

1

T52

1

T33

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T8

1

T27

1

T132

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

63

1

T19

1

T20

1

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

49

1

T8

1

T24

4

T26

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

81

1

T1

2

T93

1

T25

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

79

1

T1

9

T8

1

T132

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

158

1

T20

2

T40

5

T52

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

126

1

T8

3

T132

12

T282

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T195

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

10

1

T326

2

T355

3

T112

1

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	29	67	69.79	29
Automatically Generated Cross Bins	96	29	67	69.79	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo3

Element holes

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo3_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

52

1

T3

1

T40

2

T24

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T26

1

T348

1

T122

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

50

1

T4

2

T19

3

T20

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T26

1

T132

2

T282

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T4

2

T19

2

T74

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T26

1

T27

1

T132

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

61

1

T4

3

T19

1

T11

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T4

2

T349

1

T316

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

75

1

T1

1

T4

4

T40

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T27

2

T282

1

T348

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

45

1

T40

1

T52

1

T74

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

20

1

T26

2

T27

1

T282

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

60

1

T20

2

T74

1

T93

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T26

1

T27

1

T132

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

51

1

T19

1

T10

1

T93

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

26

1

T132

1

T63

1

T316

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

76

1

T1

1

T4

2

T19

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T27

1

T132

1

T282

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

64

1

T4

1

T19

1

T20

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

13

1

T24

1

T282

1

T349

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

43

1

T4

1

T19

2

T74

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T8

2

T26

1

T282

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

47

1

T40

1

T74

2

T94

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

50

1

T4

4

T27

1

T282

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

53

1

T4

1

T20

2

T52

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T4

1

T26

1

T27

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

51

1

T19

1

T20

1

T52

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

41

1

T27

2

T63

8

T80

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

44

1

T1

1

T20

3

T40

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

41

1

T8

1

T27

1

T282

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

67

1

T19

1

T24

1

T94

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

55

1

T24

1

T26

2

T348

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

56

1

T3

1

T19

1

T11

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T282

1

T348

1

T316

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

59

1

T3

2

T11

3

T74

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

18

1

T26

1

T27

2

T132

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

56

1

T3

1

T11

1

T40

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

25

1

T8

1

T348

2

T349

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

54

1

T3

9

T19

2

T20

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

22

1

T26

3

T348

1

T316

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

44

1

T52

1

T27

1

T76

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T132

1

T282

1

T348

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

44

1

T19

1

T24

1

T52

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T8

2

T26

1

T282

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T40

2

T74

1

T76

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

38

1

T26

1

T27

1

T132

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

75

1

T19

1

T40

1

T25

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

43

1

T8

2

T27

1

T132

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

65

1

T20

2

T24

1

T74

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T8

1

T349

1

T356

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

72

1

T20

1

T40

1

T24

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

29

1

T27

1

T132

2

T122

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

80

1

T52

1

T74

1

T94

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

33

1

T8

3

T27

1

T122

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

98

1

T20

1

T11

6

T24

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

76

1

T8

3

T24

3

T26

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

63

1

T10

1

T52

1

T33

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T8

1

T27

1

T132

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

61

1

T19

1

T20

1

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

49

1

T8

1

T24

4

T26

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

69

1

T1

1

T93

1

T25

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

79

1

T1

9

T8

1

T132

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

199

1

T20

2

T40

2

T52

7

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

119

1

T8

3

T132

12

T282

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T358

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

2

1

T352

2

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

17

1

T348

1

T316

3

T321

6

User Defined Cross Bins for cross_combo3

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded