Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.17 99.37 96.78 100.00 97.44 98.82 99.61 88.20


Total tests in report: 922
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
57.55 57.55 75.29 75.29 63.78 63.78 84.93 84.93 13.46 13.46 77.01 77.01 61.66 61.66 26.70 26.70 /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.3855705119
78.83 21.28 91.64 16.35 82.74 18.96 90.64 5.71 79.49 66.03 91.90 14.90 85.84 24.18 29.53 2.84 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.1667516558
85.52 6.69 97.24 5.60 90.93 8.19 97.03 6.39 81.41 1.92 96.93 5.03 91.62 5.78 43.47 13.93 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3355625408
87.63 2.12 97.26 0.02 91.25 0.33 97.49 0.46 82.05 0.64 97.01 0.07 92.29 0.67 56.08 12.61 /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.1710375390
88.96 1.32 97.54 0.28 92.52 1.26 97.49 0.00 82.05 0.00 97.01 0.00 92.97 0.67 63.12 7.04 /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.342412694
90.21 1.26 98.06 0.52 92.59 0.08 97.49 0.00 89.74 7.69 97.52 0.52 92.97 0.00 63.12 0.00 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.3288020929
91.23 1.01 98.08 0.02 93.02 0.43 98.17 0.68 89.74 0.00 97.56 0.04 92.97 0.00 69.05 5.93 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.1059646228
92.07 0.85 98.19 0.11 93.38 0.35 98.17 0.00 89.74 0.00 97.60 0.04 94.89 1.93 72.54 3.50 /workspace/coverage/default/35.sysrst_ctrl_combo_detect.1185792554
92.59 0.51 98.25 0.06 93.40 0.03 98.17 0.00 90.38 0.64 97.67 0.07 95.57 0.67 74.67 2.13 /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.241027080
93.03 0.44 98.32 0.07 93.45 0.05 98.17 0.00 90.38 0.00 97.67 0.00 95.86 0.29 77.36 2.68 /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3610885369
93.41 0.38 98.41 0.09 93.55 0.10 98.17 0.00 91.67 1.28 97.78 0.11 96.15 0.29 78.17 0.81 /workspace/coverage/default/35.sysrst_ctrl_stress_all.1020942542
93.74 0.33 98.49 0.07 93.66 0.10 98.17 0.00 92.31 0.64 97.89 0.11 97.40 1.25 78.27 0.10 /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3810032418
94.03 0.28 98.56 0.07 93.78 0.13 98.17 0.00 93.59 1.28 97.97 0.07 97.78 0.39 78.32 0.05 /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.296290623
94.28 0.25 98.68 0.11 93.88 0.10 98.17 0.00 94.23 0.64 98.04 0.07 97.98 0.19 78.98 0.66 /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3884253836
94.52 0.24 98.73 0.06 93.98 0.10 99.54 1.37 94.23 0.00 98.04 0.00 97.98 0.00 79.13 0.15 /workspace/coverage/default/41.sysrst_ctrl_alert_test.1813460533
94.74 0.22 98.73 0.00 94.77 0.78 99.54 0.00 94.23 0.00 98.04 0.00 98.55 0.58 79.33 0.20 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2152139982
94.93 0.19 98.79 0.06 94.79 0.03 99.54 0.00 94.23 0.00 98.04 0.00 98.65 0.10 80.50 1.17 /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.748830599
95.11 0.17 98.79 0.00 94.79 0.00 99.54 0.00 94.23 0.00 98.04 0.00 98.65 0.00 81.71 1.22 /workspace/coverage/default/36.sysrst_ctrl_combo_detect.1162102917
95.26 0.16 98.86 0.07 94.87 0.08 99.54 0.00 94.87 0.64 98.15 0.11 98.84 0.19 81.71 0.00 /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.6824066
95.42 0.15 98.92 0.06 94.97 0.10 99.54 0.00 95.51 0.64 98.23 0.07 99.04 0.19 81.71 0.00 /workspace/coverage/default/13.sysrst_ctrl_edge_detect.2778005595
95.56 0.14 98.92 0.00 95.90 0.94 99.54 0.00 95.51 0.00 98.23 0.00 99.04 0.00 81.76 0.05 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2791166045
95.69 0.13 98.96 0.04 95.93 0.03 99.54 0.00 96.15 0.64 98.26 0.04 99.13 0.10 81.86 0.10 /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1695985657
95.82 0.13 99.01 0.06 95.93 0.00 99.54 0.00 96.15 0.00 98.26 0.00 99.13 0.00 82.73 0.86 /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1344306702
95.95 0.12 99.05 0.04 95.98 0.05 99.54 0.00 96.79 0.64 98.30 0.04 99.23 0.10 82.73 0.00 /workspace/coverage/default/30.sysrst_ctrl_edge_detect.2907150720
96.07 0.12 99.09 0.04 96.01 0.03 99.54 0.00 97.44 0.64 98.34 0.04 99.33 0.10 82.73 0.00 /workspace/coverage/default/19.sysrst_ctrl_stress_all.1870710242
96.17 0.10 99.14 0.06 96.18 0.18 99.54 0.00 97.44 0.00 98.41 0.07 99.33 0.00 83.13 0.41 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1162588365
96.26 0.10 99.14 0.00 96.21 0.03 100.00 0.46 97.44 0.00 98.41 0.00 99.42 0.10 83.23 0.10 /workspace/coverage/default/0.sysrst_ctrl_sec_cm.1954909459
96.36 0.09 99.14 0.00 96.21 0.00 100.00 0.00 97.44 0.00 98.41 0.00 99.42 0.00 83.89 0.66 /workspace/coverage/default/18.sysrst_ctrl_stress_all.2115827563
96.44 0.08 99.14 0.00 96.21 0.00 100.00 0.00 97.44 0.00 98.41 0.00 99.42 0.00 84.45 0.56 /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.1441750109
96.51 0.07 99.16 0.02 96.21 0.00 100.00 0.00 97.44 0.00 98.41 0.00 99.42 0.00 84.90 0.46 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1192967487
96.56 0.05 99.18 0.02 96.21 0.00 100.00 0.00 97.44 0.00 98.45 0.04 99.42 0.00 85.21 0.30 /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3993872736
96.61 0.05 99.22 0.04 96.36 0.15 100.00 0.00 97.44 0.00 98.52 0.07 99.52 0.10 85.21 0.00 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3756760410
96.66 0.05 99.22 0.00 96.36 0.00 100.00 0.00 97.44 0.00 98.52 0.00 99.52 0.00 85.56 0.35 /workspace/coverage/default/41.sysrst_ctrl_stress_all.2527572974
96.71 0.05 99.22 0.00 96.66 0.30 100.00 0.00 97.44 0.00 98.52 0.00 99.52 0.00 85.61 0.05 /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2204487585
96.75 0.04 99.22 0.00 96.66 0.00 100.00 0.00 97.44 0.00 98.52 0.00 99.52 0.00 85.92 0.30 /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3275203755
96.79 0.04 99.23 0.02 96.66 0.00 100.00 0.00 97.44 0.00 98.56 0.04 99.52 0.00 86.12 0.20 /workspace/coverage/default/27.sysrst_ctrl_combo_detect.1785602271
96.82 0.03 99.25 0.02 96.66 0.00 100.00 0.00 97.44 0.00 98.60 0.04 99.52 0.00 86.27 0.15 /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.4171566097
96.85 0.03 99.25 0.00 96.66 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.52 0.00 86.47 0.20 /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2324452819
96.88 0.03 99.25 0.00 96.66 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.52 0.00 86.68 0.20 /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3116834475
96.91 0.03 99.25 0.00 96.71 0.05 100.00 0.00 97.44 0.00 98.60 0.00 99.52 0.00 86.83 0.15 /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3695748589
96.93 0.02 99.25 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.52 0.00 86.98 0.15 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1242356344
96.95 0.02 99.25 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.52 0.00 87.13 0.15 /workspace/coverage/default/38.sysrst_ctrl_combo_detect.3715387707
96.97 0.02 99.29 0.04 96.71 0.00 100.00 0.00 97.44 0.00 98.67 0.07 99.52 0.00 87.13 0.00 /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.527291575
96.98 0.02 99.31 0.02 96.71 0.00 100.00 0.00 97.44 0.00 98.71 0.04 99.52 0.00 87.18 0.05 /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1093065215
97.00 0.01 99.31 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.71 0.00 99.52 0.00 87.28 0.10 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.54552966
97.01 0.01 99.31 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.71 0.00 99.52 0.00 87.39 0.10 /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3007292158
97.02 0.01 99.31 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.71 0.00 99.52 0.00 87.49 0.10 /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.2207205868
97.04 0.01 99.31 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.71 0.00 99.52 0.00 87.59 0.10 /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3573077396
97.05 0.01 99.31 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.71 0.00 99.52 0.00 87.69 0.10 /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3451084298
97.07 0.01 99.31 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.71 0.00 99.52 0.00 87.79 0.10 /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3864069531
97.08 0.01 99.31 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.71 0.00 99.61 0.10 87.79 0.00 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1940356394
97.09 0.01 99.33 0.02 96.71 0.00 100.00 0.00 97.44 0.00 98.74 0.04 99.61 0.00 87.79 0.00 /workspace/coverage/default/1.sysrst_ctrl_edge_detect.3521689275
97.10 0.01 99.35 0.02 96.71 0.00 100.00 0.00 97.44 0.00 98.78 0.04 99.61 0.00 87.79 0.00 /workspace/coverage/default/33.sysrst_ctrl_edge_detect.58021055
97.11 0.01 99.37 0.02 96.71 0.00 100.00 0.00 97.44 0.00 98.82 0.04 99.61 0.00 87.79 0.00 /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.164473821
97.11 0.01 99.37 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.82 0.00 99.61 0.00 87.84 0.05 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1886997800
97.12 0.01 99.37 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.82 0.00 99.61 0.00 87.89 0.05 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1446914060
97.13 0.01 99.37 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.82 0.00 99.61 0.00 87.94 0.05 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3192491430
97.13 0.01 99.37 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.82 0.00 99.61 0.00 87.99 0.05 /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.1208386016
97.14 0.01 99.37 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.82 0.00 99.61 0.00 88.04 0.05 /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.674327288
97.15 0.01 99.37 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.82 0.00 99.61 0.00 88.10 0.05 /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.23230205
97.16 0.01 99.37 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.82 0.00 99.61 0.00 88.15 0.05 /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3911648166
97.16 0.01 99.37 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.82 0.00 99.61 0.00 88.20 0.05 /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.1505148624
97.17 0.01 99.37 0.00 96.74 0.03 100.00 0.00 97.44 0.00 98.82 0.00 99.61 0.00 88.20 0.00 /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.2255992671
97.17 0.01 99.37 0.00 96.76 0.03 100.00 0.00 97.44 0.00 98.82 0.00 99.61 0.00 88.20 0.00 /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.4036758982

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1408700388
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2158681385
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.296923922
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3320088278
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3932346834
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1894290930
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.646912039
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.3535346501
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.137141342
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3502464929
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3822443399
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3357149431
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3136589449
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3619731312
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2197727951
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.994649102
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2835607560
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3475807899
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2779289004
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3616216619
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.95340889
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3683916046
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1692379167
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2251115887
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2398409516
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2665427782
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2082187981
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.4156423800
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1413616715
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3353103673
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.402480546
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1999279955
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.859876249
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.41241187
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3357592583
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2596830564
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.232879808
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.966121061
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.771385382
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1285929108
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1284980773
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1687154165
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3979732653
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2396168836
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3955435188
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3932905625
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3632413208
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3667599550
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3121001439
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2247497276
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1155919162
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2824742950
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2996806283
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2079762134
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3022938231
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2022828540
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2126609655
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3394538965
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1700508135
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.752606957
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1645887795
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2691958346
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.128878733
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.700683886
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.1789449299
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.568629612
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.2446339458
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.881304454
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1629914904
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3650066279
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1022080079
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2294639470
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3548375457
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3139919016
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.864164477
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3848700720
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1855453974
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.3318511188
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2856603476
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2144444163
/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1172617434
/workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3628475353
/workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2270985115
/workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1465328334
/workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.4011807050
/workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2588202174
/workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.740947729
/workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3388568464
/workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.893084712
/workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1208544309
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/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2979456212
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1881897603
/workspace/coverage/default/42.sysrst_ctrl_alert_test.2331159511
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3342589629
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.1811741119
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2146637912
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.594000470
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.2674572329
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3915158619
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.956839178
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.34950215
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.714190599
/workspace/coverage/default/42.sysrst_ctrl_smoke.3052097956
/workspace/coverage/default/42.sysrst_ctrl_stress_all.4183172073
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.3101691783
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.822722825
/workspace/coverage/default/43.sysrst_ctrl_alert_test.1590848420
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1206663612
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.1772447473
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2669336391
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2404508327
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.1133664251
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1386761899
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.854256468
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1847632242
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1039089993
/workspace/coverage/default/43.sysrst_ctrl_smoke.2860053748
/workspace/coverage/default/43.sysrst_ctrl_stress_all.1938662883
/workspace/coverage/default/44.sysrst_ctrl_alert_test.2799794880
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.142137250
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.1622230005
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.773479729
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1390927303
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.1829775350
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.4264106816
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3757260955
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3559549188
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2805692855
/workspace/coverage/default/44.sysrst_ctrl_smoke.587142061
/workspace/coverage/default/44.sysrst_ctrl_stress_all.2382051347
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.468145457
/workspace/coverage/default/45.sysrst_ctrl_alert_test.3560566511
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.354921733
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.1399647161
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.30764547
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.3712826400
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2661670400
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.1128197112
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.3850229714
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.3364189606
/workspace/coverage/default/45.sysrst_ctrl_smoke.3003577645
/workspace/coverage/default/45.sysrst_ctrl_stress_all.4096981629
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.3978088025
/workspace/coverage/default/46.sysrst_ctrl_alert_test.2727191473
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.4215287912
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.3623822836
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1609061997
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1756535750
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.2732316834
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1802372501
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3263448047
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1551158966
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2338061846
/workspace/coverage/default/46.sysrst_ctrl_smoke.782034240
/workspace/coverage/default/46.sysrst_ctrl_stress_all.3439095050
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3640402054
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.2779836964
/workspace/coverage/default/47.sysrst_ctrl_alert_test.1747539691
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3292898701
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.3134498658
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.847335855
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3148168029
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.3405934062
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.770511266
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2565107183
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.908035793
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.446742694
/workspace/coverage/default/47.sysrst_ctrl_smoke.2661779650
/workspace/coverage/default/47.sysrst_ctrl_stress_all.3978066563
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2531365316
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3231717754
/workspace/coverage/default/48.sysrst_ctrl_alert_test.2530795651
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1617814501
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.3509750309
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3851826369
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3880951182
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.3924535441
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1819337460
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2229661452
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3651025936
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3941907854
/workspace/coverage/default/48.sysrst_ctrl_smoke.620258818
/workspace/coverage/default/48.sysrst_ctrl_stress_all.3472736201
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.224153426
/workspace/coverage/default/49.sysrst_ctrl_alert_test.2433537223
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.4281713253
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.3460582306
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1655377637
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3009148945
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.1347952292
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.335995456
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.2508073921
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.817836429
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2720262999
/workspace/coverage/default/49.sysrst_ctrl_smoke.3261600004
/workspace/coverage/default/49.sysrst_ctrl_stress_all.3927026623
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2844938401
/workspace/coverage/default/5.sysrst_ctrl_alert_test.1987867174
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2875132287
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.2201896060
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.4256333337
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.1598001772
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3196881964
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.220435598
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.1345335121
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3401154041
/workspace/coverage/default/5.sysrst_ctrl_smoke.1459674582
/workspace/coverage/default/5.sysrst_ctrl_stress_all.2163916358
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.309074823
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.464127341
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1489141653
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.1173371186
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.652439108
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.3938189760
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2775647600
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.4173087099
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.235608200
/workspace/coverage/default/6.sysrst_ctrl_alert_test.4103430309
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.866589903
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.3165283913
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.525902643
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.1927897129
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1997500637
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1907694633
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.3535212449
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3501160328
/workspace/coverage/default/6.sysrst_ctrl_smoke.1246133989
/workspace/coverage/default/6.sysrst_ctrl_stress_all.648211110
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1416534205
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.630875423
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.266633221
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.850868754
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.972454675
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3658549753
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1926197383
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.957646226
/workspace/coverage/default/7.sysrst_ctrl_alert_test.2678928139
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2744665959
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.3280846831
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.2873583289
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1949337330
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.3597587577
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.4228603444
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.136395466
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1748636233
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.584844135
/workspace/coverage/default/7.sysrst_ctrl_smoke.4193720546
/workspace/coverage/default/7.sysrst_ctrl_stress_all.2682410699
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1948673418
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3751854102
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2005043032
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1437391507
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.1431428074
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.718870139
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1885998398
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.1168296930
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.161804651
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.150544477
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1297910992
/workspace/coverage/default/8.sysrst_ctrl_alert_test.4049173977
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1464249496
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.113113297
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1791546912
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.4027628992
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.2215060486
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3706396272
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.3151619201
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.4119118606
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.1282430032
/workspace/coverage/default/8.sysrst_ctrl_smoke.1398346855
/workspace/coverage/default/8.sysrst_ctrl_stress_all.2977290809
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3898232596
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1117864334
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2258356011
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.518770210
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3496578932
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2194822483
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.579280987
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2823069679
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.4061538943
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.2939730702
/workspace/coverage/default/9.sysrst_ctrl_alert_test.3254349895
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.729766233
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.4195815131
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.2722165351
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.2138992929
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.955508305
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2584544284
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3911737347
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.2806361555
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.1005402835
/workspace/coverage/default/9.sysrst_ctrl_smoke.993865616
/workspace/coverage/default/9.sysrst_ctrl_stress_all.2272028794
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.3875817569
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2184788175
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3187583456
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.4182708810
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.4201944713
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3863447656
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1216838224
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1392077107
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1439904078



Total test records in report: 922
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T6 /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.2055285690 Jun 27 05:00:35 PM PDT 24 Jun 27 05:00:43 PM PDT 24 2477286329 ps
T1 /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.1168296930 Jun 27 05:01:56 PM PDT 24 Jun 27 05:02:53 PM PDT 24 41844590308 ps
T2 /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.3855705119 Jun 27 04:59:53 PM PDT 24 Jun 27 05:01:35 PM PDT 24 73032087028 ps
T12 /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.1795965001 Jun 27 05:00:33 PM PDT 24 Jun 27 05:00:41 PM PDT 24 2508424418 ps
T13 /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.866589903 Jun 27 04:59:39 PM PDT 24 Jun 27 04:59:47 PM PDT 24 3457854972 ps
T3 /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.100982065 Jun 27 05:00:04 PM PDT 24 Jun 27 05:00:49 PM PDT 24 63498456737 ps
T14 /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.2974310590 Jun 27 05:01:02 PM PDT 24 Jun 27 05:01:14 PM PDT 24 2695828838 ps
T15 /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.3110425881 Jun 27 05:00:54 PM PDT 24 Jun 27 05:01:02 PM PDT 24 3635819526 ps
T4 /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3610885369 Jun 27 05:01:50 PM PDT 24 Jun 27 05:02:37 PM PDT 24 66030454337 ps
T5 /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3695748589 Jun 27 05:01:54 PM PDT 24 Jun 27 05:02:10 PM PDT 24 489078597766 ps
T7 /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.1571269767 Jun 27 05:00:34 PM PDT 24 Jun 27 05:03:18 PM PDT 24 2583396857947 ps
T47 /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.577779273 Jun 27 05:00:31 PM PDT 24 Jun 27 05:00:39 PM PDT 24 4672398844 ps
T19 /workspace/coverage/default/39.sysrst_ctrl_combo_detect.1266466926 Jun 27 05:01:13 PM PDT 24 Jun 27 05:03:04 PM PDT 24 105747487595 ps
T48 /workspace/coverage/default/41.sysrst_ctrl_alert_test.1813460533 Jun 27 05:01:19 PM PDT 24 Jun 27 05:01:31 PM PDT 24 2013249797 ps
T49 /workspace/coverage/default/15.sysrst_ctrl_smoke.2467037260 Jun 27 05:00:03 PM PDT 24 Jun 27 05:00:09 PM PDT 24 2113579875 ps
T50 /workspace/coverage/default/44.sysrst_ctrl_smoke.587142061 Jun 27 05:01:39 PM PDT 24 Jun 27 05:01:43 PM PDT 24 2157130609 ps
T20 /workspace/coverage/default/34.sysrst_ctrl_combo_detect.3835617724 Jun 27 05:01:05 PM PDT 24 Jun 27 05:03:07 PM PDT 24 42798434247 ps
T51 /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.3593230047 Jun 27 05:01:12 PM PDT 24 Jun 27 05:01:21 PM PDT 24 2650521488 ps
T8 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3355625408 Jun 27 04:59:58 PM PDT 24 Jun 27 05:01:05 PM PDT 24 248457385109 ps
T9 /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.3686039301 Jun 27 05:01:04 PM PDT 24 Jun 27 05:01:20 PM PDT 24 3887545391 ps
T75 /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.282940753 Jun 27 05:00:58 PM PDT 24 Jun 27 05:01:08 PM PDT 24 2136461846 ps
T10 /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.527291575 Jun 27 04:59:40 PM PDT 24 Jun 27 05:00:24 PM PDT 24 81149446838 ps
T11 /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.748830599 Jun 27 05:00:30 PM PDT 24 Jun 27 05:01:07 PM PDT 24 55427436929 ps
T60 /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3501160328 Jun 27 04:59:45 PM PDT 24 Jun 27 04:59:54 PM PDT 24 2522984513 ps
T61 /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.3340709302 Jun 27 05:00:59 PM PDT 24 Jun 27 05:01:10 PM PDT 24 2596333526 ps
T88 /workspace/coverage/default/38.sysrst_ctrl_alert_test.982056060 Jun 27 05:01:22 PM PDT 24 Jun 27 05:01:31 PM PDT 24 2024288755 ps
T40 /workspace/coverage/default/35.sysrst_ctrl_combo_detect.1185792554 Jun 27 05:00:57 PM PDT 24 Jun 27 05:01:20 PM PDT 24 109894647690 ps
T89 /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.995971210 Jun 27 05:00:05 PM PDT 24 Jun 27 05:00:09 PM PDT 24 2065347742 ps
T24 /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.1441750109 Jun 27 05:00:55 PM PDT 24 Jun 27 05:04:09 PM PDT 24 70812750219 ps
T52 /workspace/coverage/default/8.sysrst_ctrl_combo_detect.113113297 Jun 27 04:59:41 PM PDT 24 Jun 27 05:01:38 PM PDT 24 91602515978 ps
T41 /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.3586314736 Jun 27 05:00:28 PM PDT 24 Jun 27 05:00:32 PM PDT 24 3508011831 ps
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T53 /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1117864334 Jun 27 04:59:39 PM PDT 24 Jun 27 04:59:46 PM PDT 24 6144795933 ps
T31 /workspace/coverage/default/26.sysrst_ctrl_edge_detect.2051885891 Jun 27 05:00:54 PM PDT 24 Jun 27 05:01:03 PM PDT 24 5677155229 ps
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T57 /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.3138232778 Jun 27 05:01:12 PM PDT 24 Jun 27 05:01:25 PM PDT 24 2457376365 ps
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T42 /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.3560673314 Jun 27 05:00:35 PM PDT 24 Jun 27 05:00:49 PM PDT 24 3365693185 ps
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T54 /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.1905605799 Jun 27 05:00:03 PM PDT 24 Jun 27 05:00:06 PM PDT 24 4739999069 ps
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T59 /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.1358081714 Jun 27 04:59:54 PM PDT 24 Jun 27 05:00:04 PM PDT 24 2471207661 ps
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T43 /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1193981440 Jun 27 05:00:56 PM PDT 24 Jun 27 05:01:20 PM PDT 24 26602127509 ps
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T55 /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.772268235 Jun 27 05:00:29 PM PDT 24 Jun 27 05:00:31 PM PDT 24 10070369174 ps
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T33 /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3884253836 Jun 27 05:01:36 PM PDT 24 Jun 27 05:02:21 PM PDT 24 60491183459 ps
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T167 /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.765671808 Jun 27 05:00:36 PM PDT 24 Jun 27 05:00:42 PM PDT 24 2632715482 ps
T168 /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.641675267 Jun 27 04:59:23 PM PDT 24 Jun 27 04:59:34 PM PDT 24 2518487583 ps
T95 /workspace/coverage/default/37.sysrst_ctrl_stress_all.2545459005 Jun 27 05:01:08 PM PDT 24 Jun 27 05:07:59 PM PDT 24 162199609577 ps
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T170 /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2661670400 Jun 27 05:01:39 PM PDT 24 Jun 27 05:01:49 PM PDT 24 2607802727 ps
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T56 /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.468145457 Jun 27 05:01:34 PM PDT 24 Jun 27 05:01:46 PM PDT 24 7562910227 ps
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T37 /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2531365316 Jun 27 05:01:34 PM PDT 24 Jun 27 05:02:23 PM PDT 24 76073070951 ps
T175 /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.2589508465 Jun 27 05:00:33 PM PDT 24 Jun 27 05:01:13 PM PDT 24 198406698862 ps
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T179 /workspace/coverage/default/41.sysrst_ctrl_smoke.3247066703 Jun 27 05:01:13 PM PDT 24 Jun 27 05:01:27 PM PDT 24 2111666053 ps
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T27 /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.342412694 Jun 27 05:00:59 PM PDT 24 Jun 27 05:01:49 PM PDT 24 175835233100 ps
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T45 /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.2541519472 Jun 27 05:01:09 PM PDT 24 Jun 27 05:01:53 PM PDT 24 26588302258 ps
T133 /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.1346780152 Jun 27 05:00:06 PM PDT 24 Jun 27 05:00:09 PM PDT 24 2033224701 ps
T134 /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.4021254072 Jun 27 05:00:56 PM PDT 24 Jun 27 05:01:08 PM PDT 24 2014511783 ps
T36 /workspace/coverage/default/17.sysrst_ctrl_edge_detect.1327827353 Jun 27 05:00:32 PM PDT 24 Jun 27 05:00:39 PM PDT 24 5987585672 ps
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T135 /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.34950215 Jun 27 05:01:14 PM PDT 24 Jun 27 05:01:25 PM PDT 24 2153975214 ps
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T394 /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.3656827215 Jun 27 05:00:59 PM PDT 24 Jun 27 05:01:11 PM PDT 24 2468258516 ps
T67 /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.2891254404 Jun 27 05:00:58 PM PDT 24 Jun 27 05:04:58 PM PDT 24 195712198949 ps
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T64 /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3810032418 Jun 27 05:01:12 PM PDT 24 Jun 27 05:03:58 PM PDT 24 554172397248 ps
T77 /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3640402054 Jun 27 05:01:39 PM PDT 24 Jun 27 05:02:27 PM PDT 24 103026133613 ps
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T116 /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.1581562848 Jun 27 05:00:54 PM PDT 24 Jun 27 05:01:08 PM PDT 24 3332048795 ps
T70 /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.1265076953 Jun 27 05:01:02 PM PDT 24 Jun 27 05:01:21 PM PDT 24 9542400409 ps
T46 /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.235608200 Jun 27 05:01:52 PM PDT 24 Jun 27 05:02:11 PM PDT 24 24606269045 ps
T117 /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.1723856650 Jun 27 05:00:33 PM PDT 24 Jun 27 05:00:36 PM PDT 24 2546403307 ps
T118 /workspace/coverage/default/4.sysrst_ctrl_smoke.647924702 Jun 27 04:59:40 PM PDT 24 Jun 27 04:59:51 PM PDT 24 2118597218 ps
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T259 /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.1206470317 Jun 27 04:59:23 PM PDT 24 Jun 27 04:59:31 PM PDT 24 2052275890 ps
T260 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.440995936 Jun 27 04:59:40 PM PDT 24 Jun 27 04:59:51 PM PDT 24 2415306880 ps
T261 /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.1747930392 Jun 27 05:00:36 PM PDT 24 Jun 27 05:00:41 PM PDT 24 2504159548 ps
T262 /workspace/coverage/default/44.sysrst_ctrl_alert_test.2799794880 Jun 27 05:01:34 PM PDT 24 Jun 27 05:01:38 PM PDT 24 2098638780 ps
T263 /workspace/coverage/default/27.sysrst_ctrl_stress_all.362200676 Jun 27 05:00:55 PM PDT 24 Jun 27 05:01:07 PM PDT 24 8647953377 ps
T63 /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.2772625977 Jun 27 04:59:58 PM PDT 24 Jun 27 05:00:26 PM PDT 24 87430235501 ps
T264 /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.43530496 Jun 27 05:00:50 PM PDT 24 Jun 27 05:01:02 PM PDT 24 3705410710 ps
T265 /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.3586165027 Jun 27 05:01:00 PM PDT 24 Jun 27 05:01:14 PM PDT 24 2516922308 ps
T266 /workspace/coverage/default/14.sysrst_ctrl_alert_test.3490775748 Jun 27 05:00:02 PM PDT 24 Jun 27 05:00:06 PM PDT 24 2035613848 ps
T396 /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.4119118606 Jun 27 04:59:44 PM PDT 24 Jun 27 04:59:53 PM PDT 24 2119311054 ps
T397 /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.3722760643 Jun 27 05:00:30 PM PDT 24 Jun 27 05:00:34 PM PDT 24 2471960235 ps
T73 /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.1969788018 Jun 27 05:00:28 PM PDT 24 Jun 27 05:01:16 PM PDT 24 93983154344 ps
T398 /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.769628522 Jun 27 04:59:39 PM PDT 24 Jun 27 04:59:48 PM PDT 24 2528532760 ps
T322 /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3263448047 Jun 27 05:01:39 PM PDT 24 Jun 27 05:01:49 PM PDT 24 2462427628 ps
T399 /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.908035793 Jun 27 05:01:31 PM PDT 24 Jun 27 05:01:37 PM PDT 24 2254530253 ps
T273 /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.2939730702 Jun 27 05:01:50 PM PDT 24 Jun 27 05:02:23 PM PDT 24 44977386805 ps
T375 /workspace/coverage/default/15.sysrst_ctrl_combo_detect.3184916909 Jun 27 05:00:00 PM PDT 24 Jun 27 05:04:21 PM PDT 24 100817764161 ps
T400 /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.1678617195 Jun 27 05:00:27 PM PDT 24 Jun 27 05:00:30 PM PDT 24 2181901165 ps
T401 /workspace/coverage/default/11.sysrst_ctrl_stress_all.1888867966 Jun 27 04:59:56 PM PDT 24 Jun 27 05:00:02 PM PDT 24 6782375157 ps
T30 /workspace/coverage/default/0.sysrst_ctrl_stress_all.3817108147 Jun 27 04:59:23 PM PDT 24 Jun 27 04:59:45 PM PDT 24 991497984498 ps
T376 /workspace/coverage/default/2.sysrst_ctrl_combo_detect.668609079 Jun 27 04:59:34 PM PDT 24 Jun 27 05:00:07 PM PDT 24 33842168276 ps
T402 /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.335995456 Jun 27 05:01:53 PM PDT 24 Jun 27 05:02:03 PM PDT 24 2609232683 ps
T282 /workspace/coverage/default/42.sysrst_ctrl_combo_detect.1811741119 Jun 27 05:01:13 PM PDT 24 Jun 27 05:01:55 PM PDT 24 85727493045 ps
T403 /workspace/coverage/default/29.sysrst_ctrl_stress_all.744379097 Jun 27 05:01:01 PM PDT 24 Jun 27 05:01:27 PM PDT 24 6820422443 ps
T348 /workspace/coverage/default/27.sysrst_ctrl_combo_detect.1785602271 Jun 27 05:00:51 PM PDT 24 Jun 27 05:05:09 PM PDT 24 95950808187 ps
T404 /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.238778565 Jun 27 05:01:19 PM PDT 24 Jun 27 05:01:35 PM PDT 24 3341605478 ps
T405 /workspace/coverage/default/10.sysrst_ctrl_alert_test.513900361 Jun 27 04:59:53 PM PDT 24 Jun 27 04:59:57 PM PDT 24 2033711662 ps
T406 /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.3590885664 Jun 27 05:00:29 PM PDT 24 Jun 27 05:00:32 PM PDT 24 2531546655 ps
T319 /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1549674059 Jun 27 05:00:01 PM PDT 24 Jun 27 05:00:06 PM PDT 24 3583238996 ps
T34 /workspace/coverage/default/33.sysrst_ctrl_edge_detect.58021055 Jun 27 05:01:01 PM PDT 24 Jun 27 05:01:18 PM PDT 24 2411422221 ps
T268 /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.1052514195 Jun 27 05:01:01 PM PDT 24 Jun 27 05:02:14 PM PDT 24 24079925724 ps
T407 /workspace/coverage/default/12.sysrst_ctrl_smoke.1478967990 Jun 27 04:59:55 PM PDT 24 Jun 27 05:00:04 PM PDT 24 2112906691 ps
T408 /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.3967756780 Jun 27 05:01:02 PM PDT 24 Jun 27 05:01:14 PM PDT 24 2260645552 ps
T409 /workspace/coverage/default/42.sysrst_ctrl_stress_all.4183172073 Jun 27 05:01:17 PM PDT 24 Jun 27 05:01:30 PM PDT 24 9940597520 ps
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T410 /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.3437480579 Jun 27 05:00:33 PM PDT 24 Jun 27 05:00:37 PM PDT 24 2109212141 ps
T32 /workspace/coverage/default/40.sysrst_ctrl_edge_detect.3477763213 Jun 27 05:01:14 PM PDT 24 Jun 27 05:01:27 PM PDT 24 2519842447 ps
T411 /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.1888013264 Jun 27 05:01:02 PM PDT 24 Jun 27 05:01:38 PM PDT 24 101018753140 ps
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T412 /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.30764547 Jun 27 05:01:39 PM PDT 24 Jun 27 05:01:53 PM PDT 24 4184445243 ps
T325 /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.1005402835 Jun 27 04:59:41 PM PDT 24 Jun 27 04:59:51 PM PDT 24 2524720248 ps
T279 /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.150544477 Jun 27 05:01:50 PM PDT 24 Jun 27 05:03:20 PM PDT 24 70485139034 ps
T413 /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.4027628992 Jun 27 04:59:41 PM PDT 24 Jun 27 04:59:58 PM PDT 24 3376572826 ps
T312 /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.4281713253 Jun 27 05:01:48 PM PDT 24 Jun 27 05:01:57 PM PDT 24 2986409811 ps
T172 /workspace/coverage/default/44.sysrst_ctrl_edge_detect.1829775350 Jun 27 05:01:37 PM PDT 24 Jun 27 05:01:41 PM PDT 24 2951845885 ps
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T96 /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.224153426 Jun 27 05:01:55 PM PDT 24 Jun 27 05:01:59 PM PDT 24 8166223180 ps
T241 /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.1958392571 Jun 27 04:59:22 PM PDT 24 Jun 27 04:59:31 PM PDT 24 2637241777 ps
T242 /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2324452819 Jun 27 05:01:29 PM PDT 24 Jun 27 05:05:58 PM PDT 24 103239800907 ps
T243 /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.1634673629 Jun 27 04:59:51 PM PDT 24 Jun 27 04:59:59 PM PDT 24 2613073969 ps
T244 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1192967487 Jun 27 04:59:37 PM PDT 24 Jun 27 05:03:40 PM PDT 24 93030398188 ps
T245 /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.2297788050 Jun 27 05:01:01 PM PDT 24 Jun 27 05:01:13 PM PDT 24 2479290066 ps
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T247 /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.575467360 Jun 27 05:00:28 PM PDT 24 Jun 27 05:00:31 PM PDT 24 4525596211 ps
T97 /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.3321358454 Jun 27 05:01:10 PM PDT 24 Jun 27 05:01:23 PM PDT 24 4050392693 ps
T39 /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2979456212 Jun 27 05:01:12 PM PDT 24 Jun 27 05:04:07 PM PDT 24 64362681071 ps
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T160 /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3573077396 Jun 27 05:01:50 PM PDT 24 Jun 27 05:02:37 PM PDT 24 73827343774 ps
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T162 /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.3485910342 Jun 27 05:01:12 PM PDT 24 Jun 27 05:04:00 PM PDT 24 1139099311919 ps
T163 /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.2812284672 Jun 27 04:59:36 PM PDT 24 Jun 27 04:59:41 PM PDT 24 2203156054 ps
T164 /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.804290046 Jun 27 05:00:55 PM PDT 24 Jun 27 05:01:03 PM PDT 24 7512301411 ps
T165 /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3915158619 Jun 27 05:01:15 PM PDT 24 Jun 27 05:01:24 PM PDT 24 2622938241 ps
T78 /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1224675753 Jun 27 05:01:03 PM PDT 24 Jun 27 05:02:01 PM PDT 24 66628282511 ps
T414 /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.3965216259 Jun 27 05:01:01 PM PDT 24 Jun 27 05:01:14 PM PDT 24 9783490144 ps
T313 /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1617814501 Jun 27 05:01:52 PM PDT 24 Jun 27 05:01:58 PM PDT 24 3359601054 ps
T314 /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.3452898969 Jun 27 05:00:30 PM PDT 24 Jun 27 05:00:36 PM PDT 24 3946409796 ps
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T274 /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1392077107 Jun 27 05:02:09 PM PDT 24 Jun 27 05:03:55 PM PDT 24 66914786128 ps
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T416 /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.770511266 Jun 27 05:01:27 PM PDT 24 Jun 27 05:01:33 PM PDT 24 2645943385 ps
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T423 /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.1580213119 Jun 27 05:00:55 PM PDT 24 Jun 27 05:01:07 PM PDT 24 4696924326 ps
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T315 /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.3057170518 Jun 27 05:00:56 PM PDT 24 Jun 27 05:02:00 PM PDT 24 20065364223 ps
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T310 /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.1064633871 Jun 27 05:00:34 PM PDT 24 Jun 27 05:00:43 PM PDT 24 2070866013 ps
T311 /workspace/coverage/default/34.sysrst_ctrl_smoke.761548185 Jun 27 05:01:02 PM PDT 24 Jun 27 05:01:14 PM PDT 24 2133606118 ps
T444 /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.876106399 Jun 27 04:59:58 PM PDT 24 Jun 27 05:00:06 PM PDT 24 4887133741 ps
T445 /workspace/coverage/default/42.sysrst_ctrl_alert_test.2331159511 Jun 27 05:01:14 PM PDT 24 Jun 27 05:01:27 PM PDT 24 2013804886 ps
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