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Summary for Variable cfg.vif.ac_present

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.ac_present

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 103 1 T10 9 T73 10 T39 10
auto[1] 97 1 T10 11 T73 10 T39 10


Summary for Variable cfg.vif.bat_disable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.bat_disable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 102 1 T10 11 T73 9 T39 13
auto[1] 98 1 T10 9 T73 11 T39 7


Summary for Variable cfg.vif.key0_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key0_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 99 1 T10 6 T73 11 T39 11
auto[1] 101 1 T10 14 T73 9 T39 9


Summary for Variable cfg.vif.key0_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key0_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 98 1 T10 12 T73 11 T39 11
auto[1] 102 1 T10 8 T73 9 T39 9


Summary for Variable cfg.vif.key1_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key1_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 101 1 T10 11 T73 9 T39 13
auto[1] 99 1 T10 9 T73 11 T39 7


Summary for Variable cfg.vif.key1_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key1_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 89 1 T10 8 T73 11 T39 10
auto[1] 111 1 T10 12 T73 9 T39 10


Summary for Variable cfg.vif.key2_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key2_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 104 1 T10 10 T73 8 T39 14
auto[1] 96 1 T10 10 T73 12 T39 6


Summary for Variable cfg.vif.key2_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key2_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 95 1 T10 10 T73 11 T39 10
auto[1] 105 1 T10 10 T73 9 T39 10


Summary for Variable cfg.vif.lid_open

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.lid_open

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 114 1 T10 8 T73 13 T39 13
auto[1] 86 1 T10 12 T73 7 T39 7


Summary for Variable cfg.vif.pwrb_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.pwrb_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 109 1 T10 8 T73 13 T39 11
auto[1] 91 1 T10 12 T73 7 T39 9


Summary for Variable cfg.vif.pwrb_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.pwrb_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 94 1 T10 5 T73 9 T39 8
auto[1] 106 1 T10 15 T73 11 T39 12


Summary for Variable cfg.vif.z3_wakeup

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.z3_wakeup

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 111 1 T10 13 T73 9 T39 10
auto[1] 89 1 T10 7 T73 11 T39 10


Summary for Variable cp_ac_present

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 98 1 T10 9 T73 11 T39 10
auto[1] 102 1 T10 11 T73 9 T39 10


Summary for Variable cp_bat_disable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_bat_disable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 102 1 T10 11 T73 9 T39 13
auto[1] 98 1 T10 9 T73 11 T39 7


Summary for Variable cp_key0_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 100 1 T10 12 T73 9 T39 16
auto[1] 100 1 T10 8 T73 11 T39 4


Summary for Variable cp_key0_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 113 1 T10 10 T73 9 T39 12
auto[1] 87 1 T10 10 T73 11 T39 8


Summary for Variable cp_key1_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 106 1 T10 14 T73 9 T39 9
auto[1] 94 1 T10 6 T73 11 T39 11


Summary for Variable cp_key1_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 106 1 T10 7 T73 11 T39 12
auto[1] 94 1 T10 13 T73 9 T39 8


Summary for Variable cp_key2_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 94 1 T10 9 T73 6 T39 11
auto[1] 106 1 T10 11 T73 14 T39 9


Summary for Variable cp_key2_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 95 1 T10 7 T73 9 T39 9
auto[1] 105 1 T10 13 T73 11 T39 11


Summary for Variable cp_lid_open

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_lid_open

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 94 1 T10 10 T73 9 T39 11
auto[1] 106 1 T10 10 T73 11 T39 9


Summary for Variable cp_pwrb_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 94 1 T10 9 T73 10 T39 8
auto[1] 106 1 T10 11 T73 10 T39 12


Summary for Variable cp_pwrb_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 103 1 T10 6 T73 6 T39 11
auto[1] 97 1 T10 14 T73 14 T39 9


Summary for Variable cp_z3_wakeup

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_z3_wakeup

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 111 1 T10 13 T73 9 T39 10
auto[1] 89 1 T10 7 T73 11 T39 10


Summary for Cross key0_inXval

Samples crossed: cp_key0_in cfg.vif.key0_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key0_inXval

Bins
cp_key0_incfg.vif.key0_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 46 1 T10 5 T73 4 T39 9
auto[0] auto[1] 54 1 T10 7 T73 5 T39 7
auto[1] auto[0] 53 1 T10 1 T73 7 T39 2
auto[1] auto[1] 47 1 T10 7 T73 4 T39 2


Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key0_outXval

Bins
cp_key0_outcfg.vif.key0_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 52 1 T10 7 T73 4 T39 7
auto[0] auto[1] 61 1 T10 3 T73 5 T39 5
auto[1] auto[0] 46 1 T10 5 T73 7 T39 4
auto[1] auto[1] 41 1 T10 5 T73 4 T39 4


Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key1_inXval

Bins
cp_key1_incfg.vif.key1_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 48 1 T10 8 T73 2 T39 5
auto[0] auto[1] 58 1 T10 6 T73 7 T39 4
auto[1] auto[0] 53 1 T10 3 T73 7 T39 8
auto[1] auto[1] 41 1 T10 3 T73 4 T39 3


Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key1_outXval

Bins
cp_key1_outcfg.vif.key1_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 42 1 T10 3 T73 4 T39 5
auto[0] auto[1] 64 1 T10 4 T73 7 T39 7
auto[1] auto[0] 47 1 T10 5 T73 7 T39 5
auto[1] auto[1] 47 1 T10 8 T73 2 T39 3


Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key2_inXval

Bins
cp_key2_incfg.vif.key2_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 48 1 T10 5 T73 2 T39 8
auto[0] auto[1] 46 1 T10 4 T73 4 T39 3
auto[1] auto[0] 56 1 T10 5 T73 6 T39 6
auto[1] auto[1] 50 1 T10 6 T73 8 T39 3


Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key2_outXval

Bins
cp_key2_outcfg.vif.key2_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 44 1 T10 4 T73 5 T39 5
auto[0] auto[1] 51 1 T10 3 T73 4 T39 4
auto[1] auto[0] 51 1 T10 6 T73 6 T39 5
auto[1] auto[1] 54 1 T10 7 T73 5 T39 6


Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for pwrb_inXval

Bins
cp_pwrb_incfg.vif.pwrb_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 55 1 T10 5 T73 7 T39 4
auto[0] auto[1] 39 1 T10 4 T73 3 T39 4
auto[1] auto[0] 54 1 T10 3 T73 6 T39 7
auto[1] auto[1] 52 1 T10 8 T73 4 T39 5


Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for pwrb_outXval

Bins
cp_pwrb_outcfg.vif.pwrb_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 52 1 T10 2 T73 3 T39 4
auto[0] auto[1] 51 1 T10 4 T73 3 T39 7
auto[1] auto[0] 42 1 T10 3 T73 6 T39 4
auto[1] auto[1] 55 1 T10 11 T73 8 T39 5


Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for ac_presentXval

Bins
cp_ac_presentcfg.vif.ac_presentCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 51 1 T10 4 T73 6 T39 5
auto[0] auto[1] 47 1 T10 5 T73 5 T39 5
auto[1] auto[0] 52 1 T10 5 T73 4 T39 5
auto[1] auto[1] 50 1 T10 6 T73 5 T39 5


Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for bat_disableXval

Bins
cp_bat_disablecfg.vif.bat_disableCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 102 1 T10 11 T73 9 T39 13
auto[1] auto[1] 98 1 T10 9 T73 11 T39 7


User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded


Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for lid_openXval

Bins
cp_lid_opencfg.vif.lid_openCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 54 1 T10 3 T73 6 T39 7
auto[0] auto[1] 40 1 T10 7 T73 3 T39 4
auto[1] auto[0] 60 1 T10 5 T73 7 T39 6
auto[1] auto[1] 46 1 T10 5 T73 4 T39 3


Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for z3_wakeupXval

Bins
cp_z3_wakeupcfg.vif.z3_wakeupCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 111 1 T10 13 T73 9 T39 10
auto[1] auto[1] 89 1 T10 7 T73 11 T39 10


User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded

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