Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
760 |
1 |
|
|
T16 |
7 |
|
T24 |
5 |
|
T25 |
10 |
| auto[1] |
820 |
1 |
|
|
T16 |
13 |
|
T24 |
15 |
|
T25 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
755 |
1 |
|
|
T16 |
10 |
|
T24 |
10 |
|
T25 |
11 |
| auto[1] |
825 |
1 |
|
|
T16 |
10 |
|
T24 |
10 |
|
T25 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
771 |
1 |
|
|
T16 |
9 |
|
T24 |
9 |
|
T25 |
10 |
| auto[1] |
809 |
1 |
|
|
T16 |
11 |
|
T24 |
11 |
|
T25 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
776 |
1 |
|
|
T16 |
12 |
|
T24 |
8 |
|
T25 |
8 |
| auto[1] |
804 |
1 |
|
|
T16 |
8 |
|
T24 |
12 |
|
T25 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
776 |
1 |
|
|
T16 |
10 |
|
T24 |
9 |
|
T25 |
10 |
| auto[1] |
804 |
1 |
|
|
T16 |
10 |
|
T24 |
11 |
|
T25 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
783 |
1 |
|
|
T16 |
10 |
|
T24 |
9 |
|
T25 |
10 |
| auto[1] |
797 |
1 |
|
|
T16 |
10 |
|
T24 |
11 |
|
T25 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
773 |
1 |
|
|
T16 |
9 |
|
T24 |
8 |
|
T25 |
8 |
| auto[1] |
807 |
1 |
|
|
T16 |
11 |
|
T24 |
12 |
|
T25 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
820 |
1 |
|
|
T16 |
7 |
|
T24 |
17 |
|
T25 |
12 |
| auto[1] |
760 |
1 |
|
|
T16 |
13 |
|
T24 |
3 |
|
T25 |
8 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
829 |
1 |
|
|
T16 |
9 |
|
T24 |
9 |
|
T25 |
12 |
| auto[1] |
751 |
1 |
|
|
T16 |
11 |
|
T24 |
11 |
|
T25 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
781 |
1 |
|
|
T16 |
11 |
|
T24 |
13 |
|
T25 |
10 |
| auto[1] |
799 |
1 |
|
|
T16 |
9 |
|
T24 |
7 |
|
T25 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
790 |
1 |
|
|
T16 |
11 |
|
T24 |
11 |
|
T25 |
7 |
| auto[1] |
790 |
1 |
|
|
T16 |
9 |
|
T24 |
9 |
|
T25 |
13 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
798 |
1 |
|
|
T16 |
10 |
|
T24 |
10 |
|
T25 |
11 |
| auto[1] |
782 |
1 |
|
|
T16 |
10 |
|
T24 |
10 |
|
T25 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
795 |
1 |
|
|
T16 |
10 |
|
T24 |
14 |
|
T25 |
8 |
| auto[1] |
785 |
1 |
|
|
T16 |
10 |
|
T24 |
6 |
|
T25 |
12 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
755 |
1 |
|
|
T16 |
10 |
|
T24 |
10 |
|
T25 |
11 |
| auto[1] |
825 |
1 |
|
|
T16 |
10 |
|
T24 |
10 |
|
T25 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
804 |
1 |
|
|
T16 |
12 |
|
T24 |
13 |
|
T25 |
12 |
| auto[1] |
776 |
1 |
|
|
T16 |
8 |
|
T24 |
7 |
|
T25 |
8 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
787 |
1 |
|
|
T16 |
9 |
|
T24 |
8 |
|
T25 |
10 |
| auto[1] |
793 |
1 |
|
|
T16 |
11 |
|
T24 |
12 |
|
T25 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
786 |
1 |
|
|
T16 |
6 |
|
T24 |
10 |
|
T25 |
10 |
| auto[1] |
794 |
1 |
|
|
T16 |
14 |
|
T24 |
10 |
|
T25 |
10 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
801 |
1 |
|
|
T16 |
14 |
|
T24 |
8 |
|
T25 |
6 |
| auto[1] |
779 |
1 |
|
|
T16 |
6 |
|
T24 |
12 |
|
T25 |
14 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
760 |
1 |
|
|
T16 |
10 |
|
T24 |
13 |
|
T25 |
7 |
| auto[1] |
820 |
1 |
|
|
T16 |
10 |
|
T24 |
7 |
|
T25 |
13 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
793 |
1 |
|
|
T16 |
10 |
|
T24 |
8 |
|
T25 |
13 |
| auto[1] |
787 |
1 |
|
|
T16 |
10 |
|
T24 |
12 |
|
T25 |
7 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
790 |
1 |
|
|
T16 |
11 |
|
T24 |
11 |
|
T25 |
10 |
| auto[1] |
790 |
1 |
|
|
T16 |
9 |
|
T24 |
9 |
|
T25 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
768 |
1 |
|
|
T16 |
11 |
|
T24 |
10 |
|
T25 |
16 |
| auto[1] |
812 |
1 |
|
|
T16 |
9 |
|
T24 |
10 |
|
T25 |
4 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
799 |
1 |
|
|
T16 |
7 |
|
T24 |
10 |
|
T25 |
7 |
| auto[1] |
781 |
1 |
|
|
T16 |
13 |
|
T24 |
10 |
|
T25 |
13 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
798 |
1 |
|
|
T16 |
10 |
|
T24 |
10 |
|
T25 |
11 |
| auto[1] |
782 |
1 |
|
|
T16 |
10 |
|
T24 |
10 |
|
T25 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
379 |
1 |
|
|
T16 |
5 |
|
T24 |
6 |
|
T25 |
6 |
| auto[0] |
auto[1] |
425 |
1 |
|
|
T16 |
7 |
|
T24 |
7 |
|
T25 |
6 |
| auto[1] |
auto[0] |
392 |
1 |
|
|
T16 |
4 |
|
T24 |
3 |
|
T25 |
4 |
| auto[1] |
auto[1] |
384 |
1 |
|
|
T16 |
4 |
|
T24 |
4 |
|
T25 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
373 |
1 |
|
|
T16 |
5 |
|
T24 |
3 |
|
T25 |
4 |
| auto[0] |
auto[1] |
414 |
1 |
|
|
T16 |
4 |
|
T24 |
5 |
|
T25 |
6 |
| auto[1] |
auto[0] |
403 |
1 |
|
|
T16 |
7 |
|
T24 |
5 |
|
T25 |
4 |
| auto[1] |
auto[1] |
390 |
1 |
|
|
T16 |
4 |
|
T24 |
7 |
|
T25 |
6 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
376 |
1 |
|
|
T16 |
2 |
|
T24 |
5 |
|
T25 |
6 |
| auto[0] |
auto[1] |
410 |
1 |
|
|
T16 |
4 |
|
T24 |
5 |
|
T25 |
4 |
| auto[1] |
auto[0] |
400 |
1 |
|
|
T16 |
8 |
|
T24 |
4 |
|
T25 |
4 |
| auto[1] |
auto[1] |
394 |
1 |
|
|
T16 |
6 |
|
T24 |
6 |
|
T25 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
387 |
1 |
|
|
T16 |
6 |
|
T24 |
4 |
|
T25 |
4 |
| auto[0] |
auto[1] |
414 |
1 |
|
|
T16 |
8 |
|
T24 |
4 |
|
T25 |
2 |
| auto[1] |
auto[0] |
396 |
1 |
|
|
T16 |
4 |
|
T24 |
5 |
|
T25 |
6 |
| auto[1] |
auto[1] |
383 |
1 |
|
|
T16 |
2 |
|
T24 |
7 |
|
T25 |
8 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
383 |
1 |
|
|
T16 |
5 |
|
T24 |
4 |
|
T25 |
3 |
| auto[0] |
auto[1] |
377 |
1 |
|
|
T16 |
5 |
|
T24 |
9 |
|
T25 |
4 |
| auto[1] |
auto[0] |
390 |
1 |
|
|
T16 |
4 |
|
T24 |
4 |
|
T25 |
5 |
| auto[1] |
auto[1] |
430 |
1 |
|
|
T16 |
6 |
|
T24 |
3 |
|
T25 |
8 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
423 |
1 |
|
|
T16 |
4 |
|
T24 |
6 |
|
T25 |
8 |
| auto[0] |
auto[1] |
370 |
1 |
|
|
T16 |
6 |
|
T24 |
2 |
|
T25 |
5 |
| auto[1] |
auto[0] |
397 |
1 |
|
|
T16 |
3 |
|
T24 |
11 |
|
T25 |
4 |
| auto[1] |
auto[1] |
390 |
1 |
|
|
T16 |
7 |
|
T24 |
1 |
|
T25 |
3 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
389 |
1 |
|
|
T16 |
6 |
|
T24 |
7 |
|
T25 |
7 |
| auto[0] |
auto[1] |
379 |
1 |
|
|
T16 |
5 |
|
T24 |
3 |
|
T25 |
9 |
| auto[1] |
auto[0] |
392 |
1 |
|
|
T16 |
5 |
|
T24 |
6 |
|
T25 |
3 |
| auto[1] |
auto[1] |
420 |
1 |
|
|
T16 |
4 |
|
T24 |
4 |
|
T25 |
1 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
409 |
1 |
|
|
T16 |
4 |
|
T24 |
6 |
|
T25 |
1 |
| auto[0] |
auto[1] |
390 |
1 |
|
|
T16 |
3 |
|
T24 |
4 |
|
T25 |
6 |
| auto[1] |
auto[0] |
381 |
1 |
|
|
T16 |
7 |
|
T24 |
5 |
|
T25 |
6 |
| auto[1] |
auto[1] |
400 |
1 |
|
|
T16 |
6 |
|
T24 |
5 |
|
T25 |
7 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
381 |
1 |
|
|
T16 |
2 |
|
T24 |
3 |
|
T25 |
6 |
| auto[0] |
auto[1] |
414 |
1 |
|
|
T16 |
8 |
|
T24 |
11 |
|
T25 |
2 |
| auto[1] |
auto[0] |
379 |
1 |
|
|
T16 |
5 |
|
T24 |
2 |
|
T25 |
4 |
| auto[1] |
auto[1] |
406 |
1 |
|
|
T16 |
5 |
|
T24 |
4 |
|
T25 |
8 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
755 |
1 |
|
|
T16 |
10 |
|
T24 |
10 |
|
T25 |
11 |
| auto[1] |
auto[1] |
825 |
1 |
|
|
T16 |
10 |
|
T24 |
10 |
|
T25 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
416 |
1 |
|
|
T16 |
5 |
|
T24 |
5 |
|
T25 |
5 |
| auto[0] |
auto[1] |
374 |
1 |
|
|
T16 |
6 |
|
T24 |
6 |
|
T25 |
5 |
| auto[1] |
auto[0] |
413 |
1 |
|
|
T16 |
4 |
|
T24 |
4 |
|
T25 |
7 |
| auto[1] |
auto[1] |
377 |
1 |
|
|
T16 |
5 |
|
T24 |
5 |
|
T25 |
3 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
798 |
1 |
|
|
T16 |
10 |
|
T24 |
10 |
|
T25 |
11 |
| auto[1] |
auto[1] |
782 |
1 |
|
|
T16 |
10 |
|
T24 |
10 |
|
T25 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
80 |
1 |
|
|
T68 |
11 |
|
T121 |
13 |
|
T142 |
9 |
| auto[1] |
80 |
1 |
|
|
T68 |
9 |
|
T121 |
7 |
|
T142 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
92 |
1 |
|
|
T68 |
10 |
|
T121 |
13 |
|
T142 |
6 |
| auto[1] |
68 |
1 |
|
|
T68 |
10 |
|
T121 |
7 |
|
T142 |
14 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
79 |
1 |
|
|
T68 |
12 |
|
T121 |
11 |
|
T142 |
8 |
| auto[1] |
81 |
1 |
|
|
T68 |
8 |
|
T121 |
9 |
|
T142 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
83 |
1 |
|
|
T68 |
8 |
|
T121 |
9 |
|
T142 |
10 |
| auto[1] |
77 |
1 |
|
|
T68 |
12 |
|
T121 |
11 |
|
T142 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
70 |
1 |
|
|
T68 |
6 |
|
T121 |
10 |
|
T142 |
7 |
| auto[1] |
90 |
1 |
|
|
T68 |
14 |
|
T121 |
10 |
|
T142 |
13 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
71 |
1 |
|
|
T68 |
8 |
|
T121 |
6 |
|
T142 |
8 |
| auto[1] |
89 |
1 |
|
|
T68 |
12 |
|
T121 |
14 |
|
T142 |
12 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
73 |
1 |
|
|
T68 |
4 |
|
T121 |
10 |
|
T142 |
8 |
| auto[1] |
87 |
1 |
|
|
T68 |
16 |
|
T121 |
10 |
|
T142 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
76 |
1 |
|
|
T68 |
10 |
|
T121 |
11 |
|
T142 |
9 |
| auto[1] |
84 |
1 |
|
|
T68 |
10 |
|
T121 |
9 |
|
T142 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
85 |
1 |
|
|
T68 |
11 |
|
T121 |
6 |
|
T142 |
15 |
| auto[1] |
75 |
1 |
|
|
T68 |
9 |
|
T121 |
14 |
|
T142 |
5 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
83 |
1 |
|
|
T68 |
11 |
|
T121 |
12 |
|
T142 |
9 |
| auto[1] |
77 |
1 |
|
|
T68 |
9 |
|
T121 |
8 |
|
T142 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
79 |
1 |
|
|
T68 |
8 |
|
T121 |
10 |
|
T142 |
9 |
| auto[1] |
81 |
1 |
|
|
T68 |
12 |
|
T121 |
10 |
|
T142 |
11 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
78 |
1 |
|
|
T68 |
14 |
|
T121 |
11 |
|
T142 |
10 |
| auto[1] |
82 |
1 |
|
|
T68 |
6 |
|
T121 |
9 |
|
T142 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
81 |
1 |
|
|
T68 |
11 |
|
T121 |
7 |
|
T142 |
12 |
| auto[1] |
79 |
1 |
|
|
T68 |
9 |
|
T121 |
13 |
|
T142 |
8 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
92 |
1 |
|
|
T68 |
10 |
|
T121 |
13 |
|
T142 |
6 |
| auto[1] |
68 |
1 |
|
|
T68 |
10 |
|
T121 |
7 |
|
T142 |
14 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
80 |
1 |
|
|
T68 |
7 |
|
T121 |
12 |
|
T142 |
10 |
| auto[1] |
80 |
1 |
|
|
T68 |
13 |
|
T121 |
8 |
|
T142 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
74 |
1 |
|
|
T68 |
7 |
|
T121 |
8 |
|
T142 |
8 |
| auto[1] |
86 |
1 |
|
|
T68 |
13 |
|
T121 |
12 |
|
T142 |
12 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
90 |
1 |
|
|
T68 |
12 |
|
T121 |
10 |
|
T142 |
15 |
| auto[1] |
70 |
1 |
|
|
T68 |
8 |
|
T121 |
10 |
|
T142 |
5 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
73 |
1 |
|
|
T68 |
12 |
|
T121 |
8 |
|
T142 |
12 |
| auto[1] |
87 |
1 |
|
|
T68 |
8 |
|
T121 |
12 |
|
T142 |
8 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
79 |
1 |
|
|
T68 |
9 |
|
T121 |
11 |
|
T142 |
10 |
| auto[1] |
81 |
1 |
|
|
T68 |
11 |
|
T121 |
9 |
|
T142 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
76 |
1 |
|
|
T68 |
9 |
|
T121 |
8 |
|
T142 |
11 |
| auto[1] |
84 |
1 |
|
|
T68 |
11 |
|
T121 |
12 |
|
T142 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
71 |
1 |
|
|
T68 |
8 |
|
T121 |
8 |
|
T142 |
7 |
| auto[1] |
89 |
1 |
|
|
T68 |
12 |
|
T121 |
12 |
|
T142 |
13 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
75 |
1 |
|
|
T68 |
6 |
|
T121 |
11 |
|
T142 |
10 |
| auto[1] |
85 |
1 |
|
|
T68 |
14 |
|
T121 |
9 |
|
T142 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
81 |
1 |
|
|
T68 |
11 |
|
T121 |
9 |
|
T142 |
8 |
| auto[1] |
79 |
1 |
|
|
T68 |
9 |
|
T121 |
11 |
|
T142 |
12 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
78 |
1 |
|
|
T68 |
14 |
|
T121 |
11 |
|
T142 |
10 |
| auto[1] |
82 |
1 |
|
|
T68 |
6 |
|
T121 |
9 |
|
T142 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
34 |
1 |
|
|
T68 |
4 |
|
T121 |
5 |
|
T142 |
3 |
| auto[0] |
auto[1] |
46 |
1 |
|
|
T68 |
3 |
|
T121 |
7 |
|
T142 |
7 |
| auto[1] |
auto[0] |
45 |
1 |
|
|
T68 |
8 |
|
T121 |
6 |
|
T142 |
5 |
| auto[1] |
auto[1] |
35 |
1 |
|
|
T68 |
5 |
|
T121 |
2 |
|
T142 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
33 |
1 |
|
|
T68 |
2 |
|
T121 |
2 |
|
T142 |
3 |
| auto[0] |
auto[1] |
41 |
1 |
|
|
T68 |
5 |
|
T121 |
6 |
|
T142 |
5 |
| auto[1] |
auto[0] |
50 |
1 |
|
|
T68 |
6 |
|
T121 |
7 |
|
T142 |
7 |
| auto[1] |
auto[1] |
36 |
1 |
|
|
T68 |
7 |
|
T121 |
5 |
|
T142 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
40 |
1 |
|
|
T68 |
4 |
|
T121 |
5 |
|
T142 |
6 |
| auto[0] |
auto[1] |
50 |
1 |
|
|
T68 |
8 |
|
T121 |
5 |
|
T142 |
9 |
| auto[1] |
auto[0] |
30 |
1 |
|
|
T68 |
2 |
|
T121 |
5 |
|
T142 |
1 |
| auto[1] |
auto[1] |
40 |
1 |
|
|
T68 |
6 |
|
T121 |
5 |
|
T142 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
32 |
1 |
|
|
T68 |
5 |
|
T121 |
2 |
|
T142 |
5 |
| auto[0] |
auto[1] |
41 |
1 |
|
|
T68 |
7 |
|
T121 |
6 |
|
T142 |
7 |
| auto[1] |
auto[0] |
39 |
1 |
|
|
T68 |
3 |
|
T121 |
4 |
|
T142 |
3 |
| auto[1] |
auto[1] |
48 |
1 |
|
|
T68 |
5 |
|
T121 |
8 |
|
T142 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
38 |
1 |
|
|
T68 |
2 |
|
T121 |
4 |
|
T142 |
3 |
| auto[0] |
auto[1] |
41 |
1 |
|
|
T68 |
7 |
|
T121 |
7 |
|
T142 |
7 |
| auto[1] |
auto[0] |
35 |
1 |
|
|
T68 |
2 |
|
T121 |
6 |
|
T142 |
5 |
| auto[1] |
auto[1] |
46 |
1 |
|
|
T68 |
9 |
|
T121 |
3 |
|
T142 |
5 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
38 |
1 |
|
|
T68 |
5 |
|
T121 |
3 |
|
T142 |
4 |
| auto[0] |
auto[1] |
38 |
1 |
|
|
T68 |
4 |
|
T121 |
5 |
|
T142 |
7 |
| auto[1] |
auto[0] |
38 |
1 |
|
|
T68 |
5 |
|
T121 |
8 |
|
T142 |
5 |
| auto[1] |
auto[1] |
46 |
1 |
|
|
T68 |
6 |
|
T121 |
4 |
|
T142 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
40 |
1 |
|
|
T68 |
3 |
|
T121 |
6 |
|
T142 |
4 |
| auto[0] |
auto[1] |
35 |
1 |
|
|
T68 |
3 |
|
T121 |
5 |
|
T142 |
6 |
| auto[1] |
auto[0] |
43 |
1 |
|
|
T68 |
8 |
|
T121 |
6 |
|
T142 |
5 |
| auto[1] |
auto[1] |
42 |
1 |
|
|
T68 |
6 |
|
T121 |
3 |
|
T142 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
41 |
1 |
|
|
T68 |
4 |
|
T121 |
4 |
|
T142 |
3 |
| auto[0] |
auto[1] |
40 |
1 |
|
|
T68 |
7 |
|
T121 |
5 |
|
T142 |
5 |
| auto[1] |
auto[0] |
38 |
1 |
|
|
T68 |
4 |
|
T121 |
6 |
|
T142 |
6 |
| auto[1] |
auto[1] |
41 |
1 |
|
|
T68 |
5 |
|
T121 |
5 |
|
T142 |
6 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
39 |
1 |
|
|
T68 |
7 |
|
T121 |
4 |
|
T142 |
7 |
| auto[0] |
auto[1] |
42 |
1 |
|
|
T68 |
4 |
|
T121 |
3 |
|
T142 |
5 |
| auto[1] |
auto[0] |
41 |
1 |
|
|
T68 |
4 |
|
T121 |
9 |
|
T142 |
2 |
| auto[1] |
auto[1] |
38 |
1 |
|
|
T68 |
5 |
|
T121 |
4 |
|
T142 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
92 |
1 |
|
|
T68 |
10 |
|
T121 |
13 |
|
T142 |
6 |
| auto[1] |
auto[1] |
68 |
1 |
|
|
T68 |
10 |
|
T121 |
7 |
|
T142 |
14 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
40 |
1 |
|
|
T68 |
5 |
|
T142 |
5 |
|
T145 |
5 |
| auto[0] |
auto[1] |
31 |
1 |
|
|
T68 |
3 |
|
T121 |
8 |
|
T142 |
2 |
| auto[1] |
auto[0] |
45 |
1 |
|
|
T68 |
6 |
|
T121 |
6 |
|
T142 |
10 |
| auto[1] |
auto[1] |
44 |
1 |
|
|
T68 |
6 |
|
T121 |
6 |
|
T142 |
3 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
78 |
1 |
|
|
T68 |
14 |
|
T121 |
11 |
|
T142 |
10 |
| auto[1] |
auto[1] |
82 |
1 |
|
|
T68 |
6 |
|
T121 |
9 |
|
T142 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20 |
1 |
|
|
T142 |
11 |
|
T170 |
9 |
| auto[1] |
20 |
1 |
|
|
T142 |
9 |
|
T170 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20 |
1 |
|
|
T142 |
7 |
|
T170 |
13 |
| auto[1] |
20 |
1 |
|
|
T142 |
13 |
|
T170 |
7 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14 |
1 |
|
|
T142 |
7 |
|
T170 |
7 |
| auto[1] |
26 |
1 |
|
|
T142 |
13 |
|
T170 |
13 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
22 |
1 |
|
|
T142 |
10 |
|
T170 |
12 |
| auto[1] |
18 |
1 |
|
|
T142 |
10 |
|
T170 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
22 |
1 |
|
|
T142 |
11 |
|
T170 |
11 |
| auto[1] |
18 |
1 |
|
|
T142 |
9 |
|
T170 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17 |
1 |
|
|
T142 |
7 |
|
T170 |
10 |
| auto[1] |
23 |
1 |
|
|
T142 |
13 |
|
T170 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14 |
1 |
|
|
T142 |
9 |
|
T170 |
5 |
| auto[1] |
26 |
1 |
|
|
T142 |
11 |
|
T170 |
15 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
22 |
1 |
|
|
T142 |
11 |
|
T170 |
11 |
| auto[1] |
18 |
1 |
|
|
T142 |
9 |
|
T170 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20 |
1 |
|
|
T142 |
8 |
|
T170 |
12 |
| auto[1] |
20 |
1 |
|
|
T142 |
12 |
|
T170 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18 |
1 |
|
|
T142 |
9 |
|
T170 |
9 |
| auto[1] |
22 |
1 |
|
|
T142 |
11 |
|
T170 |
11 |