Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg
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Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_cov_0/sysrst_ctrl_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_key_intr_status_cg 100.00 1 100 1 64 64




Group Instance : sysrst_ctrl_key_intr_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_key_intr_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 28 0 28 100.00


Variables for Group Instance sysrst_ctrl_key_intr_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_ac_present_h2l 2 0 2 100.00 100 1 1 2
cp_ac_present_l2h 2 0 2 100.00 100 1 1 2
cp_ec_rst_l_h2l 2 0 2 100.00 100 1 1 2
cp_ec_rst_l_l2h 2 0 2 100.00 100 1 1 2
cp_flash_wp_l_h2l 2 0 2 100.00 100 1 1 2
cp_flash_wp_l_l2h 2 0 2 100.00 100 1 1 2
cp_key0_in_h2l 2 0 2 100.00 100 1 1 2
cp_key0_in_l2h 2 0 2 100.00 100 1 1 2
cp_key1_in_h2l 2 0 2 100.00 100 1 1 2
cp_key1_in_l2h 2 0 2 100.00 100 1 1 2
cp_key2_in_h2l 2 0 2 100.00 100 1 1 2
cp_key2_in_l2h 2 0 2 100.00 100 1 1 2
cp_pwrb_h2l 2 0 2 100.00 100 1 1 2
cp_pwrb_l2h 2 0 2 100.00 100 1 1 2


Summary for Variable cp_ac_present_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 991 1 T4 15 T8 2 T10 15
auto[1] 109 1 T8 1 T39 1 T40 2



Summary for Variable cp_ac_present_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 947 1 T4 12 T8 2 T10 15
auto[1] 153 1 T4 3 T8 1 T39 2



Summary for Variable cp_ec_rst_l_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst_l_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 946 1 T4 15 T8 3 T10 15
auto[1] 154 1 T39 1 T40 3 T34 1



Summary for Variable cp_ec_rst_l_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst_l_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1001 1 T4 15 T8 3 T10 15
auto[1] 99 1 T34 3 T36 2 T37 3



Summary for Variable cp_flash_wp_l_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_flash_wp_l_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 944 1 T4 15 T8 1 T10 15
auto[1] 156 1 T8 2 T39 4 T40 3



Summary for Variable cp_flash_wp_l_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_flash_wp_l_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1000 1 T4 15 T8 3 T10 15
auto[1] 100 1 T13 1 T39 2 T40 3



Summary for Variable cp_key0_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1006 1 T4 13 T8 3 T10 15
auto[1] 94 1 T4 2 T39 2 T40 2



Summary for Variable cp_key0_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 980 1 T4 12 T8 3 T10 15
auto[1] 120 1 T4 3 T13 1 T39 2



Summary for Variable cp_key1_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 994 1 T4 15 T8 2 T10 15
auto[1] 106 1 T8 1 T40 3 T35 1



Summary for Variable cp_key1_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 958 1 T4 15 T8 1 T10 15
auto[1] 142 1 T8 2 T39 1 T35 2



Summary for Variable cp_key2_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 995 1 T4 13 T8 1 T10 15
auto[1] 105 1 T4 2 T8 2 T40 2



Summary for Variable cp_key2_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 975 1 T4 12 T8 1 T10 15
auto[1] 125 1 T4 3 T8 2 T13 3



Summary for Variable cp_pwrb_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1008 1 T4 15 T8 3 T10 15
auto[1] 92 1 T39 1 T35 2 T36 2



Summary for Variable cp_pwrb_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 952 1 T4 15 T8 3 T10 15
auto[1] 148 1 T39 2 T34 3 T36 2

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