Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1918

1

T1

18

T2

13

T3

12

auto[1]

643

1

T1

6

T2

2

T3

7

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1940

1

T1

24

T2

7

T3

7

auto[1]

621

1

T2

8

T3

12

T9

4

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1874

1

T1

9

T2

13

T3

19

auto[1]

687

1

T1

15

T2

2

T9

13

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1998

1

T1

24

T2

10

T3

7

auto[1]

563

1

T2

5

T3

12

T9

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2362

1

T1

21

T2

15

T3

19

auto[1]

199

1

T1

3

T11

3

T45

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2309

1

T1

9

T2

15

T3

19

auto[1]

252

1

T1

15

T47

2

T33

11

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2350

1

T1

24

T2

15

T3

19

auto[1]

211

1

T11

3

T45

2

T33

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2362

1

T1

21

T2

15

T3

19

auto[1]

199

1

T1

3

T11

5

T75

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2391

1

T1

24

T2

15

T3

19

auto[1]

170

1

T45

2

T47

7

T33

7

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1906

1

T1

15

T2

2

T3

12

auto[1]

655

1

T1

9

T2

13

T3

7

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

969

1

T2

10

T3

19

T9

19

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

75

1

T47

7

T80

1

T173

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

48

1

T47

5

T379

7

T203

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T185

5

T396

2

-

-

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

58

1

T11

5

T75

2

T287

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T302

1

T378

2

T389

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

15

1

T33

5

T396

1

T397

9

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T33

2

T398

3

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

69

1

T80

2

T81

1

T375

12

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

10

1

T11

3

T289

2

T399

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

19

1

T287

1

T382

5

T295

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T45

2

T377

3

T295

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

27

1

T286

7

T159

4

T400

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T401

3

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

4

1

T112

2

T398

2

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

86

1

T1

12

T173

4

T287

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

21

1

T377

5

T402

3

T382

9

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

33

1

T47

2

T287

2

T302

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T403

2

T404

2

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

40

1

T33

10

T296

2

T386

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T1

3

T286

1

T405

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

10

1

T375

4

T406

2

T390

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

16

1

T172

2

T294

2

T407

10

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

5

1

T213

3

T159

2

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

8

1

T90

4

T173

1

T391

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T33

1

T407

6

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

121

1

T11

5

T47

2

T33

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

128

1

T32

8

T115

7

T33

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

85

1

T9

5

T173

1

T304

16

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

107

1

T45

2

T144

8

T287

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

67

1

T32

6

T47

5

T302

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

56

1

T3

7

T49

3

T115

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

18

1

T303

3

T41

1

T375

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

108

1

T1

6

T9

10

T408

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

66

1

T2

2

T32

7

T81

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

57

1

T1

3

T286

1

T405

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

27

1

T1

6

T291

1

T296

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T287

4

T41

2

T409

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

34

1

T202

1

T378

4

T96

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

44

1

T144

3

T77

4

T41

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

19

1

T32

3

T173

4

T85

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

106

1

T11

3

T80

1

T287

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

54

1

T3

7

T80

2

T374

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

63

1

T2

8

T10

1

T91

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

37

1

T75

2

T303

2

T291

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

60

1

T3

5

T115

6

T173

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T394

6

T299

2

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

12

1

T304

3

T95

5

T96

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T9

1

T13

1

T375

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

109

1

T47

7

T33

2

T85

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T9

3

T144

7

T33

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

33

1

T173

3

T97

10

T233

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T34

2

T298

1

T387

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

16

1

T410

3

T391

8

T392

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T382

8

T306

2

T277

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

13

1

T49

1

T77

3

T91

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T392

2

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded