Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

838

1

T7

11

T4

12

T10

14

auto[1]

911

1

T7

9

T4

8

T10

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

415

1

T7

5

T4

5

T10

6

from_0to1

416

1

T7

5

T4

5

T10

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

877

1

T7

9

T4

12

T10

14

auto[1]

872

1

T7

11

T4

8

T10

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

901

1

T7

10

T4

13

T10

16

auto[1]

848

1

T7

10

T4

7

T10

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

46

1

T7

2

T4

1

T10

2

auto[0]

from_1to0

auto[0]

auto[1]

52

1

T10

1

T69

1

T419

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T4

1

T10

2

T28

1

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T7

1

T4

1

T28

1

auto[0]

from_0to1

auto[0]

auto[0]

51

1

T4

1

T10

1

T28

2

auto[0]

from_0to1

auto[0]

auto[1]

43

1

T419

1

T61

1

T138

1

auto[0]

from_0to1

auto[1]

auto[0]

51

1

T7

1

T28

1

T71

1

auto[0]

from_0to1

auto[1]

auto[1]

51

1

T7

2

T28

1

T70

1

auto[1]

from_1to0

auto[0]

auto[0]

47

1

T7

1

T4

1

T419

1

auto[1]

from_1to0

auto[0]

auto[1]

51

1

T69

1

T71

1

T419

1

auto[1]

from_1to0

auto[1]

auto[0]

53

1

T7

1

T4

1

T28

2

auto[1]

from_1to0

auto[1]

auto[1]

54

1

T10

1

T349

2

T61

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T7

1

T10

1

T69

1

auto[1]

from_0to1

auto[0]

auto[1]

53

1

T4

1

T10

2

T131

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T4

3

T10

1

T69

1

auto[1]

from_0to1

auto[1]

auto[1]

45

1

T7

1

T10

1

T69

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

884

1

T7

7

T4

11

T10

14

auto[1]

865

1

T7

13

T4

9

T10

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

421

1

T7

5

T4

3

T10

10

from_0to1

424

1

T7

4

T4

4

T10

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

887

1

T7

9

T4

8

T10

16

auto[1]

862

1

T7

11

T4

12

T10

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

881

1

T7

11

T4

8

T10

15

auto[1]

868

1

T7

9

T4

12

T10

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T10

3

T70

1

T419

1

auto[0]

from_1to0

auto[0]

auto[1]

45

1

T10

1

T69

1

T71

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T69

2

T70

2

T61

1

auto[0]

from_1to0

auto[1]

auto[1]

44

1

T10

2

T28

1

T70

1

auto[0]

from_0to1

auto[0]

auto[0]

51

1

T7

2

T10

1

T28

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T7

1

T4

1

T28

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T10

1

T28

1

T70

1

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T4

1

T10

1

T69

2

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T7

3

T10

1

T28

2

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T4

1

T10

2

T71

1

auto[1]

from_1to0

auto[1]

auto[0]

55

1

T4

1

T10

1

T28

1

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T7

2

T4

1

T28

1

auto[1]

from_0to1

auto[0]

auto[0]

46

1

T10

1

T28

1

T70

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T7

1

T4

1

T10

3

auto[1]

from_0to1

auto[1]

auto[0]

51

1

T4

1

T10

1

T28

1

auto[1]

from_0to1

auto[1]

auto[1]

41

1

T10

2

T70

3

T71

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

886

1

T7

10

T4

13

T10

20

auto[1]

863

1

T7

10

T4

7

T10

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

415

1

T7

4

T4

6

T10

8

from_0to1

422

1

T7

5

T4

5

T10

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

880

1

T7

10

T4

8

T10

16

auto[1]

869

1

T7

10

T4

12

T10

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

849

1

T7

8

T4

9

T10

15

auto[1]

900

1

T7

12

T4

11

T10

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T7

1

T4

1

T10

3

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T4

1

T10

1

T28

1

auto[0]

from_1to0

auto[1]

auto[0]

47

1

T10

2

T70

1

T131

1

auto[0]

from_1to0

auto[1]

auto[1]

50

1

T7

1

T4

2

T28

1

auto[0]

from_0to1

auto[0]

auto[0]

41

1

T7

1

T10

2

T70

2

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T7

1

T4

2

T10

2

auto[0]

from_0to1

auto[1]

auto[0]

52

1

T4

1

T28

1

T419

1

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T4

1

T10

1

T71

1

auto[1]

from_1to0

auto[0]

auto[0]

48

1

T4

1

T28

1

T70

1

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T7

1

T61

2

T420

1

auto[1]

from_1to0

auto[1]

auto[0]

49

1

T7

1

T4

1

T10

1

auto[1]

from_1to0

auto[1]

auto[1]

48

1

T10

1

T419

1

T349

1

auto[1]

from_0to1

auto[0]

auto[0]

45

1

T28

2

T69

2

T419

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T10

1

T28

1

T69

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T7

2

T4

1

T69

1

auto[1]

from_0to1

auto[1]

auto[1]

50

1

T7

1

T10

1

T71

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

900

1

T7

15

T4

10

T10

15

auto[1]

849

1

T7

5

T4

10

T10

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

424

1

T7

5

T4

4

T10

7

from_0to1

422

1

T7

5

T4

5

T10

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

894

1

T7

9

T4

9

T10

18

auto[1]

855

1

T7

11

T4

11

T10

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

919

1

T7

8

T4

10

T10

15

auto[1]

830

1

T7

12

T4

10

T10

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T7

2

T10

2

T28

3

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T7

1

T10

2

T28

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T4

2

T69

1

T71

2

auto[0]

from_1to0

auto[1]

auto[1]

46

1

T10

1

T69

1

T70

2

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T7

1

T4

1

T419

1

auto[0]

from_0to1

auto[0]

auto[1]

49

1

T7

2

T10

2

T28

2

auto[0]

from_0to1

auto[1]

auto[0]

42

1

T7

1

T69

1

T70

2

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T4

1

T28

1

T69

1

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T4

1

T69

2

T70

1

auto[1]

from_1to0

auto[0]

auto[1]

34

1

T10

1

T70

1

T419

1

auto[1]

from_1to0

auto[1]

auto[0]

51

1

T7

1

T10

1

T28

1

auto[1]

from_1to0

auto[1]

auto[1]

53

1

T7

1

T4

1

T28

2

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T4

1

T10

1

T69

1

auto[1]

from_0to1

auto[0]

auto[1]

48

1

T10

1

T28

1

T69

1

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T7

1

T4

2

T10

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T10

1

T28

2

T69

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

883

1

T7

11

T4

11

T10

13

auto[1]

866

1

T7

9

T4

9

T10

16

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

417

1

T7

4

T4

5

T10

8

from_0to1

419

1

T7

5

T4

6

T10

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

884

1

T7

9

T4

15

T10

13

auto[1]

865

1

T7

11

T4

5

T10

16

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

864

1

T7

10

T4

13

T10

14

auto[1]

885

1

T7

10

T4

7

T10

15

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

56

1

T7

1

T4

1

T10

1

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T4

1

T10

1

T28

1

auto[0]

from_1to0

auto[1]

auto[0]

36

1

T69

2

T70

1

T71

1

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T7

1

T10

2

T69

1

auto[0]

from_0to1

auto[0]

auto[0]

51

1

T4

2

T28

1

T70

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T7

1

T4

1

T10

1

auto[0]

from_0to1

auto[1]

auto[0]

45

1

T7

1

T4

1

T10

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T7

1

T10

1

T69

1

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T4

2

T10

1

T69

1

auto[1]

from_1to0

auto[0]

auto[1]

49

1

T4

1

T69

1

T70

1

auto[1]

from_1to0

auto[1]

auto[0]

54

1

T7

1

T28

1

T70

1

auto[1]

from_1to0

auto[1]

auto[1]

54

1

T7

1

T10

3

T28

1

auto[1]

from_0to1

auto[0]

auto[0]

41

1

T4

1

T28

1

T69

1

auto[1]

from_0to1

auto[0]

auto[1]

46

1

T7

1

T10

1

T28

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T4

1

T10

2

T28

1

auto[1]

from_0to1

auto[1]

auto[1]

47

1

T7

1

T10

1

T69

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

880

1

T7

9

T4

13

T10

15

auto[1]

869

1

T7

11

T4

7

T10

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

426

1

T7

4

T4

6

T10

7

from_0to1

430

1

T7

4

T4

5

T10

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

887

1

T7

10

T4

8

T10

14

auto[1]

862

1

T7

10

T4

12

T10

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

879

1

T7

12

T4

8

T10

11

auto[1]

870

1

T7

8

T4

12

T10

18

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

51

1

T4

1

T10

1

T70

1

auto[0]

from_1to0

auto[0]

auto[1]

52

1

T10

2

T28

2

T61

2

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T7

2

T4

1

T28

1

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T4

2

T10

1

T28

1

auto[0]

from_0to1

auto[0]

auto[0]

49

1

T10

1

T419

1

T349

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T4

3

T10

1

T69

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T10

1

T69

2

T419

2

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T4

1

T10

1

T28

3

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T7

1

T4

1

T10

2

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T28

1

T69

1

T349

1

auto[1]

from_1to0

auto[1]

auto[0]

40

1

T28

1

T69

1

T70

3

auto[1]

from_1to0

auto[1]

auto[1]

55

1

T7

1

T4

1

T10

1

auto[1]

from_0to1

auto[0]

auto[0]

48

1

T7

1

T10

1

T28

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T7

1

T4

1

T10

1

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T7

1

T28

1

T69

1

auto[1]

from_0to1

auto[1]

auto[1]

50

1

T7

1

T10

1

T28

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

870

1

T7

12

T4

7

T10

12

auto[1]

879

1

T7

8

T4

13

T10

17

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

408

1

T7

5

T4

3

T10

7

from_0to1

407

1

T7

5

T4

3

T10

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

868

1

T7

11

T4

11

T10

17

auto[1]

881

1

T7

9

T4

9

T10

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

892

1

T7

11

T4

10

T10

20

auto[1]

857

1

T7

9

T4

10

T10

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

46

1

T28

1

T70

2

T71

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T7

2

T4

1

T10

1

auto[0]

from_1to0

auto[1]

auto[0]

49

1

T69

1

T71

1

T61

1

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T10

3

T28

2

T69

3

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T7

1

T10

1

T28

2

auto[0]

from_0to1

auto[0]

auto[1]

39

1

T7

2

T69

1

T419

1

auto[0]

from_0to1

auto[1]

auto[0]

43

1

T7

2

T4

1

T10

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T71

1

T131

1

T61

2

auto[1]

from_1to0

auto[0]

auto[0]

53

1

T4

2

T10

3

T70

1

auto[1]

from_1to0

auto[0]

auto[1]

47

1

T28

1

T71

1

T419

1

auto[1]

from_1to0

auto[1]

auto[0]

40

1

T7

1

T70

1

T349

1

auto[1]

from_1to0

auto[1]

auto[1]

51

1

T7

2

T131

1

T61

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T10

2

T28

1

T70

1

auto[1]

from_0to1

auto[0]

auto[1]

43

1

T69

1

T71

1

T349

1

auto[1]

from_0to1

auto[1]

auto[0]

46

1

T10

2

T28

1

T69

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T4

2

T10

1

T70

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

864

1

T7

8

T4

11

T10

9

auto[1]

885

1

T7

12

T4

9

T10

20

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

423

1

T7

5

T4

6

T10

8

from_0to1

419

1

T7

5

T4

5

T10

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

849

1

T7

11

T4

12

T10

15

auto[1]

900

1

T7

9

T4

8

T10

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

857

1

T7

11

T4

11

T10

13

auto[1]

892

1

T7

9

T4

9

T10

16

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

47

1

T4

2

T10

1

T28

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T4

1

T71

1

T419

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T4

1

T10

1

T28

1

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T7

2

T4

2

T10

1

auto[0]

from_0to1

auto[0]

auto[0]

44

1

T4

1

T10

1

T28

1

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T10

1

T70

2

T71

1

auto[0]

from_0to1

auto[1]

auto[0]

53

1

T4

1

T70

2

T71

1

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T28

1

T69

1

T71

1

auto[1]

from_1to0

auto[0]

auto[0]

37

1

T7

2

T69

2

T71

2

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T69

2

T419

3

T61

4

auto[1]

from_1to0

auto[1]

auto[0]

48

1

T10

2

T28

1

T69

1

auto[1]

from_1to0

auto[1]

auto[1]

52

1

T7

1

T10

3

T28

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T7

1

T10

1

T28

1

auto[1]

from_0to1

auto[0]

auto[1]

40

1

T7

1

T4

2

T10

2

auto[1]

from_0to1

auto[1]

auto[0]

51

1

T7

2

T10

1

T70

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T7

1

T4

1

T10

1