Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	149032	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

115951

1

T6

2

T7

48

T1

320

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	136543	1			T5	2		T6	3		T7	62
values[0x0]	63754	1			T5	4		T7	29		T1	280
values[0x1]	64686	1			T5	3		T6	3		T7	32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	120677	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

144306

1

T5

2

T6

2

T7

63

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	862	1			T3	3		T4	2		T9	8
valid_sources[0x01]	890	1			T5	1		T4	3		T9	2
valid_sources[0x02]	724	1			T16	1		T25	1		T3	1
valid_sources[0x03]	911	1			T3	3		T4	2		T9	9
valid_sources[0x04]	1848	1			T1	884		T2	2		T16	1
valid_sources[0x05]	957	1			T58	1		T3	1		T67	1
valid_sources[0x06]	931	1			T16	1		T4	2		T9	2
valid_sources[0x07]	1937	1			T3	6		T9	1		T10	5
valid_sources[0x08]	1049	1			T2	15		T25	1		T4	3
valid_sources[0x09]	912	1			T3	3		T4	2		T10	3
valid_sources[0x0a]	1073	1			T2	2		T25	1		T9	2
valid_sources[0x0b]	1204	1			T4	2		T9	4		T10	7
valid_sources[0x0c]	876	1			T4	1		T9	3		T10	2
valid_sources[0x0d]	939	1			T3	2		T9	2		T10	4
valid_sources[0x0e]	1219	1			T4	1		T9	1		T10	3
valid_sources[0x0f]	1162	1			T5	1		T2	7		T3	2
valid_sources[0x10]	1058	1			T7	123		T3	14		T9	1
valid_sources[0x11]	1884	1			T14	1		T2	2		T19	29
valid_sources[0x12]	767	1			T3	11		T63	1		T4	3
valid_sources[0x13]	934	1			T2	14		T25	2		T3	1
valid_sources[0x14]	943	1			T2	4		T25	1		T3	3
valid_sources[0x15]	907	1			T3	2		T27	5		T4	1
valid_sources[0x16]	1086	1			T25	1		T4	1		T9	2
valid_sources[0x17]	835	1			T2	12		T29	3		T4	2
valid_sources[0x18]	895	1			T14	1		T58	1		T3	3
valid_sources[0x19]	1699	1			T2	3		T3	4		T9	9
valid_sources[0x1a]	891	1			T14	1		T2	1		T3	3
valid_sources[0x1b]	866	1			T10	3		T11	6		T28	7
valid_sources[0x1c]	733	1			T4	1		T9	1		T10	5
valid_sources[0x1d]	984	1			T3	6		T63	2		T4	1
valid_sources[0x1e]	1110	1			T3	3		T4	1		T9	1
valid_sources[0x1f]	1162	1			T25	1		T3	6		T9	2
valid_sources[0x20]	977	1			T3	6		T10	2		T11	3
valid_sources[0x21]	981	1			T29	5		T3	5		T63	1
valid_sources[0x22]	899	1			T2	1		T31	1		T4	2
valid_sources[0x23]	1032	1			T2	1		T3	9		T4	2
valid_sources[0x24]	774	1			T2	2		T4	1		T9	2
valid_sources[0x25]	2014	1			T3	3		T4	2		T9	2
valid_sources[0x26]	899	1			T6	1		T2	7		T3	1
valid_sources[0x27]	933	1			T2	3		T3	6		T4	4
valid_sources[0x28]	1314	1			T2	1		T31	1		T3	5
valid_sources[0x29]	1083	1			T2	9		T25	1		T3	1
valid_sources[0x2a]	863	1			T25	1		T4	2		T10	2
valid_sources[0x2b]	895	1			T3	1		T10	7		T11	6
valid_sources[0x2c]	1495	1			T5	1		T2	3		T4	4
valid_sources[0x2d]	1022	1			T2	6		T4	1		T9	9
valid_sources[0x2e]	1073	1			T2	5		T58	1		T63	2
valid_sources[0x2f]	1218	1			T17	1		T3	10		T9	2
valid_sources[0x30]	1068	1			T16	1		T29	15		T4	1
valid_sources[0x31]	1018	1			T2	3		T3	2		T9	1
valid_sources[0x32]	1286	1			T31	1		T4	3		T9	5
valid_sources[0x33]	1004	1			T4	4		T9	1		T10	2
valid_sources[0x34]	913	1			T3	14		T63	1		T27	1
valid_sources[0x35]	916	1			T16	1		T3	1		T4	6
valid_sources[0x36]	2244	1			T2	3		T9	1		T10	11
valid_sources[0x37]	702	1			T29	7		T9	1		T10	4
valid_sources[0x38]	889	1			T25	1		T3	2		T9	8
valid_sources[0x39]	1142	1			T2	1		T3	11		T4	1
valid_sources[0x3a]	965	1			T3	22		T4	3		T9	1
valid_sources[0x3b]	978	1			T4	2		T9	2		T10	7
valid_sources[0x3c]	1003	1			T16	1		T3	8		T9	3
valid_sources[0x3d]	955	1			T2	5		T63	1		T4	1
valid_sources[0x3e]	673	1			T63	1		T4	1		T9	3
valid_sources[0x3f]	2308	1			T2	3		T3	7		T4	1
valid_sources[0x40]	871	1			T2	5		T3	5		T4	2
valid_sources[0x41]	1526	1			T2	11		T3	8		T67	2
valid_sources[0x42]	861	1			T3	3		T63	3		T4	3
valid_sources[0x43]	1264	1			T2	1		T3	5		T4	3
valid_sources[0x44]	798	1			T14	1		T2	6		T4	1
valid_sources[0x45]	824	1			T15	3		T29	18		T4	1
valid_sources[0x46]	732	1			T6	2		T2	5		T63	1
valid_sources[0x47]	1173	1			T2	13		T3	1		T4	2
valid_sources[0x48]	915	1			T2	5		T3	2		T4	1
valid_sources[0x49]	1081	1			T25	1		T3	4		T4	1
valid_sources[0x4a]	969	1			T2	10		T63	1		T4	2
valid_sources[0x4b]	925	1			T16	1		T4	2		T9	3
valid_sources[0x4c]	1716	1			T2	20		T31	1		T4	1
valid_sources[0x4d]	2089	1			T20	44		T4	3		T10	4
valid_sources[0x4e]	1029	1			T9	1		T10	5		T11	7
valid_sources[0x4f]	1045	1			T17	2		T25	1		T3	1
valid_sources[0x50]	1072	1			T2	3		T31	1		T3	1
valid_sources[0x51]	900	1			T16	1		T3	1		T4	3
valid_sources[0x52]	1071	1			T58	1		T3	4		T10	9
valid_sources[0x53]	874	1			T2	5		T31	2		T4	1
valid_sources[0x54]	867	1			T2	12		T9	3		T10	3
valid_sources[0x55]	1381	1			T14	1		T63	1		T4	1
valid_sources[0x56]	1094	1			T2	7		T31	1		T4	1
valid_sources[0x57]	876	1			T31	1		T58	1		T3	5
valid_sources[0x58]	876	1			T2	2		T3	8		T27	1
valid_sources[0x59]	758	1			T3	1		T9	4		T10	2
valid_sources[0x5a]	940	1			T3	1		T9	1		T10	3
valid_sources[0x5b]	917	1			T16	1		T3	4		T4	1
valid_sources[0x5c]	734	1			T4	1		T10	3		T11	6
valid_sources[0x5d]	995	1			T6	2		T3	3		T4	3
valid_sources[0x5e]	917	1			T2	10		T11	6		T28	1
valid_sources[0x5f]	816	1			T2	7		T29	9		T10	4
valid_sources[0x60]	1032	1			T5	1		T31	1		T58	1
valid_sources[0x61]	2165	1			T16	1		T31	1		T58	1
valid_sources[0x62]	916	1			T2	8		T58	1		T3	6
valid_sources[0x63]	927	1			T58	2		T63	1		T9	2
valid_sources[0x64]	967	1			T5	1		T29	20		T31	1
valid_sources[0x65]	981	1			T5	1		T3	9		T4	3
valid_sources[0x66]	1049	1			T29	4		T58	1		T3	31
valid_sources[0x67]	841	1			T25	3		T4	1		T9	1
valid_sources[0x68]	1019	1			T25	1		T3	2		T4	2
valid_sources[0x69]	1403	1			T2	2		T3	1		T63	1
valid_sources[0x6a]	1875	1			T3	1		T4	1		T9	5
valid_sources[0x6b]	1104	1			T3	5		T4	4		T9	3
valid_sources[0x6c]	817	1			T31	1		T3	14		T4	1
valid_sources[0x6d]	1215	1			T5	1		T3	2		T4	3
valid_sources[0x6e]	879	1			T25	1		T3	1		T4	2
valid_sources[0x6f]	891	1			T3	9		T9	4		T10	4
valid_sources[0x70]	881	1			T4	2		T9	4		T10	2
valid_sources[0x71]	1004	1			T16	1		T25	2		T3	1
valid_sources[0x72]	1017	1			T2	2		T3	2		T4	2
valid_sources[0x73]	806	1			T2	5		T31	1		T3	5
valid_sources[0x74]	782	1			T29	21		T3	1		T4	1
valid_sources[0x75]	1052	1			T25	1		T63	1		T4	1
valid_sources[0x76]	969	1			T5	1		T29	4		T31	2
valid_sources[0x77]	884	1			T3	4		T9	3		T10	5
valid_sources[0x78]	808	1			T14	2		T3	12		T9	5
valid_sources[0x79]	825	1			T3	3		T4	3		T9	4
valid_sources[0x7a]	926	1			T5	1		T9	2		T10	5
valid_sources[0x7b]	797	1			T2	3		T3	3		T27	2
valid_sources[0x7c]	1119	1			T2	3		T63	1		T4	3
valid_sources[0x7d]	884	1			T3	1		T9	2		T10	3
valid_sources[0x7e]	843	1			T9	5		T10	2		T11	3
valid_sources[0x7f]	736	1			T63	1		T4	2		T9	2
valid_sources[0x80]	886	1			T2	15		T25	1		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62063

1

T6

2

T7

28

T1

159

values[0x0]

all_enables

biggest_size

31375

1

T7

15

T1

103

T14

1

values[0x1]

all_enables

biggest_size

22513

1

T7

5

T1

58

T2

36