Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T1,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T16,T10,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T16,T10,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T16,T10,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T10,T28
1	0	Covered	T7,T1,T14
1	1	Covered	T16,T10,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T10,T28
0	1	Covered	T98,T101,T102
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T10,T28
0	1	Covered	T16,T10,T28
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T10,T28
1	-	Covered	T16,T10,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T10,T28
DetectSt	168	Covered	T16,T10,T28
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T16,T10,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T10,T28
DebounceSt->IdleSt	163	Covered	T13,T55,T57
DetectSt->IdleSt	186	Covered	T98,T101,T102
DetectSt->StableSt	191	Covered	T16,T10,T28
IdleSt->DebounceSt	148	Covered	T16,T10,T28
StableSt->IdleSt	206	Covered	T16,T10,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T10,T28
0	1	Covered	T16,T10,T28
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T10,T28
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T10,T28
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T36,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T10,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T55,T57
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T10,T28
DetectSt	-	-	-	-	1	-	-	Covered	T98,T101,T102
DetectSt	-	-	-	-	0	1	-	Covered	T16,T10,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T10,T28
StableSt	-	-	-	-	-	-	0	Covered	T16,T10,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	325	0	0
CntIncr_A	8063858	395765	0	0
CntNoWrap_A	8063858	7444619	0	0
DetectStDropOut_A	8063858	4	0	0
DetectedOut_A	8063858	909	0	0
DetectedPulseOut_A	8063858	140	0	0
DisabledIdleSt_A	8063858	7041644	0	0
DisabledNoDetection_A	8063858	7043949	0	0
EnterDebounceSt_A	8063858	185	0	0
EnterDetectSt_A	8063858	144	0	0
EnterStableSt_A	8063858	140	0	0
PulseIsPulse_A	8063858	140	0	0
StayInStableSt	8063858	769	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8063858	6518	0	0
gen_low_level_sva.LowLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	140	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	325	0	0
T10	0	4	0	0
T13	0	3	0	0
T16	1709	2	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T25	496	0	0	0
T28	0	2	0	0
T29	5170	0	0	0
T31	929	0	0	0
T35	0	1	0	0
T50	0	2	0	0
T52	0	6	0	0
T55	0	5	0	0
T56	0	4	0	0
T57	0	1	0	0
T58	421	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	395765	0	0
T10	0	158	0	0
T13	0	163	0	0
T16	1709	97	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T25	496	0	0	0
T28	0	90	0	0
T29	5170	0	0	0
T31	929	0	0	0
T35	0	72	0	0
T50	0	73	0	0
T52	0	115	0	0
T55	0	94	0	0
T56	0	64	0	0
T57	0	15	0	0
T58	421	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444619	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	505	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	4	0	0
T98	16609	1	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T106	543	0	0	0
T107	519	0	0	0
T108	12455	0	0	0
T109	538	0	0	0
T110	504	0	0	0
T111	7300	0	0	0
T112	25370	0	0	0
T113	430	0	0	0
T114	1104	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	909	0	0
T10	0	4	0	0
T13	0	5	0	0
T16	1709	9	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T25	496	0	0	0
T28	0	7	0	0
T29	5170	0	0	0
T31	929	0	0	0
T34	0	13	0	0
T50	0	7	0	0
T52	0	18	0	0
T55	0	22	0	0
T56	0	7	0	0
T58	421	0	0	0
T117	0	6	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	140	0	0
T10	0	2	0	0
T13	0	1	0	0
T16	1709	1	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T25	496	0	0	0
T28	0	1	0	0
T29	5170	0	0	0
T31	929	0	0	0
T34	0	2	0	0
T50	0	1	0	0
T52	0	3	0	0
T55	0	2	0	0
T56	0	2	0	0
T58	421	0	0	0
T117	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7041644	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	365	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7043949	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	367	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	185	0	0
T10	0	2	0	0
T13	0	2	0	0
T16	1709	1	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T25	496	0	0	0
T28	0	1	0	0
T29	5170	0	0	0
T31	929	0	0	0
T35	0	1	0	0
T50	0	1	0	0
T52	0	3	0	0
T55	0	3	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	421	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	144	0	0
T10	0	2	0	0
T13	0	1	0	0
T16	1709	1	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T25	496	0	0	0
T28	0	1	0	0
T29	5170	0	0	0
T31	929	0	0	0
T34	0	2	0	0
T50	0	1	0	0
T52	0	3	0	0
T55	0	2	0	0
T56	0	2	0	0
T58	421	0	0	0
T117	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	140	0	0
T10	0	2	0	0
T13	0	1	0	0
T16	1709	1	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T25	496	0	0	0
T28	0	1	0	0
T29	5170	0	0	0
T31	929	0	0	0
T34	0	2	0	0
T50	0	1	0	0
T52	0	3	0	0
T55	0	2	0	0
T56	0	2	0	0
T58	421	0	0	0
T117	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	140	0	0
T10	0	2	0	0
T13	0	1	0	0
T16	1709	1	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T25	496	0	0	0
T28	0	1	0	0
T29	5170	0	0	0
T31	929	0	0	0
T34	0	2	0	0
T50	0	1	0	0
T52	0	3	0	0
T55	0	2	0	0
T56	0	2	0	0
T58	421	0	0	0
T117	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	769	0	0
T10	0	2	0	0
T13	0	4	0	0
T16	1709	8	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T25	496	0	0	0
T28	0	6	0	0
T29	5170	0	0	0
T31	929	0	0	0
T34	0	11	0	0
T50	0	6	0	0
T52	0	15	0	0
T55	0	20	0	0
T56	0	5	0	0
T58	421	0	0	0
T117	0	5	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6518	0	0
T1	12650	34	0	0
T2	23681	14	0	0
T7	504	7	0	0
T14	413	2	0	0
T15	425	2	0	0
T16	1709	3	0	0
T17	405	0	0	0
T18	885	4	0	0
T19	428	3	0	0
T20	499	7	0	0
T21	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	140	0	0
T10	0	2	0	0
T13	0	1	0	0
T16	1709	1	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T25	496	0	0	0
T28	0	1	0	0
T29	5170	0	0	0
T31	929	0	0	0
T34	0	2	0	0
T50	0	1	0	0
T52	0	3	0	0
T55	0	2	0	0
T56	0	2	0	0
T58	421	0	0	0
T117	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T1,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T12,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T4,T12,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T12,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T13
1	0	Covered	T7,T1,T14
1	1	Covered	T4,T12,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T12,T13
0	1	Covered	T60,T78,T89
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T12,T13
0	1	Unreachable
1	0	Covered	T4,T12,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T12,T13
DetectSt	168	Covered	T4,T12,T13
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T4,T12,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T12,T13
DebounceSt->IdleSt	163	Covered	T13,T36,T77
DetectSt->IdleSt	186	Covered	T60,T78,T89
DetectSt->StableSt	191	Covered	T4,T12,T13
IdleSt->DebounceSt	148	Covered	T4,T12,T13
StableSt->IdleSt	206	Covered	T4,T12,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T12,T13
0	1	Covered	T4,T12,T13
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T13
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T12,T13
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T36,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T12,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T77,T119
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T12,T13
DetectSt	-	-	-	-	1	-	-	Covered	T60,T78,T89
DetectSt	-	-	-	-	0	1	-	Covered	T4,T12,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T12,T13
StableSt	-	-	-	-	-	-	0	Covered	T4,T12,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	151	0	0
CntIncr_A	8063858	50386	0	0
CntNoWrap_A	8063858	7444793	0	0
DetectStDropOut_A	8063858	8	0	0
DetectedOut_A	8063858	76609	0	0
DetectedPulseOut_A	8063858	46	0	0
DisabledIdleSt_A	8063858	6782395	0	0
DisabledNoDetection_A	8063858	6784758	0	0
EnterDebounceSt_A	8063858	99	0	0
EnterDetectSt_A	8063858	54	0	0
EnterStableSt_A	8063858	46	0	0
PulseIsPulse_A	8063858	46	0	0
StayInStableSt	8063858	76563	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8063858	6518	0	0
gen_low_level_sva.LowLevelEvent_A	8063858	7447309	0	0
gen_sticky_sva.StableStDropOut_A	8063858	6583	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	151	0	0
T4	5277	2	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	2	0	0
T13	0	3	0	0
T36	0	1	0	0
T59	4405	0	0	0
T60	0	2	0	0
T61	0	4	0	0
T62	0	2	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	50386	0	0
T4	5277	83	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	79	0	0
T13	0	28	0	0
T36	0	17	0	0
T59	4405	0	0	0
T60	0	69	0	0
T61	0	112	0	0
T62	0	88	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T76	0	95	0	0
T77	0	32	0	0
T78	0	174	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444793	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	8	0	0
T34	18289	0	0	0
T35	6318	0	0	0
T60	621	1	0	0
T75	10843	0	0	0
T78	0	1	0	0
T89	0	2	0	0
T117	695	0	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	2	0	0
T127	491	0	0	0
T128	422	0	0	0
T129	451	0	0	0
T130	758	0	0	0
T131	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	76609	0	0
T4	5277	121	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	62	0	0
T13	0	32	0	0
T59	4405	0	0	0
T61	0	280	0	0
T62	0	83	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T76	0	48	0	0
T78	0	1	0	0
T87	0	31	0	0
T118	0	51	0	0
T119	0	636	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	46	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	1	0	0
T13	0	1	0	0
T59	4405	0	0	0
T61	0	2	0	0
T62	0	1	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T76	0	1	0	0
T78	0	1	0	0
T87	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6782395	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6784758	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	99	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	1	0	0
T13	0	2	0	0
T36	0	2	0	0
T59	4405	0	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	54	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	1	0	0
T13	0	1	0	0
T59	4405	0	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T76	0	1	0	0
T78	0	2	0	0
T87	0	1	0	0
T118	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	46	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	1	0	0
T13	0	1	0	0
T59	4405	0	0	0
T61	0	2	0	0
T62	0	1	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T76	0	1	0	0
T78	0	1	0	0
T87	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	46	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	1	0	0
T13	0	1	0	0
T59	4405	0	0	0
T61	0	2	0	0
T62	0	1	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T76	0	1	0	0
T78	0	1	0	0
T87	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	76563	0	0
T4	5277	120	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	61	0	0
T13	0	31	0	0
T59	4405	0	0	0
T61	0	278	0	0
T62	0	82	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T76	0	47	0	0
T87	0	30	0	0
T118	0	50	0	0
T119	0	635	0	0
T120	0	41	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6518	0	0
T1	12650	34	0	0
T2	23681	14	0	0
T7	504	7	0	0
T14	413	2	0	0
T15	425	2	0	0
T16	1709	3	0	0
T17	405	0	0	0
T18	885	4	0	0
T19	428	3	0	0
T20	499	7	0	0
T21	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6583	0	0
T4	5277	99	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	63	0	0
T13	0	362	0	0
T59	4405	0	0	0
T61	0	237	0	0
T62	0	30	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T76	0	45	0	0
T78	0	80	0	0
T87	0	193	0	0
T118	0	421	0	0
T119	0	107	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T7,T14,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T7,T14,T15
1	1	Covered	T7,T14,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T12,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T4,T12,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T13,T60

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T13
1	0	Covered	T7,T14,T15
1	1	Covered	T4,T12,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T13,T60
0	1	Covered	T62,T87,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T13,T60
0	1	Unreachable
1	0	Covered	T4,T13,T60

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T12,T13
DetectSt	168	Covered	T4,T13,T60
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T4,T13,T60

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T13,T60
DebounceSt->IdleSt	163	Covered	T12,T61,T36
DetectSt->IdleSt	186	Covered	T62,T87,T88
DetectSt->StableSt	191	Covered	T4,T13,T60
IdleSt->DebounceSt	148	Covered	T4,T12,T13
StableSt->IdleSt	206	Covered	T4,T13,T60

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T12,T13
0	1	Covered	T4,T12,T13
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T13,T60
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T12,T13
IdleSt	0	-	-	-	-	-	-	Covered	T7,T14,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T36,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T13,T60
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T61,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T12,T13
DetectSt	-	-	-	-	1	-	-	Covered	T62,T87,T88
DetectSt	-	-	-	-	0	1	-	Covered	T4,T13,T60
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T13,T60
StableSt	-	-	-	-	-	-	0	Covered	T4,T13,T60
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	164	0	0
CntIncr_A	8063858	183232	0	0
CntNoWrap_A	8063858	7444780	0	0
DetectStDropOut_A	8063858	15	0	0
DetectedOut_A	8063858	306043	0	0
DetectedPulseOut_A	8063858	45	0	0
DisabledIdleSt_A	8063858	6782395	0	0
DisabledNoDetection_A	8063858	6784758	0	0
EnterDebounceSt_A	8063858	106	0	0
EnterDetectSt_A	8063858	60	0	0
EnterStableSt_A	8063858	45	0	0
PulseIsPulse_A	8063858	45	0	0
StayInStableSt	8063858	305998	0	0
gen_high_level_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_sticky_sva.StableStDropOut_A	8063858	54883	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	164	0	0
T4	5277	2	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	1	0	0
T13	0	2	0	0
T36	0	1	0	0
T59	4405	0	0	0
T60	0	2	0	0
T61	0	5	0	0
T62	0	2	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	183232	0	0
T4	5277	73	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	86	0	0
T13	0	72	0	0
T36	0	17	0	0
T59	4405	0	0	0
T60	0	75	0	0
T61	0	246	0	0
T62	0	28	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T76	0	69	0	0
T77	0	74	0	0
T78	0	160	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444780	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	15	0	0
T62	10299	1	0	0
T87	0	1	0	0
T88	0	2	0	0
T132	0	3	0	0
T133	0	2	0	0
T134	0	4	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	526	0	0	0
T138	501	0	0	0
T139	403	0	0	0
T140	432	0	0	0
T141	501	0	0	0
T142	742	0	0	0
T143	494	0	0	0
T144	30192	0	0	0
T145	786	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	306043	0	0
T4	5277	103	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	364	0	0
T59	4405	0	0	0
T60	0	71	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T77	0	35	0	0
T93	0	129	0	0
T119	0	429	0	0
T120	0	34	0	0
T121	0	318	0	0
T122	0	16	0	0
T123	0	251	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	45	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	1	0	0
T59	4405	0	0	0
T60	0	1	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T77	0	1	0	0
T93	0	1	0	0
T119	0	2	0	0
T120	0	1	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6782395	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6784758	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	106	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	1	0	0
T13	0	1	0	0
T36	0	2	0	0
T59	4405	0	0	0
T60	0	1	0	0
T61	0	5	0	0
T62	0	1	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	60	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	1	0	0
T59	4405	0	0	0
T60	0	1	0	0
T62	0	1	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T77	0	1	0	0
T87	0	1	0	0
T93	0	1	0	0
T119	0	2	0	0
T120	0	1	0	0
T121	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	45	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	1	0	0
T59	4405	0	0	0
T60	0	1	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T77	0	1	0	0
T93	0	1	0	0
T119	0	2	0	0
T120	0	1	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	45	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	1	0	0
T59	4405	0	0	0
T60	0	1	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T77	0	1	0	0
T93	0	1	0	0
T119	0	2	0	0
T120	0	1	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	305998	0	0
T4	5277	102	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	363	0	0
T59	4405	0	0	0
T60	0	70	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T77	0	34	0	0
T93	0	128	0	0
T119	0	427	0	0
T120	0	33	0	0
T121	0	317	0	0
T122	0	15	0	0
T123	0	250	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	54883	0	0
T4	5277	131	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	89	0	0
T59	4405	0	0	0
T60	0	29	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T77	0	27	0	0
T93	0	50	0	0
T119	0	47452	0	0
T120	0	47	0	0
T121	0	478	0	0
T122	0	117	0	0
T123	0	122	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T7,T1,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T12,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T4,T12,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T13,T60

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T13
1	0	Covered	T7,T1,T14
1	1	Covered	T4,T12,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T13,T60
0	1	Covered	T61,T76,T77
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T13,T60
0	1	Unreachable
1	0	Covered	T4,T13,T60

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T12,T13
DetectSt	168	Covered	T4,T13,T60
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T4,T13,T60

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T13,T60
DebounceSt->IdleSt	163	Covered	T12,T36,T79
DetectSt->IdleSt	186	Covered	T61,T76,T77
DetectSt->StableSt	191	Covered	T4,T13,T60
IdleSt->DebounceSt	148	Covered	T4,T12,T13
StableSt->IdleSt	206	Covered	T4,T13,T60

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T12,T13
0	1	Covered	T4,T12,T13
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T13,T60
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T12,T13
IdleSt	0	-	-	-	-	-	-	Covered	T7,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T36,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T13,T60
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T119,T123
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T12,T13
DetectSt	-	-	-	-	1	-	-	Covered	T61,T76,T77
DetectSt	-	-	-	-	0	1	-	Covered	T4,T13,T60
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T13,T60
StableSt	-	-	-	-	-	-	0	Covered	T4,T13,T60
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	147	0	0
CntIncr_A	8063858	52264	0	0
CntNoWrap_A	8063858	7444797	0	0
DetectStDropOut_A	8063858	9	0	0
DetectedOut_A	8063858	7744	0	0
DetectedPulseOut_A	8063858	46	0	0
DisabledIdleSt_A	8063858	6782395	0	0
DisabledNoDetection_A	8063858	6784758	0	0
EnterDebounceSt_A	8063858	94	0	0
EnterDetectSt_A	8063858	55	0	0
EnterStableSt_A	8063858	46	0	0
PulseIsPulse_A	8063858	46	0	0
StayInStableSt	8063858	7698	0	0
gen_high_event_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_high_level_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_sticky_sva.StableStDropOut_A	8063858	121172	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	147	0	0
T4	5277	2	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	1	0	0
T13	0	2	0	0
T36	0	1	0	0
T59	4405	0	0	0
T60	0	2	0	0
T61	0	6	0	0
T62	0	2	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T76	0	2	0	0
T77	0	2	0	0
T78	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	52264	0	0
T4	5277	72	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	35	0	0
T13	0	63	0	0
T36	0	18	0	0
T59	4405	0	0	0
T60	0	21	0	0
T61	0	179	0	0
T62	0	79	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T76	0	10	0	0
T77	0	26	0	0
T78	0	11	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444797	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	9	0	0
T61	68032	1	0	0
T62	10299	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T137	526	0	0	0
T138	501	0	0	0
T139	403	0	0	0
T140	432	0	0	0
T141	501	0	0	0
T142	742	0	0	0
T143	494	0	0	0
T144	30192	0	0	0
T146	0	2	0	0
T147	0	1	0	0
T148	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7744	0	0
T4	5277	201	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	280	0	0
T59	4405	0	0	0
T60	0	9	0	0
T61	0	146	0	0
T62	0	74	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T78	0	29	0	0
T87	0	148	0	0
T118	0	88	0	0
T119	0	493	0	0
T120	0	5	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	46	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	1	0	0
T59	4405	0	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T78	0	1	0	0
T87	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6782395	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6784758	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	94	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	1	0	0
T13	0	1	0	0
T36	0	2	0	0
T59	4405	0	0	0
T60	0	1	0	0
T61	0	3	0	0
T62	0	1	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	55	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	1	0	0
T59	4405	0	0	0
T60	0	1	0	0
T61	0	3	0	0
T62	0	1	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T87	0	1	0	0
T118	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	46	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	1	0	0
T59	4405	0	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T78	0	1	0	0
T87	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	46	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	1	0	0
T59	4405	0	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T78	0	1	0	0
T87	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7698	0	0
T4	5277	200	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	279	0	0
T59	4405	0	0	0
T60	0	8	0	0
T61	0	144	0	0
T62	0	73	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T78	0	28	0	0
T87	0	147	0	0
T118	0	87	0	0
T119	0	492	0	0
T120	0	4	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	121172	0	0
T4	5277	40	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	196	0	0
T59	4405	0	0	0
T60	0	159	0	0
T61	0	262	0	0
T62	0	55	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T78	0	288	0	0
T87	0	30	0	0
T118	0	382	0	0
T119	0	284	0	0
T120	0	34	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T40,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T40,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T40,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T39,T40
1	0	Covered	T5,T6,T7
1	1	Covered	T40,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T35,T36
0	1	Covered	T149
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T35,T36
0	1	Covered	T37,T41,T150
1	0	Covered	T36

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T35,T36
1	-	Covered	T37,T41,T150

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T35,T36
DetectSt	168	Covered	T40,T35,T36
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T40,T35,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T35,T36
DebounceSt->IdleSt	163	Covered	T79,T151
DetectSt->IdleSt	186	Covered	T149
DetectSt->StableSt	191	Covered	T40,T35,T36
IdleSt->DebounceSt	148	Covered	T40,T35,T36
StableSt->IdleSt	206	Covered	T35,T36,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T35,T36
0	1	Covered	T40,T35,T36
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T35,T36
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T35,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T151
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T149
DetectSt	-	-	-	-	0	1	-	Covered	T40,T35,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T37,T41
StableSt	-	-	-	-	-	-	0	Covered	T40,T35,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	76	0	0
CntIncr_A	8063858	30066	0	0
CntNoWrap_A	8063858	7444868	0	0
DetectStDropOut_A	8063858	1	0	0
DetectedOut_A	8063858	15758	0	0
DetectedPulseOut_A	8063858	36	0	0
DisabledIdleSt_A	8063858	7118448	0	0
DisabledNoDetection_A	8063858	7120764	0	0
EnterDebounceSt_A	8063858	39	0	0
EnterDetectSt_A	8063858	37	0	0
EnterStableSt_A	8063858	36	0	0
PulseIsPulse_A	8063858	36	0	0
StayInStableSt	8063858	15696	0	0
gen_high_level_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	76	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	650	2	0	0
T41	0	8	0	0
T43	0	2	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T150	0	6	0	0
T152	0	2	0	0
T153	0	2	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	30066	0	0
T35	0	97	0	0
T36	0	27	0	0
T37	0	92	0	0
T38	0	48	0	0
T40	650	36	0	0
T41	0	320	0	0
T43	0	44	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T150	0	123	0	0
T152	0	7428	0	0
T153	0	28	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444868	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	1	0	0
T149	7784	1	0	0
T158	688	0	0	0
T159	12783	0	0	0
T160	1258	0	0	0
T161	495	0	0	0
T162	502	0	0	0
T163	662	0	0	0
T164	425	0	0	0
T165	419	0	0	0
T166	18686	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	15758	0	0
T35	0	136	0	0
T36	0	16	0	0
T37	0	13	0	0
T38	0	42	0	0
T40	650	88	0	0
T41	0	177	0	0
T43	0	43	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T150	0	124	0	0
T152	0	13265	0	0
T153	0	198	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	36	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	650	1	0	0
T41	0	4	0	0
T43	0	1	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T150	0	3	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7118448	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7120764	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	39	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	650	1	0	0
T41	0	4	0	0
T43	0	1	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T150	0	3	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	37	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	650	1	0	0
T41	0	4	0	0
T43	0	1	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T150	0	3	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	36	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	650	1	0	0
T41	0	4	0	0
T43	0	1	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T150	0	3	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	36	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	650	1	0	0
T41	0	4	0	0
T43	0	1	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T150	0	3	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	15696	0	0
T35	0	134	0	0
T36	0	15	0	0
T37	0	12	0	0
T38	0	40	0	0
T40	650	86	0	0
T41	0	171	0	0
T43	0	41	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T150	0	120	0	0
T152	0	13263	0	0
T153	0	196	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	9	0	0
T37	1207	1	0	0
T41	0	2	0	0
T101	0	1	0	0
T150	0	2	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	8989	0	0	0
T171	495	0	0	0
T172	10159	0	0	0
T173	19013	0	0	0
T174	522	0	0	0
T175	432	0	0	0
T176	488	0	0	0
T177	58481	0	0	0
T178	524	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T8,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T8,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T8,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T39,T40
1	0	Covered	T7,T1,T14
1	1	Covered	T8,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T39,T40
0	1	Covered	T179,T180
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T39,T40
0	1	Covered	T40,T35,T38
1	0	Covered	T36

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T39,T40
1	-	Covered	T40,T35,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T39,T40
DetectSt	168	Covered	T8,T39,T40
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T8,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T39,T40
DebounceSt->IdleSt	163	Covered	T79,T181,T182
DetectSt->IdleSt	186	Covered	T179,T180
DetectSt->StableSt	191	Covered	T8,T39,T40
IdleSt->DebounceSt	148	Covered	T8,T39,T40
StableSt->IdleSt	206	Covered	T39,T40,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T39,T40
0	1	Covered	T8,T39,T40
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T39,T40
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T181,T183,T184
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T39,T40
DetectSt	-	-	-	-	1	-	-	Covered	T179,T180
DetectSt	-	-	-	-	0	1	-	Covered	T8,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T35,T36
StableSt	-	-	-	-	-	-	0	Covered	T8,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	141	0	0
CntIncr_A	8063858	287666	0	0
CntNoWrap_A	8063858	7444803	0	0
DetectStDropOut_A	8063858	2	0	0
DetectedOut_A	8063858	126826	0	0
DetectedPulseOut_A	8063858	65	0	0
DisabledIdleSt_A	8063858	6582357	0	0
DisabledNoDetection_A	8063858	6584656	0	0
EnterDebounceSt_A	8063858	75	0	0
EnterDetectSt_A	8063858	67	0	0
EnterStableSt_A	8063858	65	0	0
PulseIsPulse_A	8063858	65	0	0
StayInStableSt	8063858	126734	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8063858	2365	0	0
gen_low_level_sva.LowLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	141	0	0
T8	550	2	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T28	9269	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T38	0	2	0	0
T39	0	4	0	0
T40	0	2	0	0
T41	0	4	0	0
T42	0	2	0	0
T44	0	2	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T152	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	287666	0	0
T8	550	32	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T28	9269	0	0	0
T35	0	97	0	0
T36	0	27	0	0
T38	0	48	0	0
T39	0	101	0	0
T40	0	36	0	0
T41	0	174	0	0
T42	0	88	0	0
T44	0	35	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T152	0	7428	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444803	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	2	0	0
T179	621	1	0	0
T180	0	1	0	0
T185	17680	0	0	0
T186	773	0	0	0
T187	527	0	0	0
T188	409	0	0	0
T189	426	0	0	0
T190	833	0	0	0
T191	855	0	0	0
T192	543	0	0	0
T193	459	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	126826	0	0
T8	550	109	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T28	9269	0	0	0
T35	0	43	0	0
T36	0	17	0	0
T38	0	31	0	0
T39	0	101	0	0
T40	0	80	0	0
T41	0	257	0	0
T42	0	341	0	0
T44	0	90	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T152	0	7167	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	65	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T28	9269	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T152	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6582357	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6584656	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	75	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T28	9269	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T152	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	67	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T28	9269	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T152	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	65	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T28	9269	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T152	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	65	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T28	9269	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T152	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	126734	0	0
T8	550	107	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T28	9269	0	0	0
T35	0	42	0	0
T36	0	16	0	0
T38	0	30	0	0
T39	0	97	0	0
T40	0	79	0	0
T41	0	255	0	0
T42	0	339	0	0
T44	0	88	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T152	0	7166	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	2365	0	0
T1	12650	0	0	0
T2	23681	0	0	0
T3	0	9	0	0
T7	504	5	0	0
T14	413	1	0	0
T15	425	3	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	3	0	0
T20	499	6	0	0
T21	0	5	0	0
T25	0	5	0	0
T26	0	4	0	0
T58	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	37	0	0
T35	0	1	0	0
T38	0	1	0	0
T40	650	1	0	0
T41	0	2	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T122	0	1	0	0
T150	0	3	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T194	0	1	0	0
T195	0	2	0	0