Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T34,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T34,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T34,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T36,T37
1	0	Covered	T5,T6,T7
1	1	Covered	T34,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T36,T37
0	1	Covered	T85,T86,T184
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T36,T37
0	1	Covered	T37,T38,T41
1	0	Covered	T36

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T36,T37
1	-	Covered	T37,T38,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T36,T37
DetectSt	168	Covered	T34,T36,T37
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T34,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T36,T37
DebounceSt->IdleSt	163	Covered	T79,T84
DetectSt->IdleSt	186	Covered	T85,T86,T184
DetectSt->StableSt	191	Covered	T34,T36,T37
IdleSt->DebounceSt	148	Covered	T34,T36,T37
StableSt->IdleSt	206	Covered	T34,T36,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T34,T36,T37
0	1	Covered	T34,T36,T37
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T36,T37
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T36,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T84
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T36,T37
DetectSt	-	-	-	-	1	-	-	Covered	T85,T86,T184
DetectSt	-	-	-	-	0	1	-	Covered	T34,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T37,T38
StableSt	-	-	-	-	-	-	0	Covered	T34,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	86	0	0
CntIncr_A	8063858	38386	0	0
CntNoWrap_A	8063858	7444858	0	0
DetectStDropOut_A	8063858	3	0	0
DetectedOut_A	8063858	97213	0	0
DetectedPulseOut_A	8063858	39	0	0
DisabledIdleSt_A	8063858	7118760	0	0
DisabledNoDetection_A	8063858	7121074	0	0
EnterDebounceSt_A	8063858	44	0	0
EnterDetectSt_A	8063858	42	0	0
EnterStableSt_A	8063858	39	0	0
PulseIsPulse_A	8063858	39	0	0
StayInStableSt	8063858	97156	0	0
gen_high_level_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	86	0	0
T34	18289	2	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	0	2	0	0
T41	0	2	0	0
T44	0	2	0	0
T61	68032	0	0	0
T62	10299	0	0	0
T79	0	1	0	0
T117	695	0	0	0
T129	451	0	0	0
T130	758	0	0	0
T131	502	0	0	0
T137	526	0	0	0
T138	501	0	0	0
T150	0	2	0	0
T153	0	2	0	0
T194	0	2	0	0
T196	407	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	38386	0	0
T34	18289	19	0	0
T36	0	27	0	0
T37	0	184	0	0
T38	0	48	0	0
T41	0	90	0	0
T44	0	35	0	0
T61	68032	0	0	0
T62	10299	0	0	0
T79	0	21	0	0
T117	695	0	0	0
T129	451	0	0	0
T130	758	0	0	0
T131	502	0	0	0
T137	526	0	0	0
T138	501	0	0	0
T150	0	41	0	0
T153	0	28	0	0
T194	0	87	0	0
T196	407	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444858	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	3	0	0
T85	36430	1	0	0
T86	0	1	0	0
T88	2680	0	0	0
T184	0	1	0	0
T197	835	0	0	0
T198	1237	0	0	0
T199	522	0	0	0
T200	423	0	0	0
T201	641	0	0	0
T202	9188	0	0	0
T203	15732	0	0	0
T204	4967	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	97213	0	0
T34	18289	132	0	0
T36	0	17	0	0
T37	0	188	0	0
T38	0	122	0	0
T41	0	148	0	0
T44	0	41	0	0
T61	68032	0	0	0
T62	10299	0	0	0
T117	695	0	0	0
T129	451	0	0	0
T130	758	0	0	0
T131	502	0	0	0
T137	526	0	0	0
T138	501	0	0	0
T150	0	275	0	0
T153	0	44	0	0
T194	0	187	0	0
T195	0	92810	0	0
T196	407	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	39	0	0
T34	18289	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T61	68032	0	0	0
T62	10299	0	0	0
T117	695	0	0	0
T129	451	0	0	0
T130	758	0	0	0
T131	502	0	0	0
T137	526	0	0	0
T138	501	0	0	0
T150	0	1	0	0
T153	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0
T196	407	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7118760	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7121074	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	44	0	0
T34	18289	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T61	68032	0	0	0
T62	10299	0	0	0
T79	0	1	0	0
T117	695	0	0	0
T129	451	0	0	0
T130	758	0	0	0
T131	502	0	0	0
T137	526	0	0	0
T138	501	0	0	0
T150	0	1	0	0
T153	0	1	0	0
T194	0	1	0	0
T196	407	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	42	0	0
T34	18289	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T61	68032	0	0	0
T62	10299	0	0	0
T117	695	0	0	0
T129	451	0	0	0
T130	758	0	0	0
T131	502	0	0	0
T137	526	0	0	0
T138	501	0	0	0
T150	0	1	0	0
T153	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0
T196	407	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	39	0	0
T34	18289	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T61	68032	0	0	0
T62	10299	0	0	0
T117	695	0	0	0
T129	451	0	0	0
T130	758	0	0	0
T131	502	0	0	0
T137	526	0	0	0
T138	501	0	0	0
T150	0	1	0	0
T153	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0
T196	407	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	39	0	0
T34	18289	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T61	68032	0	0	0
T62	10299	0	0	0
T117	695	0	0	0
T129	451	0	0	0
T130	758	0	0	0
T131	502	0	0	0
T137	526	0	0	0
T138	501	0	0	0
T150	0	1	0	0
T153	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0
T196	407	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	97156	0	0
T34	18289	130	0	0
T36	0	16	0	0
T37	0	185	0	0
T38	0	121	0	0
T41	0	147	0	0
T44	0	39	0	0
T61	68032	0	0	0
T62	10299	0	0	0
T117	695	0	0	0
T129	451	0	0	0
T130	758	0	0	0
T131	502	0	0	0
T137	526	0	0	0
T138	501	0	0	0
T150	0	274	0	0
T153	0	43	0	0
T194	0	185	0	0
T195	0	92809	0	0
T196	407	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	20	0	0
T37	1207	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T83	0	1	0	0
T150	0	1	0	0
T153	0	1	0	0
T167	0	1	0	0
T170	8989	0	0	0
T171	495	0	0	0
T172	10159	0	0	0
T173	19013	0	0	0
T174	522	0	0	0
T175	432	0	0	0
T176	488	0	0	0
T177	58481	0	0	0
T178	524	0	0	0
T182	0	1	0	0
T195	0	1	0	0
T205	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T40,T34,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T40,T34,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T40,T36,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T34
1	0	Covered	T6,T7,T1
1	1	Covered	T40,T34,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T36,T43
0	1	Covered	T82,T83,T206
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T36,T43
0	1	Covered	T40,T37,T44
1	0	Covered	T36

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T36,T43
1	-	Covered	T40,T37,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T34,T36
DetectSt	168	Covered	T40,T36,T43
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T40,T36,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T36,T43
DebounceSt->IdleSt	163	Covered	T34,T79,T167
DetectSt->IdleSt	186	Covered	T82,T83,T206
DetectSt->StableSt	191	Covered	T40,T36,T43
IdleSt->DebounceSt	148	Covered	T40,T34,T36
StableSt->IdleSt	206	Covered	T40,T36,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T34,T36
0	1	Covered	T40,T34,T36
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T36,T43
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T34,T36
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T36,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T167,T169
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T34,T36
DetectSt	-	-	-	-	1	-	-	Covered	T82,T83,T206
DetectSt	-	-	-	-	0	1	-	Covered	T40,T36,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T36,T37
StableSt	-	-	-	-	-	-	0	Covered	T40,T36,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	148	0	0
CntIncr_A	8063858	172416	0	0
CntNoWrap_A	8063858	7444796	0	0
DetectStDropOut_A	8063858	3	0	0
DetectedOut_A	8063858	51778	0	0
DetectedPulseOut_A	8063858	69	0	0
DisabledIdleSt_A	8063858	6967850	0	0
DisabledNoDetection_A	8063858	6970157	0	0
EnterDebounceSt_A	8063858	77	0	0
EnterDetectSt_A	8063858	72	0	0
EnterStableSt_A	8063858	69	0	0
PulseIsPulse_A	8063858	69	0	0
StayInStableSt	8063858	51680	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8063858	2699	0	0
gen_low_level_sva.LowLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	39	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	148	0	0
T34	0	1	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	0	4	0	0
T40	650	2	0	0
T41	0	8	0	0
T43	0	2	0	0
T44	0	2	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T152	0	2	0	0
T153	0	4	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	172416	0	0
T34	0	19	0	0
T36	0	27	0	0
T37	0	184	0	0
T38	0	96	0	0
T40	650	36	0	0
T41	0	273	0	0
T43	0	44	0	0
T44	0	35	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T152	0	7428	0	0
T153	0	56	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444796	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	3	0	0
T82	550	1	0	0
T83	825	1	0	0
T205	12682	0	0	0
T206	0	1	0	0
T207	609	0	0	0
T208	739	0	0	0
T209	502	0	0	0
T210	573	0	0	0
T211	410	0	0	0
T212	17340	0	0	0
T213	12815	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	51778	0	0
T36	0	17	0	0
T37	0	239	0	0
T38	0	83	0	0
T40	650	126	0	0
T41	0	396	0	0
T43	0	43	0	0
T44	0	13	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T152	0	7168	0	0
T153	0	199	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T214	0	29	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	69	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	650	1	0	0
T41	0	4	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T152	0	1	0	0
T153	0	2	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T214	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6967850	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6970157	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	77	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	650	1	0	0
T41	0	4	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T152	0	1	0	0
T153	0	2	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	72	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	650	1	0	0
T41	0	4	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T152	0	1	0	0
T153	0	2	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T214	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	69	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	650	1	0	0
T41	0	4	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T152	0	1	0	0
T153	0	2	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T214	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	69	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	650	1	0	0
T41	0	4	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T152	0	1	0	0
T153	0	2	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T214	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	51680	0	0
T36	0	16	0	0
T37	0	237	0	0
T38	0	80	0	0
T40	650	125	0	0
T41	0	391	0	0
T43	0	41	0	0
T44	0	12	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T152	0	7167	0	0
T153	0	196	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T214	0	28	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	2699	0	0
T1	12650	0	0	0
T2	23681	0	0	0
T6	537	2	0	0
T7	504	2	0	0
T14	413	1	0	0
T15	425	1	0	0
T16	1709	3	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	5	0	0
T20	0	4	0	0
T21	0	2	0	0
T25	0	3	0	0
T58	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	39	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	650	1	0	0
T41	0	3	0	0
T44	0	1	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T194	0	1	0	0
T214	0	1	0	0
T215	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T7,T1,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T7,T1,T14
1	1	Covered	T7,T1,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T4,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T39
1	0	Covered	T7,T1,T14
1	1	Covered	T4,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T39,T40
0	1	Covered	T192,T149,T103
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T39,T40
0	1	Covered	T4,T40,T37
1	0	Covered	T36

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T39,T40
1	-	Covered	T4,T40,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T39,T40
DetectSt	168	Covered	T4,T39,T40
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T4,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T39,T40
DebounceSt->IdleSt	163	Covered	T79,T119,T167
DetectSt->IdleSt	186	Covered	T192,T149,T103
DetectSt->StableSt	191	Covered	T4,T39,T40
IdleSt->DebounceSt	148	Covered	T4,T39,T40
StableSt->IdleSt	206	Covered	T4,T39,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T39,T40
0	1	Covered	T4,T39,T40
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T39,T40
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T7,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T119,T167,T216
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T39,T40
DetectSt	-	-	-	-	1	-	-	Covered	T192,T149,T103
DetectSt	-	-	-	-	0	1	-	Covered	T4,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T40,T36
StableSt	-	-	-	-	-	-	0	Covered	T4,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	156	0	0
CntIncr_A	8063858	84904	0	0
CntNoWrap_A	8063858	7444788	0	0
DetectStDropOut_A	8063858	3	0	0
DetectedOut_A	8063858	6781	0	0
DetectedPulseOut_A	8063858	73	0	0
DisabledIdleSt_A	8063858	6991914	0	0
DisabledNoDetection_A	8063858	6994223	0	0
EnterDebounceSt_A	8063858	80	0	0
EnterDetectSt_A	8063858	76	0	0
EnterStableSt_A	8063858	73	0	0
PulseIsPulse_A	8063858	73	0	0
StayInStableSt	8063858	6676	0	0
gen_high_level_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	156	0	0
T4	5277	4	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T39	0	2	0	0
T40	0	4	0	0
T42	0	2	0	0
T43	0	2	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T79	0	1	0	0
T153	0	2	0	0
T217	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	84904	0	0
T4	5277	178	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	27	0	0
T37	0	184	0	0
T39	0	83	0	0
T40	0	72	0	0
T42	0	88	0	0
T43	0	44	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T79	0	21	0	0
T153	0	28	0	0
T217	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444788	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	3	0	0
T103	0	1	0	0
T149	0	1	0	0
T192	543	1	0	0
T193	459	0	0	0
T218	5116	0	0	0
T219	10821	0	0	0
T220	2261	0	0	0
T221	428	0	0	0
T222	426	0	0	0
T223	424	0	0	0
T224	9232	0	0	0
T225	589	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6781	0	0
T4	5277	258	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	17	0	0
T37	0	239	0	0
T39	0	36	0	0
T40	0	122	0	0
T42	0	210	0	0
T43	0	108	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T153	0	55	0	0
T217	0	115	0	0
T226	0	173	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	73	0	0
T4	5277	2	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T153	0	1	0	0
T217	0	2	0	0
T226	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6991914	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6994223	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	80	0	0
T4	5277	2	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T79	0	1	0	0
T153	0	1	0	0
T217	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	76	0	0
T4	5277	2	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T153	0	1	0	0
T217	0	2	0	0
T226	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	73	0	0
T4	5277	2	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T153	0	1	0	0
T217	0	2	0	0
T226	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	73	0	0
T4	5277	2	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T153	0	1	0	0
T217	0	2	0	0
T226	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6676	0	0
T4	5277	255	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	16	0	0
T37	0	236	0	0
T39	0	34	0	0
T40	0	119	0	0
T42	0	209	0	0
T43	0	106	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T153	0	53	0	0
T217	0	113	0	0
T226	0	170	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	40	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T85	0	1	0	0
T93	0	1	0	0
T119	0	1	0	0
T217	0	2	0	0
T226	0	1	0	0
T227	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T1,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T40,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T40,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T40,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T39,T40
1	0	Covered	T7,T1,T14
1	1	Covered	T40,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T36,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T36,T37
0	1	Covered	T40,T37,T150
1	0	Covered	T36

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T36,T37
1	-	Covered	T40,T37,T150

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T36,T37
DetectSt	168	Covered	T40,T36,T37
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T40,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T36,T37
DebounceSt->IdleSt	163	Covered	T79,T83,T228
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T40,T36,T37
IdleSt->DebounceSt	148	Covered	T40,T36,T37
StableSt->IdleSt	206	Covered	T40,T36,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T36,T37
0	1	Covered	T40,T36,T37
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T36,T37
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T36,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T83,T228
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T36,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T40,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T36,T37
StableSt	-	-	-	-	-	-	0	Covered	T40,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	81	0	0
CntIncr_A	8063858	142300	0	0
CntNoWrap_A	8063858	7444863	0	0
DetectStDropOut_A	8063858	0	0	0
DetectedOut_A	8063858	26590	0	0
DetectedPulseOut_A	8063858	39	0	0
DisabledIdleSt_A	8063858	6915575	0	0
DisabledNoDetection_A	8063858	6917882	0	0
EnterDebounceSt_A	8063858	42	0	0
EnterDetectSt_A	8063858	39	0	0
EnterStableSt_A	8063858	39	0	0
PulseIsPulse_A	8063858	39	0	0
StayInStableSt	8063858	26536	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8063858	6200	0	0
gen_low_level_sva.LowLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	81	0	0
T36	0	2	0	0
T37	0	2	0	0
T40	650	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T79	0	1	0	0
T85	0	2	0	0
T122	0	2	0	0
T150	0	2	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T215	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	142300	0	0
T36	0	27	0	0
T37	0	92	0	0
T40	650	36	0	0
T41	0	90	0	0
T42	0	88	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T79	0	21	0	0
T85	0	42	0	0
T122	0	40	0	0
T150	0	41	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T215	0	17	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444863	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	26590	0	0
T36	0	16	0	0
T37	0	281	0	0
T40	650	9	0	0
T41	0	156	0	0
T42	0	42	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T85	0	83	0	0
T86	0	55	0	0
T122	0	92	0	0
T150	0	29	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T215	0	133	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	39	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	650	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T122	0	1	0	0
T150	0	1	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T215	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6915575	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6917882	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	42	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	650	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T79	0	1	0	0
T85	0	1	0	0
T122	0	1	0	0
T150	0	1	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T215	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	39	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	650	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T122	0	1	0	0
T150	0	1	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T215	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	39	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	650	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T122	0	1	0	0
T150	0	1	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T215	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	39	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	650	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T122	0	1	0	0
T150	0	1	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T215	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	26536	0	0
T36	0	15	0	0
T37	0	280	0	0
T40	650	8	0	0
T41	0	154	0	0
T42	0	40	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T85	0	82	0	0
T86	0	53	0	0
T122	0	91	0	0
T150	0	28	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T215	0	131	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6200	0	0
T1	12650	30	0	0
T2	23681	7	0	0
T7	504	4	0	0
T14	413	1	0	0
T15	425	1	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	4	0	0
T19	428	2	0	0
T20	499	6	0	0
T21	0	2	0	0
T29	0	27	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	23	0	0
T37	0	1	0	0
T40	650	1	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T85	0	1	0	0
T111	0	1	0	0
T122	0	1	0	0
T150	0	1	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T167	0	1	0	0
T181	0	1	0	0
T182	0	2	0	0
T184	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T7,T1,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T7,T1,T14
1	1	Covered	T7,T1,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T8,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T4,T8,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T8,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T13
1	0	Covered	T7,T1,T14
1	1	Covered	T4,T8,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T13
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T13
0	1	Covered	T4,T8,T13
1	0	Covered	T36

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T8,T13
1	-	Covered	T4,T8,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T8,T13
DetectSt	168	Covered	T4,T8,T13
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T4,T8,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T8,T13
DebounceSt->IdleSt	163	Covered	T79,T229,T169
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4,T8,T13
IdleSt->DebounceSt	148	Covered	T4,T8,T13
StableSt->IdleSt	206	Covered	T4,T8,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T8,T13
0	1	Covered	T4,T8,T13
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T13
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T8,T13
IdleSt	0	-	-	-	-	-	-	Covered	T7,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T8,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T229,T169,T216
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T8,T13
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T4,T8,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T8,T13
StableSt	-	-	-	-	-	-	0	Covered	T4,T8,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	124	0	0
CntIncr_A	8063858	44213	0	0
CntNoWrap_A	8063858	7444820	0	0
DetectStDropOut_A	8063858	0	0	0
DetectedOut_A	8063858	16174	0	0
DetectedPulseOut_A	8063858	59	0	0
DisabledIdleSt_A	8063858	7204734	0	0
DisabledNoDetection_A	8063858	7207050	0	0
EnterDebounceSt_A	8063858	65	0	0
EnterDetectSt_A	8063858	59	0	0
EnterStableSt_A	8063858	59	0	0
PulseIsPulse_A	8063858	59	0	0
StayInStableSt	8063858	16092	0	0
gen_high_level_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	124	0	0
T4	5277	4	0	0
T8	550	2	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	44213	0	0
T4	5277	178	0	0
T8	550	32	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	19	0	0
T36	0	27	0	0
T37	0	92	0	0
T38	0	48	0	0
T39	0	18	0	0
T40	0	36	0	0
T42	0	88	0	0
T43	0	44	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444820	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	16174	0	0
T4	5277	256	0	0
T8	550	31	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	11	0	0
T36	0	16	0	0
T37	0	413	0	0
T38	0	42	0	0
T39	0	66	0	0
T40	0	89	0	0
T42	0	101	0	0
T43	0	43	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	59	0	0
T4	5277	2	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7204734	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7207050	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	65	0	0
T4	5277	2	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	59	0	0
T4	5277	2	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	59	0	0
T4	5277	2	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	59	0	0
T4	5277	2	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	16092	0	0
T4	5277	253	0	0
T8	550	30	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	10	0	0
T36	0	15	0	0
T37	0	412	0	0
T38	0	40	0	0
T39	0	64	0	0
T40	0	88	0	0
T42	0	99	0	0
T43	0	41	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	35	0	0
T4	5277	1	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T13	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T85	0	1	0	0
T153	0	2	0	0
T217	0	2	0	0
T230	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T1,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T8,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T4,T8,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T8,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T40
1	0	Covered	T7,T1,T14
1	1	Covered	T4,T8,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T40
0	1	Covered	T184,T149
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T40
0	1	Covered	T4,T41,T195
1	0	Covered	T36

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T8,T40
1	-	Covered	T4,T41,T195

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T8,T40
DetectSt	168	Covered	T4,T8,T40
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T4,T8,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T8,T40
DebounceSt->IdleSt	163	Covered	T217,T79
DetectSt->IdleSt	186	Covered	T184,T149
DetectSt->StableSt	191	Covered	T4,T8,T40
IdleSt->DebounceSt	148	Covered	T4,T8,T40
StableSt->IdleSt	206	Covered	T4,T36,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T8,T40
0	1	Covered	T4,T8,T40
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T40
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T8,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T8,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T217
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T8,T40
DetectSt	-	-	-	-	1	-	-	Covered	T184,T149
DetectSt	-	-	-	-	0	1	-	Covered	T4,T8,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T36,T41
StableSt	-	-	-	-	-	-	0	Covered	T4,T8,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	90	0	0
CntIncr_A	8063858	38377	0	0
CntNoWrap_A	8063858	7444854	0	0
DetectStDropOut_A	8063858	2	0	0
DetectedOut_A	8063858	7632	0	0
DetectedPulseOut_A	8063858	42	0	0
DisabledIdleSt_A	8063858	6809389	0	0
DisabledNoDetection_A	8063858	6811703	0	0
EnterDebounceSt_A	8063858	46	0	0
EnterDetectSt_A	8063858	44	0	0
EnterStableSt_A	8063858	42	0	0
PulseIsPulse_A	8063858	42	0	0
StayInStableSt	8063858	7574	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8063858	5886	0	0
gen_low_level_sva.LowLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	90	0	0
T4	5277	2	0	0
T8	550	2	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T40	0	2	0	0
T41	0	6	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T79	0	1	0	0
T119	0	2	0	0
T195	0	2	0	0
T217	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	38377	0	0
T4	5277	89	0	0
T8	550	32	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	27	0	0
T37	0	92	0	0
T40	0	36	0	0
T41	0	200	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T79	0	21	0	0
T119	0	80	0	0
T195	0	36111	0	0
T217	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444854	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	2	0	0
T149	0	1	0	0
T184	137145	1	0	0
T231	36016	0	0	0
T232	2080	0	0	0
T233	20291	0	0	0
T234	735	0	0	0
T235	5265	0	0	0
T236	1650	0	0	0
T237	503	0	0	0
T238	513	0	0	0
T239	7033	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7632	0	0
T4	5277	131	0	0
T8	550	45	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	18	0	0
T37	0	41	0	0
T40	0	42	0	0
T41	0	303	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T85	0	1	0	0
T119	0	126	0	0
T195	0	4554	0	0
T217	0	55	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	42	0	0
T4	5277	1	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T85	0	1	0	0
T119	0	1	0	0
T195	0	1	0	0
T217	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6809389	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6811703	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	46	0	0
T4	5277	1	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T79	0	1	0	0
T119	0	1	0	0
T195	0	1	0	0
T217	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	44	0	0
T4	5277	1	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T85	0	1	0	0
T119	0	1	0	0
T195	0	1	0	0
T217	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	42	0	0
T4	5277	1	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T85	0	1	0	0
T119	0	1	0	0
T195	0	1	0	0
T217	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	42	0	0
T4	5277	1	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T85	0	1	0	0
T119	0	1	0	0
T195	0	1	0	0
T217	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7574	0	0
T4	5277	130	0	0
T8	550	43	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	17	0	0
T37	0	39	0	0
T40	0	40	0	0
T41	0	298	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T119	0	124	0	0
T182	0	69	0	0
T195	0	4553	0	0
T217	0	53	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	5886	0	0
T1	12650	21	0	0
T2	23681	11	0	0
T7	504	5	0	0
T14	413	1	0	0
T15	425	3	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	2	0	0
T20	499	7	0	0
T21	0	2	0	0
T25	0	8	0	0
T29	0	28	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	25	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T41	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T182	0	1	0	0
T184	0	3	0	0
T195	0	1	0	0
T205	0	1	0	0
T240	0	1	0	0
T241	0	2	0	0