Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T7,T1,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T7,T1,T14
1	1	Covered	T7,T1,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T8,T35,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T8,T35,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T8,T35,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T39,T35
1	0	Covered	T7,T1,T14
1	1	Covered	T8,T35,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T35,T34
0	1	Covered	T41,T184,T206
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T35,T34
0	1	Covered	T37,T153,T119
1	0	Covered	T36

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T35,T34
1	-	Covered	T37,T153,T119

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T35,T34
DetectSt	168	Covered	T8,T35,T34
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T8,T35,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T35,T34
DebounceSt->IdleSt	163	Covered	T79,T242,T243
DetectSt->IdleSt	186	Covered	T41,T184,T206
DetectSt->StableSt	191	Covered	T8,T35,T34
IdleSt->DebounceSt	148	Covered	T8,T35,T34
StableSt->IdleSt	206	Covered	T35,T34,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T35,T34
0	1	Covered	T8,T35,T34
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T35,T34
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T35,T34
IdleSt	0	-	-	-	-	-	-	Covered	T7,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T35,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T242,T243,T83
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T35,T34
DetectSt	-	-	-	-	1	-	-	Covered	T41,T184,T206
DetectSt	-	-	-	-	0	1	-	Covered	T8,T35,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T37,T153
StableSt	-	-	-	-	-	-	0	Covered	T8,T35,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	142	0	0
CntIncr_A	8063858	4428	0	0
CntNoWrap_A	8063858	7444802	0	0
DetectStDropOut_A	8063858	3	0	0
DetectedOut_A	8063858	5889	0	0
DetectedPulseOut_A	8063858	64	0	0
DisabledIdleSt_A	8063858	7200712	0	0
DisabledNoDetection_A	8063858	7203019	0	0
EnterDebounceSt_A	8063858	76	0	0
EnterDetectSt_A	8063858	67	0	0
EnterStableSt_A	8063858	64	0	0
PulseIsPulse_A	8063858	64	0	0
StayInStableSt	8063858	5795	0	0
gen_high_level_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	142	0	0
T8	550	2	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T28	9269	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	4	0	0
T41	0	4	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T79	0	1	0	0
T119	0	2	0	0
T153	0	4	0	0
T217	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	4428	0	0
T8	550	32	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T28	9269	0	0	0
T34	0	19	0	0
T35	0	97	0	0
T36	0	27	0	0
T37	0	184	0	0
T41	0	99	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T79	0	20	0	0
T119	0	80	0	0
T153	0	56	0	0
T217	0	10	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444802	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	3	0	0
T41	15349	1	0	0
T81	17606	0	0	0
T91	27382	0	0	0
T184	0	1	0	0
T206	0	1	0	0
T244	527	0	0	0
T245	4412	0	0	0
T246	421	0	0	0
T247	490	0	0	0
T248	522	0	0	0
T249	408	0	0	0
T250	611	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	5889	0	0
T8	550	108	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T28	9269	0	0	0
T34	0	45	0	0
T35	0	37	0	0
T36	0	17	0	0
T37	0	479	0	0
T41	0	39	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T93	0	123	0	0
T119	0	48	0	0
T153	0	117	0	0
T217	0	204	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	64	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T28	9269	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T41	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T93	0	1	0	0
T119	0	1	0	0
T153	0	2	0	0
T217	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7200712	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7203019	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	76	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T28	9269	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T41	0	2	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T79	0	1	0	0
T119	0	1	0	0
T153	0	2	0	0
T217	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	67	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T28	9269	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T41	0	2	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T93	0	1	0	0
T119	0	1	0	0
T153	0	2	0	0
T217	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	64	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T28	9269	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T41	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T93	0	1	0	0
T119	0	1	0	0
T153	0	2	0	0
T217	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	64	0	0
T8	550	1	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T28	9269	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T41	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T93	0	1	0	0
T119	0	1	0	0
T153	0	2	0	0
T217	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	5795	0	0
T8	550	106	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T28	9269	0	0	0
T34	0	43	0	0
T35	0	35	0	0
T36	0	16	0	0
T37	0	476	0	0
T41	0	37	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T93	0	122	0	0
T119	0	47	0	0
T153	0	115	0	0
T217	0	202	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	33	0	0
T37	1207	1	0	0
T84	0	1	0	0
T93	0	1	0	0
T119	0	1	0	0
T153	0	2	0	0
T170	8989	0	0	0
T171	495	0	0	0
T172	10159	0	0	0
T173	19013	0	0	0
T174	522	0	0	0
T175	432	0	0	0
T176	488	0	0	0
T177	58481	0	0	0
T178	524	0	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	6	0	0
T242	0	1	0	0
T251	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T1,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T40,T36,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T40,T36,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T40,T36,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T40,T35
1	0	Covered	T7,T1,T14
1	1	Covered	T40,T36,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T36,T38
0	1	Covered	T84,T252
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T36,T38
0	1	Covered	T38,T153,T242
1	0	Covered	T36

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T36,T38
1	-	Covered	T38,T153,T242

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T36,T38
DetectSt	168	Covered	T40,T36,T38
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T40,T36,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T36,T38
DebounceSt->IdleSt	163	Covered	T79
DetectSt->IdleSt	186	Covered	T84,T252
DetectSt->StableSt	191	Covered	T40,T36,T38
IdleSt->DebounceSt	148	Covered	T40,T36,T38
StableSt->IdleSt	206	Covered	T36,T38,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T36,T38
0	1	Covered	T40,T36,T38
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T36,T38
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T36,T38
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T36,T38
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T36,T38
DetectSt	-	-	-	-	1	-	-	Covered	T84,T252
DetectSt	-	-	-	-	0	1	-	Covered	T40,T36,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T38,T153
StableSt	-	-	-	-	-	-	0	Covered	T40,T36,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	81	0	0
CntIncr_A	8063858	55313	0	0
CntNoWrap_A	8063858	7444863	0	0
DetectStDropOut_A	8063858	2	0	0
DetectedOut_A	8063858	3042	0	0
DetectedPulseOut_A	8063858	38	0	0
DisabledIdleSt_A	8063858	6894554	0	0
DisabledNoDetection_A	8063858	6896862	0	0
EnterDebounceSt_A	8063858	41	0	0
EnterDetectSt_A	8063858	40	0	0
EnterStableSt_A	8063858	38	0	0
PulseIsPulse_A	8063858	38	0	0
StayInStableSt	8063858	2985	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8063858	5929	0	0
gen_low_level_sva.LowLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	81	0	0
T36	0	2	0	0
T38	0	2	0	0
T40	650	2	0	0
T41	0	4	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T79	0	1	0	0
T93	0	2	0	0
T119	0	2	0	0
T153	0	4	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T195	0	2	0	0
T242	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	55313	0	0
T36	0	27	0	0
T38	0	48	0	0
T40	650	36	0	0
T41	0	160	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T79	0	20	0	0
T93	0	59	0	0
T119	0	80	0	0
T153	0	56	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T195	0	36111	0	0
T242	0	200	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444863	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	2	0	0
T84	856	1	0	0
T252	0	1	0	0
T253	18568	0	0	0
T254	8476	0	0	0
T255	503	0	0	0
T256	494	0	0	0
T257	641	0	0	0
T258	524	0	0	0
T259	10680	0	0	0
T260	2289	0	0	0
T261	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	3042	0	0
T36	0	17	0	0
T38	0	30	0	0
T40	650	88	0	0
T41	0	393	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T93	0	48	0	0
T119	0	251	0	0
T153	0	97	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T182	0	144	0	0
T195	0	44	0	0
T242	0	85	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	38	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	650	1	0	0
T41	0	2	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T93	0	1	0	0
T119	0	1	0	0
T153	0	2	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T182	0	1	0	0
T195	0	1	0	0
T242	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6894554	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6896862	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	41	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	650	1	0	0
T41	0	2	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T79	0	1	0	0
T93	0	1	0	0
T119	0	1	0	0
T153	0	2	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T195	0	1	0	0
T242	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	40	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	650	1	0	0
T41	0	2	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T93	0	1	0	0
T119	0	1	0	0
T153	0	2	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T182	0	1	0	0
T195	0	1	0	0
T242	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	38	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	650	1	0	0
T41	0	2	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T93	0	1	0	0
T119	0	1	0	0
T153	0	2	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T182	0	1	0	0
T195	0	1	0	0
T242	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	38	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	650	1	0	0
T41	0	2	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T93	0	1	0	0
T119	0	1	0	0
T153	0	2	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T182	0	1	0	0
T195	0	1	0	0
T242	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	2985	0	0
T36	0	16	0	0
T38	0	29	0	0
T40	650	86	0	0
T41	0	389	0	0
T47	20385	0	0	0
T56	642	0	0	0
T57	2705	0	0	0
T65	1421	0	0	0
T66	488	0	0	0
T93	0	46	0	0
T119	0	249	0	0
T153	0	94	0	0
T154	422	0	0	0
T155	531	0	0	0
T156	427	0	0	0
T157	402	0	0	0
T182	0	142	0	0
T195	0	42	0	0
T242	0	82	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	5929	0	0
T1	12650	28	0	0
T2	23681	14	0	0
T7	504	4	0	0
T14	413	2	0	0
T15	425	4	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	5	0	0
T20	499	10	0	0
T21	0	2	0	0
T25	0	6	0	0
T29	0	17	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	18	0	0
T38	760	1	0	0
T77	16742	0	0	0
T151	0	1	0	0
T153	0	1	0	0
T180	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T205	0	1	0	0
T228	0	1	0	0
T242	0	1	0	0
T262	0	1	0	0
T263	5320	0	0	0
T264	403	0	0	0
T265	449	0	0	0
T266	502	0	0	0
T267	506	0	0	0
T268	492	0	0	0
T269	455	0	0	0
T270	502	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T7,T1,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T7,T1,T14
1	1	Covered	T7,T1,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T39,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T4,T39,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T39,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T13,T39
1	0	Covered	T7,T1,T14
1	1	Covered	T4,T39,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T39,T36
0	1	Covered	T262,T151
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T39,T36
0	1	Covered	T4,T39,T37
1	0	Covered	T36

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T39,T36
1	-	Covered	T4,T39,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T39,T36
DetectSt	168	Covered	T4,T39,T36
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T4,T39,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T39,T36
DebounceSt->IdleSt	163	Covered	T79
DetectSt->IdleSt	186	Covered	T262,T151
DetectSt->StableSt	191	Covered	T4,T39,T36
IdleSt->DebounceSt	148	Covered	T4,T39,T36
StableSt->IdleSt	206	Covered	T4,T39,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T39,T36
0	1	Covered	T4,T39,T36
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T39,T36
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T39,T36
IdleSt	0	-	-	-	-	-	-	Covered	T7,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T39,T36
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T39,T36
DetectSt	-	-	-	-	1	-	-	Covered	T262,T151
DetectSt	-	-	-	-	0	1	-	Covered	T4,T39,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T39,T36
StableSt	-	-	-	-	-	-	0	Covered	T4,T39,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	119	0	0
CntIncr_A	8063858	20572	0	0
CntNoWrap_A	8063858	7444825	0	0
DetectStDropOut_A	8063858	2	0	0
DetectedOut_A	8063858	5696	0	0
DetectedPulseOut_A	8063858	57	0	0
DisabledIdleSt_A	8063858	7376136	0	0
DisabledNoDetection_A	8063858	7378454	0	0
EnterDebounceSt_A	8063858	60	0	0
EnterDetectSt_A	8063858	59	0	0
EnterStableSt_A	8063858	57	0	0
PulseIsPulse_A	8063858	57	0	0
StayInStableSt	8063858	5618	0	0
gen_high_level_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	119	0	0
T4	5277	4	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	2	0	0
T37	0	6	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T44	0	2	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T79	0	1	0	0
T150	0	2	0	0
T226	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	20572	0	0
T4	5277	178	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	27	0	0
T37	0	276	0	0
T39	0	83	0	0
T41	0	90	0	0
T42	0	88	0	0
T44	0	35	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T79	0	20	0	0
T150	0	41	0	0
T226	0	188	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444825	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	2	0	0
T100	24371	0	0	0
T151	0	1	0	0
T179	621	0	0	0
T185	17680	0	0	0
T186	773	0	0	0
T262	885	1	0	0
T271	720	0	0	0
T272	509	0	0	0
T273	504	0	0	0
T274	1196	0	0	0
T275	413	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	5696	0	0
T4	5277	348	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	16	0	0
T37	0	254	0	0
T39	0	49	0	0
T41	0	338	0	0
T42	0	101	0	0
T44	0	42	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T150	0	203	0	0
T194	0	316	0	0
T226	0	76	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	57	0	0
T4	5277	2	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T150	0	1	0	0
T194	0	1	0	0
T226	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7376136	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7378454	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	60	0	0
T4	5277	2	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T79	0	1	0	0
T150	0	1	0	0
T226	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	59	0	0
T4	5277	2	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T150	0	1	0	0
T194	0	1	0	0
T226	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	57	0	0
T4	5277	2	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T150	0	1	0	0
T194	0	1	0	0
T226	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	57	0	0
T4	5277	2	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	1	0	0
T37	0	3	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T150	0	1	0	0
T194	0	1	0	0
T226	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	5618	0	0
T4	5277	345	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	15	0	0
T37	0	250	0	0
T39	0	48	0	0
T41	0	337	0	0
T42	0	99	0	0
T44	0	40	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T150	0	202	0	0
T194	0	314	0	0
T226	0	73	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	35	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T37	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T86	0	1	0	0
T150	0	1	0	0
T182	0	1	0	0
T226	0	1	0	0
T230	0	1	0	0
T243	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T1,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T4,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T4,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T39,T40
1	0	Covered	T7,T1,T14
1	1	Covered	T4,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T39,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T39,T40
0	1	Covered	T4,T40,T37
1	0	Covered	T36

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T39,T40
1	-	Covered	T4,T40,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T39,T40
DetectSt	168	Covered	T4,T39,T40
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T4,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T39,T40
DebounceSt->IdleSt	163	Covered	T79,T228
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4,T39,T40
IdleSt->DebounceSt	148	Covered	T4,T39,T40
StableSt->IdleSt	206	Covered	T4,T39,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T39,T40
0	1	Covered	T4,T39,T40
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T39,T40
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T228
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T39,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T4,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T40,T36
StableSt	-	-	-	-	-	-	0	Covered	T4,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	68	0	0
CntIncr_A	8063858	38217	0	0
CntNoWrap_A	8063858	7444876	0	0
DetectStDropOut_A	8063858	0	0	0
DetectedOut_A	8063858	22995	0	0
DetectedPulseOut_A	8063858	33	0	0
DisabledIdleSt_A	8063858	7024041	0	0
DisabledNoDetection_A	8063858	7026358	0	0
EnterDebounceSt_A	8063858	35	0	0
EnterDetectSt_A	8063858	33	0	0
EnterStableSt_A	8063858	33	0	0
PulseIsPulse_A	8063858	33	0	0
StayInStableSt	8063858	22948	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8063858	5866	0	0
gen_low_level_sva.LowLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	68	0	0
T4	5277	2	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	0	4	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	6	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T79	0	1	0	0
T195	0	2	0	0
T226	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	38217	0	0
T4	5277	89	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	27	0	0
T37	0	184	0	0
T38	0	96	0	0
T39	0	83	0	0
T40	0	36	0	0
T41	0	264	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T79	0	20	0	0
T195	0	36111	0	0
T226	0	94	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444876	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	22995	0	0
T4	5277	40	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	18	0	0
T37	0	80	0	0
T38	0	84	0	0
T39	0	36	0	0
T40	0	8	0	0
T41	0	248	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T86	0	154	0	0
T195	0	20501	0	0
T226	0	138	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	33	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T86	0	1	0	0
T195	0	1	0	0
T226	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7024041	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7026358	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	35	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T79	0	1	0	0
T195	0	1	0	0
T226	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	33	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T86	0	1	0	0
T195	0	1	0	0
T226	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	33	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T86	0	1	0	0
T195	0	1	0	0
T226	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	33	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T86	0	1	0	0
T195	0	1	0	0
T226	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	22948	0	0
T4	5277	39	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T36	0	17	0	0
T37	0	78	0	0
T38	0	81	0	0
T39	0	34	0	0
T40	0	7	0	0
T41	0	243	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T86	0	152	0	0
T195	0	20500	0	0
T226	0	137	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	5866	0	0
T1	12650	25	0	0
T2	23681	12	0	0
T7	504	5	0	0
T14	413	1	0	0
T15	425	1	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	3	0	0
T20	499	6	0	0
T21	0	1	0	0
T25	0	7	0	0
T29	0	24	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	18	0	0
T4	5277	1	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T12	1054	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T83	0	1	0	0
T111	0	1	0	0
T183	0	1	0	0
T195	0	1	0	0
T226	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T7,T1,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T7,T1,T14
1	1	Covered	T7,T1,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T39,T34,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T39,T34,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T39,T34,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T39,T34,T36
1	0	Covered	T7,T1,T14
1	1	Covered	T39,T34,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T39,T34,T36
0	1	Covered	T111,T151
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T39,T34,T36
0	1	Covered	T38,T217,T41
1	0	Covered	T36

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T39,T34,T36
1	-	Covered	T38,T217,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T39,T34,T36
DetectSt	168	Covered	T39,T34,T36
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T39,T34,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T39,T34,T36
DebounceSt->IdleSt	163	Covered	T79,T85,T83
DetectSt->IdleSt	186	Covered	T111,T151
DetectSt->StableSt	191	Covered	T39,T34,T36
IdleSt->DebounceSt	148	Covered	T39,T34,T36
StableSt->IdleSt	206	Covered	T34,T36,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T39,T34,T36
0	1	Covered	T39,T34,T36
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T39,T34,T36
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T39,T34,T36
IdleSt	0	-	-	-	-	-	-	Covered	T7,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T39,T34,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T85,T83,T229
DebounceSt	-	0	0	-	-	-	-	Covered	T39,T34,T36
DetectSt	-	-	-	-	1	-	-	Covered	T111,T151
DetectSt	-	-	-	-	0	1	-	Covered	T39,T34,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T38,T217
StableSt	-	-	-	-	-	-	0	Covered	T39,T34,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	146	0	0
CntIncr_A	8063858	21319	0	0
CntNoWrap_A	8063858	7444798	0	0
DetectStDropOut_A	8063858	2	0	0
DetectedOut_A	8063858	4695	0	0
DetectedPulseOut_A	8063858	67	0	0
DisabledIdleSt_A	8063858	7375396	0	0
DisabledNoDetection_A	8063858	7377702	0	0
EnterDebounceSt_A	8063858	78	0	0
EnterDetectSt_A	8063858	69	0	0
EnterStableSt_A	8063858	67	0	0
PulseIsPulse_A	8063858	67	0	0
StayInStableSt	8063858	4600	0	0
gen_high_level_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	146	0	0
T34	0	2	0	0
T36	0	2	0	0
T38	0	4	0	0
T39	2810	2	0	0
T41	0	4	0	0
T42	0	2	0	0
T49	12606	0	0	0
T50	694	0	0	0
T51	5916	0	0	0
T52	626	0	0	0
T53	4866	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T79	0	1	0	0
T104	415	0	0	0
T214	0	2	0	0
T217	0	4	0	0
T226	0	2	0	0
T276	435	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	21319	0	0
T34	0	19	0	0
T36	0	27	0	0
T38	0	96	0	0
T39	2810	18	0	0
T41	0	113	0	0
T42	0	88	0	0
T49	12606	0	0	0
T50	694	0	0	0
T51	5916	0	0	0
T52	626	0	0	0
T53	4866	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T79	0	21	0	0
T104	415	0	0	0
T214	0	49	0	0
T217	0	20	0	0
T226	0	94	0	0
T276	435	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444798	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	2	0	0
T111	7300	1	0	0
T112	25370	0	0	0
T113	430	0	0	0
T114	1104	0	0	0
T132	2090	0	0	0
T151	0	1	0	0
T277	17080	0	0	0
T278	700	0	0	0
T279	796	0	0	0
T280	2497	0	0	0
T281	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	4695	0	0
T34	0	45	0	0
T36	0	17	0	0
T38	0	82	0	0
T39	2810	39	0	0
T41	0	62	0	0
T42	0	230	0	0
T49	12606	0	0	0
T50	694	0	0	0
T51	5916	0	0	0
T52	626	0	0	0
T53	4866	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T85	0	34	0	0
T104	415	0	0	0
T214	0	51	0	0
T217	0	73	0	0
T226	0	42	0	0
T276	435	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	67	0	0
T34	0	1	0	0
T36	0	1	0	0
T38	0	2	0	0
T39	2810	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T49	12606	0	0	0
T50	694	0	0	0
T51	5916	0	0	0
T52	626	0	0	0
T53	4866	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T85	0	1	0	0
T104	415	0	0	0
T214	0	1	0	0
T217	0	2	0	0
T226	0	1	0	0
T276	435	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7375396	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7377702	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	78	0	0
T34	0	1	0	0
T36	0	1	0	0
T38	0	2	0	0
T39	2810	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T49	12606	0	0	0
T50	694	0	0	0
T51	5916	0	0	0
T52	626	0	0	0
T53	4866	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T79	0	1	0	0
T104	415	0	0	0
T214	0	1	0	0
T217	0	2	0	0
T226	0	1	0	0
T276	435	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	69	0	0
T34	0	1	0	0
T36	0	1	0	0
T38	0	2	0	0
T39	2810	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T49	12606	0	0	0
T50	694	0	0	0
T51	5916	0	0	0
T52	626	0	0	0
T53	4866	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T85	0	1	0	0
T104	415	0	0	0
T214	0	1	0	0
T217	0	2	0	0
T226	0	1	0	0
T276	435	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	67	0	0
T34	0	1	0	0
T36	0	1	0	0
T38	0	2	0	0
T39	2810	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T49	12606	0	0	0
T50	694	0	0	0
T51	5916	0	0	0
T52	626	0	0	0
T53	4866	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T85	0	1	0	0
T104	415	0	0	0
T214	0	1	0	0
T217	0	2	0	0
T226	0	1	0	0
T276	435	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	67	0	0
T34	0	1	0	0
T36	0	1	0	0
T38	0	2	0	0
T39	2810	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T49	12606	0	0	0
T50	694	0	0	0
T51	5916	0	0	0
T52	626	0	0	0
T53	4866	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T85	0	1	0	0
T104	415	0	0	0
T214	0	1	0	0
T217	0	2	0	0
T226	0	1	0	0
T276	435	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	4600	0	0
T34	0	43	0	0
T36	0	16	0	0
T38	0	79	0	0
T39	2810	37	0	0
T41	0	60	0	0
T42	0	228	0	0
T49	12606	0	0	0
T50	694	0	0	0
T51	5916	0	0	0
T52	626	0	0	0
T53	4866	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T85	0	33	0	0
T104	415	0	0	0
T214	0	49	0	0
T217	0	71	0	0
T226	0	41	0	0
T276	435	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	38	0	0
T38	760	1	0	0
T41	0	2	0	0
T77	16742	0	0	0
T82	0	1	0	0
T83	0	1	0	0
T85	0	1	0	0
T167	0	1	0	0
T182	0	1	0	0
T217	0	2	0	0
T226	0	1	0	0
T242	0	1	0	0
T263	5320	0	0	0
T264	403	0	0	0
T265	449	0	0	0
T266	502	0	0	0
T267	506	0	0	0
T268	492	0	0	0
T269	455	0	0	0
T270	502	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T1,T14
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T1,T14
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T35,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T35,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T35,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T39,T35,T36
1	0	Covered	T7,T1,T14
1	1	Covered	T35,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Covered	T37,T38,T41
1	0	Covered	T36

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T36,T37
1	-	Covered	T37,T38,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T35,T36,T37
DetectSt	168	Covered	T35,T36,T37
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T35,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T36,T37
DebounceSt->IdleSt	163	Covered	T79,T228,T282
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T35,T36,T37
IdleSt->DebounceSt	148	Covered	T35,T36,T37
StableSt->IdleSt	206	Covered	T35,T36,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T35,T36,T37
0	1	Covered	T35,T36,T37
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T36,T37
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T35,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T36,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T228,T282
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T36,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T35,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T37,T38
StableSt	-	-	-	-	-	-	0	Covered	T35,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	65	0	0
CntIncr_A	8063858	1621	0	0
CntNoWrap_A	8063858	7444879	0	0
DetectStDropOut_A	8063858	0	0	0
DetectedOut_A	8063858	3169	0	0
DetectedPulseOut_A	8063858	31	0	0
DisabledIdleSt_A	8063858	7379105	0	0
DisabledNoDetection_A	8063858	7381424	0	0
EnterDebounceSt_A	8063858	34	0	0
EnterDetectSt_A	8063858	31	0	0
EnterStableSt_A	8063858	31	0	0
PulseIsPulse_A	8063858	31	0	0
StayInStableSt	8063858	3120	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8063858	6518	0	0
gen_low_level_sva.LowLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	65	0	0
T34	18289	0	0	0
T35	6318	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T41	0	6	0	0
T61	68032	0	0	0
T75	10843	0	0	0
T79	0	1	0	0
T117	695	0	0	0
T128	422	0	0	0
T129	451	0	0	0
T130	758	0	0	0
T131	502	0	0	0
T150	0	2	0	0
T196	407	0	0	0
T215	0	2	0	0
T226	0	2	0	0
T230	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	1621	0	0
T34	18289	0	0	0
T35	6318	97	0	0
T36	0	27	0	0
T37	0	92	0	0
T38	0	48	0	0
T41	0	250	0	0
T61	68032	0	0	0
T75	10843	0	0	0
T79	0	21	0	0
T117	695	0	0	0
T128	422	0	0	0
T129	451	0	0	0
T130	758	0	0	0
T131	502	0	0	0
T150	0	41	0	0
T196	407	0	0	0
T215	0	17	0	0
T226	0	94	0	0
T230	0	96	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444879	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	3169	0	0
T34	18289	0	0	0
T35	6318	136	0	0
T36	0	17	0	0
T37	0	280	0	0
T38	0	122	0	0
T41	0	508	0	0
T61	68032	0	0	0
T75	10843	0	0	0
T82	0	59	0	0
T117	695	0	0	0
T128	422	0	0	0
T129	451	0	0	0
T130	758	0	0	0
T131	502	0	0	0
T150	0	273	0	0
T196	407	0	0	0
T215	0	133	0	0
T226	0	135	0	0
T230	0	201	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	31	0	0
T34	18289	0	0	0
T35	6318	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	3	0	0
T61	68032	0	0	0
T75	10843	0	0	0
T82	0	1	0	0
T117	695	0	0	0
T128	422	0	0	0
T129	451	0	0	0
T130	758	0	0	0
T131	502	0	0	0
T150	0	1	0	0
T196	407	0	0	0
T215	0	1	0	0
T226	0	1	0	0
T230	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7379105	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7381424	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	34	0	0
T34	18289	0	0	0
T35	6318	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	3	0	0
T61	68032	0	0	0
T75	10843	0	0	0
T79	0	1	0	0
T117	695	0	0	0
T128	422	0	0	0
T129	451	0	0	0
T130	758	0	0	0
T131	502	0	0	0
T150	0	1	0	0
T196	407	0	0	0
T215	0	1	0	0
T226	0	1	0	0
T230	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	31	0	0
T34	18289	0	0	0
T35	6318	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	3	0	0
T61	68032	0	0	0
T75	10843	0	0	0
T82	0	1	0	0
T117	695	0	0	0
T128	422	0	0	0
T129	451	0	0	0
T130	758	0	0	0
T131	502	0	0	0
T150	0	1	0	0
T196	407	0	0	0
T215	0	1	0	0
T226	0	1	0	0
T230	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	31	0	0
T34	18289	0	0	0
T35	6318	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	3	0	0
T61	68032	0	0	0
T75	10843	0	0	0
T82	0	1	0	0
T117	695	0	0	0
T128	422	0	0	0
T129	451	0	0	0
T130	758	0	0	0
T131	502	0	0	0
T150	0	1	0	0
T196	407	0	0	0
T215	0	1	0	0
T226	0	1	0	0
T230	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	31	0	0
T34	18289	0	0	0
T35	6318	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	3	0	0
T61	68032	0	0	0
T75	10843	0	0	0
T82	0	1	0	0
T117	695	0	0	0
T128	422	0	0	0
T129	451	0	0	0
T130	758	0	0	0
T131	502	0	0	0
T150	0	1	0	0
T196	407	0	0	0
T215	0	1	0	0
T226	0	1	0	0
T230	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	3120	0	0
T34	18289	0	0	0
T35	6318	134	0	0
T36	0	16	0	0
T37	0	279	0	0
T38	0	121	0	0
T41	0	504	0	0
T61	68032	0	0	0
T75	10843	0	0	0
T82	0	57	0	0
T117	695	0	0	0
T128	422	0	0	0
T129	451	0	0	0
T130	758	0	0	0
T131	502	0	0	0
T150	0	271	0	0
T196	407	0	0	0
T215	0	131	0	0
T226	0	133	0	0
T230	0	199	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6518	0	0
T1	12650	34	0	0
T2	23681	14	0	0
T7	504	7	0	0
T14	413	2	0	0
T15	425	2	0	0
T16	1709	3	0	0
T17	405	0	0	0
T18	885	4	0	0
T19	428	3	0	0
T20	499	7	0	0
T21	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	12	0	0
T37	1207	1	0	0
T38	0	1	0	0
T41	0	2	0	0
T101	0	1	0	0
T169	0	2	0	0
T170	8989	0	0	0
T171	495	0	0	0
T172	10159	0	0	0
T173	19013	0	0	0
T174	522	0	0	0
T175	432	0	0	0
T176	488	0	0	0
T177	58481	0	0	0
T178	524	0	0	0
T180	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T229	0	1	0	0
T283	0	1	0	0