Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T29,T11
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T29,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T29,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T29,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T11
1	0	Covered	T1,T11,T45
1	1	Covered	T1,T29,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T29,T11
0	1	Covered	T29,T11,T51
1	0	Covered	T11,T46,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T45,T47
0	1	Covered	T1,T45,T47
1	0	Covered	T46,T36,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T45,T46
1	-	Covered	T1,T45,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T29,T11
DetectSt	168	Covered	T1,T29,T11
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T45,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T29,T11
DebounceSt->IdleSt	163	Covered	T36,T79,T284
DetectSt->IdleSt	186	Covered	T29,T11,T51
DetectSt->StableSt	191	Covered	T1,T45,T46
IdleSt->DebounceSt	148	Covered	T1,T29,T11
StableSt->IdleSt	206	Covered	T1,T45,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T29,T11
0	1	Covered	T1,T29,T11
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T29,T11
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T29,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T29,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T36,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T29,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T79,T284
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T29,T11
DetectSt	-	-	-	-	1	-	-	Covered	T29,T11,T51
DetectSt	-	-	-	-	0	1	-	Covered	T1,T45,T46
DetectSt	-	-	-	-	0	0	-	Covered	T1,T29,T11
StableSt	-	-	-	-	-	-	1	Covered	T1,T45,T46
StableSt	-	-	-	-	-	-	0	Covered	T1,T45,T47
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	2920	0	0
CntIncr_A	8063858	91016	0	0
CntNoWrap_A	8063858	7442024	0	0
DetectStDropOut_A	8063858	529	0	0
DetectedOut_A	8063858	61230	0	0
DetectedPulseOut_A	8063858	706	0	0
DisabledIdleSt_A	8063858	7010444	0	0
DisabledNoDetection_A	8063858	7012609	0	0
EnterDebounceSt_A	8063858	1465	0	0
EnterDetectSt_A	8063858	1456	0	0
EnterStableSt_A	8063858	706	0	0
PulseIsPulse_A	8063858	706	0	0
StayInStableSt	8063858	60415	0	0
gen_high_event_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_high_level_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	591	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	2920	0	0
T1	12650	14	0	0
T2	23681	0	0	0
T11	0	58	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T29	0	18	0	0
T33	0	22	0	0
T45	0	6	0	0
T46	0	46	0	0
T47	0	48	0	0
T51	0	24	0	0
T53	0	20	0	0
T75	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	91016	0	0
T1	12650	182	0	0
T2	23681	0	0	0
T11	0	2253	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T29	0	452	0	0
T33	0	506	0	0
T45	0	855	0	0
T46	0	1296	0	0
T47	0	1488	0	0
T51	0	790	0	0
T53	0	443	0	0
T75	0	724	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7442024	0	0
T1	12650	12214	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	529	0	0
T3	32917	0	0	0
T4	5277	0	0	0
T11	0	11	0	0
T25	496	0	0	0
T26	1780	0	0	0
T27	524	0	0	0
T29	5170	9	0	0
T31	929	0	0	0
T36	0	1	0	0
T46	0	14	0	0
T51	0	12	0	0
T53	0	10	0	0
T58	421	0	0	0
T63	509	0	0	0
T67	404	0	0	0
T90	0	6	0	0
T172	0	20	0	0
T263	0	27	0	0
T285	0	27	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	61230	0	0
T1	12650	405	0	0
T2	23681	0	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T33	0	1458	0	0
T36	0	387	0	0
T45	0	1538	0	0
T46	0	4	0	0
T47	0	1768	0	0
T80	0	315	0	0
T170	0	163	0	0
T173	0	1651	0	0
T286	0	761	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	706	0	0
T1	12650	7	0	0
T2	23681	0	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T33	0	11	0	0
T36	0	5	0	0
T45	0	3	0	0
T46	0	4	0	0
T47	0	24	0	0
T80	0	7	0	0
T170	0	8	0	0
T173	0	22	0	0
T286	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7010444	0	0
T1	12650	9354	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7012609	0	0
T1	12650	9356	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	1465	0	0
T1	12650	7	0	0
T2	23681	0	0	0
T11	0	29	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T29	0	9	0	0
T33	0	11	0	0
T45	0	3	0	0
T46	0	23	0	0
T47	0	24	0	0
T51	0	12	0	0
T53	0	10	0	0
T75	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	1456	0	0
T1	12650	7	0	0
T2	23681	0	0	0
T11	0	29	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T29	0	9	0	0
T33	0	11	0	0
T45	0	3	0	0
T46	0	23	0	0
T47	0	24	0	0
T51	0	12	0	0
T53	0	10	0	0
T75	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	706	0	0
T1	12650	7	0	0
T2	23681	0	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T33	0	11	0	0
T36	0	5	0	0
T45	0	3	0	0
T46	0	4	0	0
T47	0	24	0	0
T80	0	7	0	0
T170	0	8	0	0
T173	0	22	0	0
T286	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	706	0	0
T1	12650	7	0	0
T2	23681	0	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T33	0	11	0	0
T36	0	5	0	0
T45	0	3	0	0
T46	0	4	0	0
T47	0	24	0	0
T80	0	7	0	0
T170	0	8	0	0
T173	0	22	0	0
T286	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	60415	0	0
T1	12650	397	0	0
T2	23681	0	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T33	0	1444	0	0
T36	0	382	0	0
T45	0	1533	0	0
T47	0	1741	0	0
T80	0	308	0	0
T170	0	155	0	0
T173	0	1626	0	0
T286	0	756	0	0
T287	0	2293	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	591	0	0
T1	12650	6	0	0
T2	23681	0	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T33	0	8	0	0
T36	0	4	0	0
T45	0	1	0	0
T47	0	21	0	0
T80	0	7	0	0
T170	0	8	0	0
T173	0	19	0	0
T286	0	3	0	0
T287	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T29
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T29
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T1,T2,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T26
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T49,T91,T92
1	0	Covered	T36,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T26
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T26,T28,T13
DetectSt->IdleSt	186	Covered	T49,T36,T91
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T26
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T26
0	1	Covered	T1,T2,T26
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T26
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T36,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T26,T28,T13
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T26
DetectSt	-	-	-	-	1	-	-	Covered	T49,T36,T91
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	927	0	0
CntIncr_A	8063858	48839	0	0
CntNoWrap_A	8063858	7444017	0	0
DetectStDropOut_A	8063858	81	0	0
DetectedOut_A	8063858	14636	0	0
DetectedPulseOut_A	8063858	341	0	0
DisabledIdleSt_A	8063858	7099983	0	0
DisabledNoDetection_A	8063858	7101543	0	0
EnterDebounceSt_A	8063858	502	0	0
EnterDetectSt_A	8063858	426	0	0
EnterStableSt_A	8063858	341	0	0
PulseIsPulse_A	8063858	341	0	0
StayInStableSt	8063858	14259	0	0
gen_high_level_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	304	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	927	0	0
T1	12650	2	0	0
T2	23681	16	0	0
T3	0	10	0	0
T9	0	10	0	0
T13	0	2	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T26	0	1	0	0
T28	0	1	0	0
T32	0	6	0	0
T45	0	4	0	0
T49	0	21	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	48839	0	0
T1	12650	59	0	0
T2	23681	664	0	0
T3	0	825	0	0
T9	0	695	0	0
T13	0	40	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T26	0	20	0	0
T28	0	20	0	0
T32	0	306	0	0
T45	0	624	0	0
T49	0	1612	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444017	0	0
T1	12650	12226	0	0
T2	23681	23209	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	81	0	0
T32	23746	0	0	0
T49	12606	10	0	0
T50	694	0	0	0
T51	5916	0	0	0
T52	626	0	0	0
T53	4866	0	0	0
T54	666	0	0	0
T71	502	0	0	0
T91	0	2	0	0
T92	0	4	0	0
T93	0	7	0	0
T94	0	3	0	0
T95	0	4	0	0
T96	0	5	0	0
T97	0	8	0	0
T99	0	6	0	0
T100	0	2	0	0
T104	415	0	0	0
T105	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	14636	0	0
T1	12650	52	0	0
T2	23681	62	0	0
T3	0	27	0	0
T9	0	78	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	256	0	0
T35	0	4	0	0
T45	0	118	0	0
T47	0	242	0	0
T115	0	43	0	0
T116	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	341	0	0
T1	12650	1	0	0
T2	23681	8	0	0
T3	0	5	0	0
T9	0	5	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	3	0	0
T35	0	1	0	0
T45	0	2	0	0
T47	0	3	0	0
T115	0	3	0	0
T116	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7099983	0	0
T1	12650	11824	0	0
T2	23681	20147	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7101543	0	0
T1	12650	11827	0	0
T2	23681	20147	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	502	0	0
T1	12650	1	0	0
T2	23681	8	0	0
T3	0	5	0	0
T9	0	5	0	0
T13	0	2	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T26	0	1	0	0
T28	0	1	0	0
T32	0	3	0	0
T45	0	2	0	0
T49	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	426	0	0
T1	12650	1	0	0
T2	23681	8	0	0
T3	0	5	0	0
T9	0	5	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	3	0	0
T45	0	2	0	0
T47	0	3	0	0
T49	0	10	0	0
T115	0	3	0	0
T116	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	341	0	0
T1	12650	1	0	0
T2	23681	8	0	0
T3	0	5	0	0
T9	0	5	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	3	0	0
T35	0	1	0	0
T45	0	2	0	0
T47	0	3	0	0
T115	0	3	0	0
T116	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	341	0	0
T1	12650	1	0	0
T2	23681	8	0	0
T3	0	5	0	0
T9	0	5	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	3	0	0
T35	0	1	0	0
T45	0	2	0	0
T47	0	3	0	0
T115	0	3	0	0
T116	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	14259	0	0
T1	12650	51	0	0
T2	23681	54	0	0
T3	0	22	0	0
T9	0	73	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	253	0	0
T35	0	3	0	0
T45	0	116	0	0
T47	0	239	0	0
T115	0	40	0	0
T116	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	304	0	0
T1	12650	1	0	0
T2	23681	8	0	0
T3	0	5	0	0
T9	0	5	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	3	0	0
T35	0	1	0	0
T45	0	2	0	0
T47	0	3	0	0
T115	0	3	0	0
T116	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T29,T11
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T29,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T29,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T29,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T11
1	0	Covered	T1,T11,T45
1	1	Covered	T1,T29,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T29,T11
0	1	Covered	T29,T51,T53
1	0	Covered	T90,T36,T286

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T45
0	1	Covered	T1,T11,T45
1	0	Covered	T45,T288

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T11,T45
1	-	Covered	T1,T11,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T29,T11
DetectSt	168	Covered	T1,T29,T11
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T11,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T29,T11
DebounceSt->IdleSt	163	Covered	T36,T79,T284
DetectSt->IdleSt	186	Covered	T29,T51,T53
DetectSt->StableSt	191	Covered	T1,T11,T45
IdleSt->DebounceSt	148	Covered	T1,T29,T11
StableSt->IdleSt	206	Covered	T1,T11,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T29,T11
0	1	Covered	T1,T29,T11
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T29,T11
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T29,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T29,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T36,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T29,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T79,T284
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T29,T11
DetectSt	-	-	-	-	1	-	-	Covered	T29,T51,T53
DetectSt	-	-	-	-	0	1	-	Covered	T1,T11,T45
DetectSt	-	-	-	-	0	0	-	Covered	T1,T29,T11
StableSt	-	-	-	-	-	-	1	Covered	T1,T11,T45
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T45
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	2810	0	0
CntIncr_A	8063858	98507	0	0
CntNoWrap_A	8063858	7442134	0	0
DetectStDropOut_A	8063858	437	0	0
DetectedOut_A	8063858	59096	0	0
DetectedPulseOut_A	8063858	742	0	0
DisabledIdleSt_A	8063858	7015498	0	0
DisabledNoDetection_A	8063858	7017683	0	0
EnterDebounceSt_A	8063858	1411	0	0
EnterDetectSt_A	8063858	1399	0	0
EnterStableSt_A	8063858	742	0	0
PulseIsPulse_A	8063858	742	0	0
StayInStableSt	8063858	58264	0	0
gen_high_event_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_high_level_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	644	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	2810	0	0
T1	12650	50	0	0
T2	23681	0	0	0
T11	0	48	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T29	0	16	0	0
T33	0	6	0	0
T45	0	50	0	0
T46	0	24	0	0
T47	0	12	0	0
T51	0	12	0	0
T53	0	50	0	0
T75	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	98507	0	0
T1	12650	650	0	0
T2	23681	0	0	0
T11	0	1560	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T29	0	407	0	0
T33	0	168	0	0
T45	0	7225	0	0
T46	0	432	0	0
T47	0	372	0	0
T51	0	393	0	0
T53	0	1126	0	0
T75	0	1250	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7442134	0	0
T1	12650	12178	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	437	0	0
T3	32917	0	0	0
T4	5277	0	0	0
T25	496	0	0	0
T26	1780	0	0	0
T27	524	0	0	0
T29	5170	8	0	0
T31	929	0	0	0
T36	0	1	0	0
T51	0	6	0	0
T53	0	25	0	0
T58	421	0	0	0
T63	509	0	0	0
T67	404	0	0	0
T90	0	3	0	0
T172	0	8	0	0
T263	0	6	0	0
T285	0	2	0	0
T289	0	2	0	0
T290	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	59096	0	0
T1	12650	2098	0	0
T2	23681	0	0	0
T11	0	2016	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T33	0	188	0	0
T36	0	415	0	0
T45	0	71	0	0
T46	0	1115	0	0
T47	0	187	0	0
T75	0	1652	0	0
T80	0	1486	0	0
T170	0	1672	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	742	0	0
T1	12650	25	0	0
T2	23681	0	0	0
T11	0	24	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T33	0	3	0	0
T36	0	5	0	0
T45	0	25	0	0
T46	0	12	0	0
T47	0	6	0	0
T75	0	25	0	0
T80	0	30	0	0
T170	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7015498	0	0
T1	12650	8056	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7017683	0	0
T1	12650	8056	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	1411	0	0
T1	12650	25	0	0
T2	23681	0	0	0
T11	0	24	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T29	0	8	0	0
T33	0	3	0	0
T45	0	25	0	0
T46	0	12	0	0
T47	0	6	0	0
T51	0	6	0	0
T53	0	25	0	0
T75	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	1399	0	0
T1	12650	25	0	0
T2	23681	0	0	0
T11	0	24	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T29	0	8	0	0
T33	0	3	0	0
T45	0	25	0	0
T46	0	12	0	0
T47	0	6	0	0
T51	0	6	0	0
T53	0	25	0	0
T75	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	742	0	0
T1	12650	25	0	0
T2	23681	0	0	0
T11	0	24	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T33	0	3	0	0
T36	0	5	0	0
T45	0	25	0	0
T46	0	12	0	0
T47	0	6	0	0
T75	0	25	0	0
T80	0	30	0	0
T170	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	742	0	0
T1	12650	25	0	0
T2	23681	0	0	0
T11	0	24	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T33	0	3	0	0
T36	0	5	0	0
T45	0	25	0	0
T46	0	12	0	0
T47	0	6	0	0
T75	0	25	0	0
T80	0	30	0	0
T170	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	58264	0	0
T1	12650	2070	0	0
T2	23681	0	0	0
T11	0	1989	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T33	0	184	0	0
T36	0	410	0	0
T45	0	46	0	0
T46	0	1103	0	0
T47	0	181	0	0
T75	0	1625	0	0
T80	0	1455	0	0
T170	0	1665	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	644	0	0
T1	12650	22	0	0
T2	23681	0	0	0
T11	0	21	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T33	0	2	0	0
T36	0	5	0	0
T45	0	23	0	0
T46	0	12	0	0
T47	0	6	0	0
T75	0	23	0	0
T80	0	29	0	0
T170	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T29
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T29
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T77,T291
1	0	Covered	T36,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T36,T80,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T2,T9,T115
DetectSt->IdleSt	186	Covered	T13,T46,T36
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T36,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T9,T115
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T13,T46,T36
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	914	0	0
CntIncr_A	8063858	51209	0	0
CntNoWrap_A	8063858	7444030	0	0
DetectStDropOut_A	8063858	48	0	0
DetectedOut_A	8063858	16012	0	0
DetectedPulseOut_A	8063858	377	0	0
DisabledIdleSt_A	8063858	7106001	0	0
DisabledNoDetection_A	8063858	7107624	0	0
EnterDebounceSt_A	8063858	484	0	0
EnterDetectSt_A	8063858	430	0	0
EnterStableSt_A	8063858	377	0	0
PulseIsPulse_A	8063858	377	0	0
StayInStableSt	8063858	15610	0	0
gen_high_level_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	347	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	914	0	0
T1	12650	4	0	0
T2	23681	5	0	0
T3	0	14	0	0
T9	0	21	0	0
T10	0	2	0	0
T11	0	6	0	0
T13	0	2	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	12	0	0
T49	0	2	0	0
T115	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	51209	0	0
T1	12650	128	0	0
T2	23681	203	0	0
T3	0	749	0	0
T9	0	1530	0	0
T10	0	90	0	0
T11	0	168	0	0
T13	0	139	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	906	0	0
T49	0	149	0	0
T115	0	440	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444030	0	0
T1	12650	12224	0	0
T2	23681	23220	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	48	0	0
T13	13767	1	0	0
T39	2810	0	0	0
T45	22784	0	0	0
T49	12606	0	0	0
T50	694	0	0	0
T68	523	0	0	0
T69	504	0	0	0
T70	502	0	0	0
T71	502	0	0	0
T77	0	7	0	0
T92	0	6	0	0
T94	0	4	0	0
T96	0	1	0	0
T194	0	5	0	0
T276	435	0	0	0
T277	0	1	0	0
T291	0	3	0	0
T292	0	3	0	0
T293	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	16012	0	0
T1	12650	93	0	0
T2	23681	38	0	0
T3	0	448	0	0
T9	0	70	0	0
T10	0	66	0	0
T11	0	229	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	219	0	0
T49	0	4	0	0
T75	0	92	0	0
T115	0	307	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	377	0	0
T1	12650	2	0	0
T2	23681	2	0	0
T3	0	7	0	0
T9	0	10	0	0
T10	0	1	0	0
T11	0	3	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	6	0	0
T49	0	1	0	0
T75	0	2	0	0
T115	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7106001	0	0
T1	12650	10133	0	0
T2	23681	20147	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7107624	0	0
T1	12650	10134	0	0
T2	23681	20147	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	484	0	0
T1	12650	2	0	0
T2	23681	3	0	0
T3	0	7	0	0
T9	0	11	0	0
T10	0	1	0	0
T11	0	3	0	0
T13	0	1	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	6	0	0
T49	0	1	0	0
T115	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	430	0	0
T1	12650	2	0	0
T2	23681	2	0	0
T3	0	7	0	0
T9	0	10	0	0
T10	0	1	0	0
T11	0	3	0	0
T13	0	1	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	6	0	0
T49	0	1	0	0
T115	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	377	0	0
T1	12650	2	0	0
T2	23681	2	0	0
T3	0	7	0	0
T9	0	10	0	0
T10	0	1	0	0
T11	0	3	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	6	0	0
T49	0	1	0	0
T75	0	2	0	0
T115	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	377	0	0
T1	12650	2	0	0
T2	23681	2	0	0
T3	0	7	0	0
T9	0	10	0	0
T10	0	1	0	0
T11	0	3	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	6	0	0
T49	0	1	0	0
T75	0	2	0	0
T115	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	15610	0	0
T1	12650	90	0	0
T2	23681	36	0	0
T3	0	441	0	0
T9	0	60	0	0
T10	0	65	0	0
T11	0	226	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	213	0	0
T49	0	3	0	0
T75	0	90	0	0
T115	0	300	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	347	0	0
T1	12650	1	0	0
T2	23681	2	0	0
T3	0	7	0	0
T9	0	10	0	0
T10	0	1	0	0
T11	0	3	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	6	0	0
T49	0	1	0	0
T75	0	2	0	0
T115	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T29,T11
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T29,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T29,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T29,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T11
1	0	Covered	T1,T11,T45
1	1	Covered	T1,T29,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T29,T11
0	1	Covered	T1,T29,T45
1	0	Covered	T1,T45,T46

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T47,T33
0	1	Covered	T11,T47,T33
1	0	Covered	T294,T295,T212

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T47,T33
1	-	Covered	T11,T47,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T29,T11
DetectSt	168	Covered	T1,T29,T11
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T11,T47,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T29,T11
DebounceSt->IdleSt	163	Covered	T36,T79,T284
DetectSt->IdleSt	186	Covered	T1,T29,T45
DetectSt->StableSt	191	Covered	T11,T47,T33
IdleSt->DebounceSt	148	Covered	T1,T29,T11
StableSt->IdleSt	206	Covered	T11,T47,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T29,T11
0	1	Covered	T1,T29,T11
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T29,T11
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T29,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T29,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T36,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T29,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T79,T284
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T29,T11
DetectSt	-	-	-	-	1	-	-	Covered	T1,T29,T45
DetectSt	-	-	-	-	0	1	-	Covered	T11,T47,T33
DetectSt	-	-	-	-	0	0	-	Covered	T1,T29,T11
StableSt	-	-	-	-	-	-	1	Covered	T11,T47,T33
StableSt	-	-	-	-	-	-	0	Covered	T11,T47,T33
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	2914	0	0
CntIncr_A	8063858	95831	0	0
CntNoWrap_A	8063858	7442030	0	0
DetectStDropOut_A	8063858	486	0	0
DetectedOut_A	8063858	66326	0	0
DetectedPulseOut_A	8063858	763	0	0
DisabledIdleSt_A	8063858	7007490	0	0
DisabledNoDetection_A	8063858	7009666	0	0
EnterDebounceSt_A	8063858	1463	0	0
EnterDetectSt_A	8063858	1452	0	0
EnterStableSt_A	8063858	763	0	0
PulseIsPulse_A	8063858	763	0	0
StayInStableSt	8063858	65464	0	0
gen_high_event_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_high_level_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	637	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	2914	0	0
T1	12650	50	0	0
T2	23681	0	0	0
T11	0	20	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T29	0	34	0	0
T33	0	32	0	0
T45	0	8	0	0
T46	0	46	0	0
T47	0	44	0	0
T51	0	32	0	0
T53	0	20	0	0
T75	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	95831	0	0
T1	12650	1208	0	0
T2	23681	0	0	0
T11	0	490	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T29	0	869	0	0
T33	0	688	0	0
T45	0	1168	0	0
T46	0	1302	0	0
T47	0	1166	0	0
T51	0	1050	0	0
T53	0	443	0	0
T75	0	1298	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7442030	0	0
T1	12650	12178	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	486	0	0
T1	12650	14	0	0
T2	23681	0	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T29	0	17	0	0
T36	0	1	0	0
T45	0	2	0	0
T46	0	11	0	0
T51	0	16	0	0
T53	0	10	0	0
T263	0	9	0	0
T285	0	21	0	0
T296	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	66326	0	0
T11	14443	1145	0	0
T12	1054	0	0	0
T13	13767	0	0	0
T28	9269	0	0	0
T33	0	1828	0	0
T36	0	393	0	0
T45	22784	0	0	0
T47	0	1436	0	0
T68	523	0	0	0
T69	504	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T80	0	851	0	0
T90	0	1426	0	0
T170	0	527	0	0
T172	0	947	0	0
T173	0	1431	0	0
T286	0	3236	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	763	0	0
T11	14443	10	0	0
T12	1054	0	0	0
T13	13767	0	0	0
T28	9269	0	0	0
T33	0	16	0	0
T36	0	5	0	0
T45	22784	0	0	0
T47	0	22	0	0
T68	523	0	0	0
T69	504	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T80	0	25	0	0
T90	0	11	0	0
T170	0	5	0	0
T172	0	8	0	0
T173	0	22	0	0
T286	0	15	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7007490	0	0
T1	12650	9612	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7009666	0	0
T1	12650	9615	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	1463	0	0
T1	12650	25	0	0
T2	23681	0	0	0
T11	0	10	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T29	0	17	0	0
T33	0	16	0	0
T45	0	4	0	0
T46	0	23	0	0
T47	0	22	0	0
T51	0	16	0	0
T53	0	10	0	0
T75	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	1452	0	0
T1	12650	25	0	0
T2	23681	0	0	0
T11	0	10	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T29	0	17	0	0
T33	0	16	0	0
T45	0	4	0	0
T46	0	23	0	0
T47	0	22	0	0
T51	0	16	0	0
T53	0	10	0	0
T75	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	763	0	0
T11	14443	10	0	0
T12	1054	0	0	0
T13	13767	0	0	0
T28	9269	0	0	0
T33	0	16	0	0
T36	0	5	0	0
T45	22784	0	0	0
T47	0	22	0	0
T68	523	0	0	0
T69	504	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T80	0	25	0	0
T90	0	11	0	0
T170	0	5	0	0
T172	0	8	0	0
T173	0	22	0	0
T286	0	15	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	763	0	0
T11	14443	10	0	0
T12	1054	0	0	0
T13	13767	0	0	0
T28	9269	0	0	0
T33	0	16	0	0
T36	0	5	0	0
T45	22784	0	0	0
T47	0	22	0	0
T68	523	0	0	0
T69	504	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T80	0	25	0	0
T90	0	11	0	0
T170	0	5	0	0
T172	0	8	0	0
T173	0	22	0	0
T286	0	15	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	65464	0	0
T11	14443	1135	0	0
T12	1054	0	0	0
T13	13767	0	0	0
T28	9269	0	0	0
T33	0	1804	0	0
T36	0	388	0	0
T45	22784	0	0	0
T47	0	1409	0	0
T68	523	0	0	0
T69	504	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T80	0	824	0	0
T90	0	1411	0	0
T170	0	522	0	0
T172	0	937	0	0
T173	0	1406	0	0
T286	0	3214	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	637	0	0
T11	14443	10	0	0
T12	1054	0	0	0
T13	13767	0	0	0
T28	9269	0	0	0
T33	0	8	0	0
T36	0	5	0	0
T45	22784	0	0	0
T47	0	17	0	0
T68	523	0	0	0
T69	504	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T80	0	23	0	0
T90	0	7	0	0
T170	0	5	0	0
T172	0	6	0	0
T173	0	19	0	0
T286	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T29
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T29
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T3,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T3,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T3,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T2,T16
1	1	Covered	T3,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T11
0	1	Covered	T3,T49,T115
1	0	Covered	T36,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T13
0	1	Covered	T9,T11,T13
1	0	Covered	T36,T297

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T11,T13
1	-	Covered	T9,T11,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T11
DetectSt	168	Covered	T3,T9,T11
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T9,T11,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T11
DebounceSt->IdleSt	163	Covered	T32,T115,T36
DetectSt->IdleSt	186	Covered	T3,T49,T115
DetectSt->StableSt	191	Covered	T9,T11,T13
IdleSt->DebounceSt	148	Covered	T3,T9,T11
StableSt->IdleSt	206	Covered	T9,T11,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T9,T11
0	1	Covered	T3,T9,T11
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T11
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T36,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T115,T291
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T3,T49,T115
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T13
DetectSt	-	-	-	-	0	0	-	Covered	T3,T9,T11
StableSt	-	-	-	-	-	-	1	Covered	T9,T11,T13
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	924	0	0
CntIncr_A	8063858	49191	0	0
CntNoWrap_A	8063858	7444020	0	0
DetectStDropOut_A	8063858	53	0	0
DetectedOut_A	8063858	17127	0	0
DetectedPulseOut_A	8063858	373	0	0
DisabledIdleSt_A	8063858	7099666	0	0
DisabledNoDetection_A	8063858	7101281	0	0
EnterDebounceSt_A	8063858	494	0	0
EnterDetectSt_A	8063858	430	0	0
EnterStableSt_A	8063858	373	0	0
PulseIsPulse_A	8063858	373	0	0
StayInStableSt	8063858	16734	0	0
gen_high_level_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	349	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	924	0	0
T3	32917	24	0	0
T4	5277	0	0	0
T8	550	0	0	0
T9	33067	2	0	0
T10	15720	0	0	0
T11	14443	6	0	0
T13	0	2	0	0
T27	524	0	0	0
T32	0	15	0	0
T33	0	12	0	0
T47	0	10	0	0
T49	0	4	0	0
T59	4405	0	0	0
T63	509	0	0	0
T67	404	0	0	0
T115	0	14	0	0
T144	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	49191	0	0
T3	32917	2052	0	0
T4	5277	0	0	0
T8	550	0	0	0
T9	33067	87	0	0
T10	15720	0	0	0
T11	14443	171	0	0
T13	0	75	0	0
T27	524	0	0	0
T32	0	1344	0	0
T33	0	360	0	0
T47	0	345	0	0
T49	0	306	0	0
T59	4405	0	0	0
T63	509	0	0	0
T67	404	0	0	0
T115	0	650	0	0
T144	0	651	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444020	0	0
T1	12650	12228	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	53	0	0
T3	32917	12	0	0
T4	5277	0	0	0
T8	550	0	0	0
T9	33067	0	0	0
T10	15720	0	0	0
T11	14443	0	0	0
T27	524	0	0	0
T49	0	2	0	0
T59	4405	0	0	0
T63	509	0	0	0
T67	404	0	0	0
T97	0	7	0	0
T115	0	6	0	0
T194	0	2	0	0
T233	0	7	0	0
T298	0	6	0	0
T299	0	2	0	0
T300	0	2	0	0
T301	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	17127	0	0
T9	33067	67	0	0
T10	15720	0	0	0
T11	14443	226	0	0
T12	1054	0	0	0
T13	13767	63	0	0
T28	9269	0	0	0
T32	0	48	0	0
T33	0	251	0	0
T36	0	66	0	0
T47	0	245	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T90	0	332	0	0
T144	0	275	0	0
T286	0	571	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	373	0	0
T9	33067	1	0	0
T10	15720	0	0	0
T11	14443	3	0	0
T12	1054	0	0	0
T13	13767	1	0	0
T28	9269	0	0	0
T32	0	7	0	0
T33	0	6	0	0
T36	0	1	0	0
T47	0	5	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T90	0	4	0	0
T144	0	7	0	0
T286	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7099666	0	0
T1	12650	12228	0	0
T2	23681	20147	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7101281	0	0
T1	12650	12232	0	0
T2	23681	20147	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	494	0	0
T3	32917	12	0	0
T4	5277	0	0	0
T8	550	0	0	0
T9	33067	1	0	0
T10	15720	0	0	0
T11	14443	3	0	0
T13	0	1	0	0
T27	524	0	0	0
T32	0	8	0	0
T33	0	6	0	0
T47	0	5	0	0
T49	0	2	0	0
T59	4405	0	0	0
T63	509	0	0	0
T67	404	0	0	0
T115	0	8	0	0
T144	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	430	0	0
T3	32917	12	0	0
T4	5277	0	0	0
T8	550	0	0	0
T9	33067	1	0	0
T10	15720	0	0	0
T11	14443	3	0	0
T13	0	1	0	0
T27	524	0	0	0
T32	0	7	0	0
T33	0	6	0	0
T47	0	5	0	0
T49	0	2	0	0
T59	4405	0	0	0
T63	509	0	0	0
T67	404	0	0	0
T115	0	6	0	0
T144	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	373	0	0
T9	33067	1	0	0
T10	15720	0	0	0
T11	14443	3	0	0
T12	1054	0	0	0
T13	13767	1	0	0
T28	9269	0	0	0
T32	0	7	0	0
T33	0	6	0	0
T36	0	1	0	0
T47	0	5	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T90	0	4	0	0
T144	0	7	0	0
T286	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	373	0	0
T9	33067	1	0	0
T10	15720	0	0	0
T11	14443	3	0	0
T12	1054	0	0	0
T13	13767	1	0	0
T28	9269	0	0	0
T32	0	7	0	0
T33	0	6	0	0
T36	0	1	0	0
T47	0	5	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T90	0	4	0	0
T144	0	7	0	0
T286	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	16734	0	0
T9	33067	66	0	0
T10	15720	0	0	0
T11	14443	223	0	0
T12	1054	0	0	0
T13	13767	62	0	0
T28	9269	0	0	0
T32	0	41	0	0
T33	0	245	0	0
T36	0	65	0	0
T47	0	237	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T90	0	328	0	0
T144	0	268	0	0
T286	0	564	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	349	0	0
T9	33067	1	0	0
T10	15720	0	0	0
T11	14443	3	0	0
T12	1054	0	0	0
T13	13767	1	0	0
T28	9269	0	0	0
T32	0	7	0	0
T33	0	6	0	0
T47	0	2	0	0
T59	4405	0	0	0
T72	404	0	0	0
T73	425	0	0	0
T74	422	0	0	0
T80	0	2	0	0
T90	0	4	0	0
T144	0	7	0	0
T286	0	7	0	0