Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T29,T11
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T29,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T29,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T29,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T11
1	0	Covered	T1,T11,T45
1	1	Covered	T1,T29,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T29,T11
0	1	Covered	T29,T11,T45
1	0	Covered	T11,T45,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T46,T47
0	1	Covered	T1,T46,T47
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T46,T47
1	-	Covered	T1,T46,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T29,T11
DetectSt	168	Covered	T1,T29,T11
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T46,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T29,T11
DebounceSt->IdleSt	163	Covered	T36,T79,T284
DetectSt->IdleSt	186	Covered	T29,T11,T45
DetectSt->StableSt	191	Covered	T1,T46,T47
IdleSt->DebounceSt	148	Covered	T1,T29,T11
StableSt->IdleSt	206	Covered	T1,T46,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T29,T11
0	1	Covered	T1,T29,T11
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T29,T11
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T29,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T29,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T36,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T29,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T79,T284
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T29,T11
DetectSt	-	-	-	-	1	-	-	Covered	T29,T11,T45
DetectSt	-	-	-	-	0	1	-	Covered	T1,T46,T47
DetectSt	-	-	-	-	0	0	-	Covered	T1,T29,T11
StableSt	-	-	-	-	-	-	1	Covered	T1,T46,T47
StableSt	-	-	-	-	-	-	0	Covered	T1,T46,T47
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	3074	0	0
CntIncr_A	8063858	102991	0	0
CntNoWrap_A	8063858	7441870	0	0
DetectStDropOut_A	8063858	478	0	0
DetectedOut_A	8063858	80396	0	0
DetectedPulseOut_A	8063858	920	0	0
DisabledIdleSt_A	8063858	6997167	0	0
DisabledNoDetection_A	8063858	6999335	0	0
EnterDebounceSt_A	8063858	1546	0	0
EnterDetectSt_A	8063858	1529	0	0
EnterStableSt_A	8063858	920	0	0
PulseIsPulse_A	8063858	920	0	0
StayInStableSt	8063858	79370	0	0
gen_high_event_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_high_level_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	814	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	3074	0	0
T1	12650	50	0	0
T2	23681	0	0	0
T11	0	48	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T29	0	16	0	0
T33	0	8	0	0
T45	0	24	0	0
T46	0	20	0	0
T47	0	30	0	0
T51	0	20	0	0
T53	0	20	0	0
T75	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	102991	0	0
T1	12650	1100	0	0
T2	23681	0	0	0
T11	0	1866	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T29	0	403	0	0
T33	0	284	0	0
T45	0	3500	0	0
T46	0	310	0	0
T47	0	705	0	0
T51	0	653	0	0
T53	0	444	0	0
T75	0	1338	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7441870	0	0
T1	12650	12178	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	478	0	0
T3	32917	0	0	0
T4	5277	0	0	0
T11	0	5	0	0
T25	496	0	0	0
T26	1780	0	0	0
T27	524	0	0	0
T29	5170	8	0	0
T31	929	0	0	0
T36	0	1	0	0
T45	0	10	0	0
T51	0	10	0	0
T53	0	10	0	0
T58	421	0	0	0
T63	509	0	0	0
T67	404	0	0	0
T75	0	14	0	0
T90	0	12	0	0
T172	0	8	0	0
T285	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	80396	0	0
T1	12650	1648	0	0
T2	23681	0	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T33	0	154	0	0
T36	0	394	0	0
T46	0	638	0	0
T47	0	650	0	0
T170	0	267	0	0
T173	0	1183	0	0
T286	0	145	0	0
T287	0	1145	0	0
T302	0	779	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	920	0	0
T1	12650	25	0	0
T2	23681	0	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T33	0	4	0	0
T36	0	5	0	0
T46	0	10	0	0
T47	0	15	0	0
T170	0	8	0	0
T173	0	7	0	0
T286	0	2	0	0
T287	0	15	0	0
T302	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6997167	0	0
T1	12650	8056	0	0
T2	23681	23225	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	6999335	0	0
T1	12650	8056	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	1546	0	0
T1	12650	25	0	0
T2	23681	0	0	0
T11	0	24	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T29	0	8	0	0
T33	0	4	0	0
T45	0	12	0	0
T46	0	10	0	0
T47	0	15	0	0
T51	0	10	0	0
T53	0	10	0	0
T75	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	1529	0	0
T1	12650	25	0	0
T2	23681	0	0	0
T11	0	24	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T29	0	8	0	0
T33	0	4	0	0
T45	0	12	0	0
T46	0	10	0	0
T47	0	15	0	0
T51	0	10	0	0
T53	0	10	0	0
T75	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	920	0	0
T1	12650	25	0	0
T2	23681	0	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T33	0	4	0	0
T36	0	5	0	0
T46	0	10	0	0
T47	0	15	0	0
T170	0	8	0	0
T173	0	7	0	0
T286	0	2	0	0
T287	0	15	0	0
T302	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	920	0	0
T1	12650	25	0	0
T2	23681	0	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T33	0	4	0	0
T36	0	5	0	0
T46	0	10	0	0
T47	0	15	0	0
T170	0	8	0	0
T173	0	7	0	0
T286	0	2	0	0
T287	0	15	0	0
T302	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	79370	0	0
T1	12650	1620	0	0
T2	23681	0	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T33	0	149	0	0
T36	0	389	0	0
T46	0	628	0	0
T47	0	634	0	0
T170	0	259	0	0
T173	0	1175	0	0
T286	0	143	0	0
T287	0	1128	0	0
T302	0	773	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	814	0	0
T1	12650	22	0	0
T2	23681	0	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T33	0	3	0	0
T36	0	5	0	0
T46	0	10	0	0
T47	0	14	0	0
T170	0	8	0	0
T173	0	6	0	0
T286	0	2	0	0
T287	0	13	0	0
T302	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T29
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T29
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T303,T304,T194
1	0	Covered	T36,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T36,T81

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T49,T32,T115
DetectSt->IdleSt	186	Covered	T36,T303,T304
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T36,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T32,T115
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T36,T303,T304
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8063858	837	0	0
CntIncr_A	8063858	45033	0	0
CntNoWrap_A	8063858	7444107	0	0
DetectStDropOut_A	8063858	33	0	0
DetectedOut_A	8063858	15172	0	0
DetectedPulseOut_A	8063858	355	0	0
DisabledIdleSt_A	8063858	7088241	0	0
DisabledNoDetection_A	8063858	7089863	0	0
EnterDebounceSt_A	8063858	445	0	0
EnterDetectSt_A	8063858	392	0	0
EnterStableSt_A	8063858	355	0	0
PulseIsPulse_A	8063858	355	0	0
StayInStableSt	8063858	14785	0	0
gen_high_level_sva.HighLevelEvent_A	8063858	7447309	0	0
gen_not_sticky_sva.StableStDropOut_A	8063858	319	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	837	0	0
T1	12650	6	0	0
T2	23681	10	0	0
T3	0	14	0	0
T9	0	6	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	17	0	0
T33	0	2	0	0
T34	0	4	0	0
T49	0	7	0	0
T115	0	13	0	0
T144	0	17	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	45033	0	0
T1	12650	165	0	0
T2	23681	400	0	0
T3	0	1085	0	0
T9	0	297	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	1365	0	0
T33	0	52	0	0
T34	0	264	0	0
T49	0	392	0	0
T115	0	584	0	0
T144	0	1081	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7444107	0	0
T1	12650	12222	0	0
T2	23681	23215	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	33	0	0
T42	839	0	0	0
T194	0	1	0	0
T202	0	2	0	0
T217	623	0	0	0
T291	12076	0	0	0
T303	33641	6	0	0
T304	0	1	0	0
T305	0	2	0	0
T306	0	7	0	0
T307	0	1	0	0
T308	0	1	0	0
T309	0	8	0	0
T310	0	4	0	0
T311	464	0	0	0
T312	496	0	0	0
T313	504	0	0	0
T314	8508	0	0	0
T315	402	0	0	0
T316	496	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	15172	0	0
T1	12650	166	0	0
T2	23681	50	0	0
T3	0	107	0	0
T9	0	165	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	213	0	0
T33	0	50	0	0
T34	0	102	0	0
T49	0	139	0	0
T115	0	26	0	0
T144	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	355	0	0
T1	12650	3	0	0
T2	23681	5	0	0
T3	0	7	0	0
T9	0	3	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	8	0	0
T33	0	1	0	0
T34	0	2	0	0
T49	0	3	0	0
T115	0	6	0	0
T144	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7088241	0	0
T1	12650	10583	0	0
T2	23681	20147	0	0
T5	408	7	0	0
T6	537	136	0	0
T7	504	103	0	0
T14	413	12	0	0
T15	425	24	0	0
T16	1709	507	0	0
T17	405	4	0	0
T18	885	484	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7089863	0	0
T1	12650	10584	0	0
T2	23681	20147	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	445	0	0
T1	12650	3	0	0
T2	23681	5	0	0
T3	0	7	0	0
T9	0	3	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	9	0	0
T33	0	1	0	0
T34	0	2	0	0
T49	0	4	0	0
T115	0	7	0	0
T144	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	392	0	0
T1	12650	3	0	0
T2	23681	5	0	0
T3	0	7	0	0
T9	0	3	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	8	0	0
T33	0	1	0	0
T34	0	2	0	0
T49	0	3	0	0
T115	0	6	0	0
T144	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	355	0	0
T1	12650	3	0	0
T2	23681	5	0	0
T3	0	7	0	0
T9	0	3	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	8	0	0
T33	0	1	0	0
T34	0	2	0	0
T49	0	3	0	0
T115	0	6	0	0
T144	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	355	0	0
T1	12650	3	0	0
T2	23681	5	0	0
T3	0	7	0	0
T9	0	3	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	8	0	0
T33	0	1	0	0
T34	0	2	0	0
T49	0	3	0	0
T115	0	6	0	0
T144	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	14785	0	0
T1	12650	161	0	0
T2	23681	45	0	0
T3	0	100	0	0
T9	0	162	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	205	0	0
T33	0	49	0	0
T34	0	100	0	0
T49	0	136	0	0
T115	0	20	0	0
T144	0	33	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	7447309	0	0
T1	12650	12232	0	0
T2	23681	23235	0	0
T5	408	8	0	0
T6	537	137	0	0
T7	504	104	0	0
T14	413	13	0	0
T15	425	25	0	0
T16	1709	509	0	0
T17	405	5	0	0
T18	885	485	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8063858	319	0	0
T1	12650	1	0	0
T2	23681	5	0	0
T3	0	7	0	0
T9	0	3	0	0
T14	413	0	0	0
T15	425	0	0	0
T16	1709	0	0	0
T17	405	0	0	0
T18	885	0	0	0
T19	428	0	0	0
T20	499	0	0	0
T21	439	0	0	0
T32	0	8	0	0
T33	0	1	0	0
T34	0	2	0	0
T49	0	3	0	0
T115	0	6	0	0
T144	0	8	0	0