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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.08 99.37 96.78 100.00 97.44 98.82 99.61 94.56


Total test records in report: 906
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T785 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.693424766 Jun 29 06:27:32 PM PDT 24 Jun 29 06:27:38 PM PDT 24 2012024721 ps
T327 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2822012538 Jun 29 06:27:28 PM PDT 24 Jun 29 06:27:51 PM PDT 24 9635828593 ps
T355 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.908843676 Jun 29 06:27:23 PM PDT 24 Jun 29 06:27:28 PM PDT 24 2093209875 ps
T325 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.33366875 Jun 29 06:27:13 PM PDT 24 Jun 29 06:27:16 PM PDT 24 2207796367 ps
T786 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1511064743 Jun 29 06:27:15 PM PDT 24 Jun 29 06:27:23 PM PDT 24 2013079029 ps
T787 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.1070666133 Jun 29 06:27:14 PM PDT 24 Jun 29 06:27:16 PM PDT 24 2057678370 ps
T788 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1423413195 Jun 29 06:27:23 PM PDT 24 Jun 29 06:27:27 PM PDT 24 2017165874 ps
T357 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.239683633 Jun 29 06:27:14 PM PDT 24 Jun 29 06:27:30 PM PDT 24 6014357533 ps
T326 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3301906989 Jun 29 06:27:08 PM PDT 24 Jun 29 06:27:12 PM PDT 24 8128176324 ps
T323 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1300640039 Jun 29 06:27:22 PM PDT 24 Jun 29 06:27:26 PM PDT 24 2159410062 ps
T321 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2421228568 Jun 29 06:27:18 PM PDT 24 Jun 29 06:29:03 PM PDT 24 42443939318 ps
T358 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3120004745 Jun 29 06:27:22 PM PDT 24 Jun 29 06:27:29 PM PDT 24 2052692017 ps
T789 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2038685856 Jun 29 06:27:31 PM PDT 24 Jun 29 06:27:33 PM PDT 24 2047079512 ps
T790 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2777603860 Jun 29 06:27:20 PM PDT 24 Jun 29 06:27:22 PM PDT 24 2044439150 ps
T359 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3653312444 Jun 29 06:27:14 PM PDT 24 Jun 29 06:27:19 PM PDT 24 2064369647 ps
T791 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3640008302 Jun 29 06:27:24 PM PDT 24 Jun 29 06:27:31 PM PDT 24 2011133129 ps
T370 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1008587366 Jun 29 06:27:23 PM PDT 24 Jun 29 06:27:30 PM PDT 24 4724746493 ps
T792 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3417422486 Jun 29 06:27:28 PM PDT 24 Jun 29 06:27:32 PM PDT 24 2041182304 ps
T360 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.75043173 Jun 29 06:27:14 PM PDT 24 Jun 29 06:27:35 PM PDT 24 23607224456 ps
T318 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.223709167 Jun 29 06:27:17 PM PDT 24 Jun 29 06:27:25 PM PDT 24 2060634099 ps
T371 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2827402806 Jun 29 06:27:20 PM PDT 24 Jun 29 06:27:26 PM PDT 24 2033718589 ps
T372 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.405938227 Jun 29 06:27:16 PM PDT 24 Jun 29 06:27:24 PM PDT 24 5220682727 ps
T793 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3785340331 Jun 29 06:27:28 PM PDT 24 Jun 29 06:27:34 PM PDT 24 2012189525 ps
T794 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.3497851430 Jun 29 06:27:34 PM PDT 24 Jun 29 06:27:36 PM PDT 24 2025483955 ps
T795 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1766596319 Jun 29 06:27:29 PM PDT 24 Jun 29 06:27:35 PM PDT 24 2012676324 ps
T796 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1041312364 Jun 29 06:27:32 PM PDT 24 Jun 29 06:27:38 PM PDT 24 2011806866 ps
T361 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.4195729156 Jun 29 06:27:16 PM PDT 24 Jun 29 06:29:12 PM PDT 24 49162146877 ps
T797 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1239132116 Jun 29 06:27:30 PM PDT 24 Jun 29 06:27:32 PM PDT 24 2039451954 ps
T798 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2465165684 Jun 29 06:27:16 PM PDT 24 Jun 29 06:27:23 PM PDT 24 2085676317 ps
T799 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1718173976 Jun 29 06:27:37 PM PDT 24 Jun 29 06:27:40 PM PDT 24 2037423082 ps
T800 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.1750911292 Jun 29 06:27:13 PM PDT 24 Jun 29 06:27:46 PM PDT 24 9102374208 ps
T319 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1110491742 Jun 29 06:27:22 PM PDT 24 Jun 29 06:27:26 PM PDT 24 2089412609 ps
T801 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2718801904 Jun 29 06:27:14 PM PDT 24 Jun 29 06:27:17 PM PDT 24 2043691383 ps
T802 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3036916015 Jun 29 06:27:30 PM PDT 24 Jun 29 06:27:34 PM PDT 24 2021154953 ps
T803 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2483079683 Jun 29 06:27:22 PM PDT 24 Jun 29 06:27:24 PM PDT 24 2037608268 ps
T328 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.210516318 Jun 29 06:27:22 PM PDT 24 Jun 29 06:27:31 PM PDT 24 2053513580 ps
T329 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1877200807 Jun 29 06:27:08 PM PDT 24 Jun 29 06:27:12 PM PDT 24 2545578470 ps
T804 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1893004746 Jun 29 06:27:14 PM PDT 24 Jun 29 06:27:21 PM PDT 24 2101652373 ps
T805 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.21195921 Jun 29 06:27:13 PM PDT 24 Jun 29 06:27:15 PM PDT 24 2030072104 ps
T322 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3824375495 Jun 29 06:27:12 PM PDT 24 Jun 29 06:28:02 PM PDT 24 22279578060 ps
T331 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2632918542 Jun 29 06:27:24 PM PDT 24 Jun 29 06:27:54 PM PDT 24 42844098227 ps
T48 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.729471173 Jun 29 06:27:16 PM PDT 24 Jun 29 06:27:25 PM PDT 24 2342113362 ps
T806 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3798031801 Jun 29 06:27:25 PM PDT 24 Jun 29 06:27:32 PM PDT 24 2076646604 ps
T395 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3121673652 Jun 29 06:27:15 PM PDT 24 Jun 29 06:29:02 PM PDT 24 42394925446 ps
T807 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.71876682 Jun 29 06:27:21 PM PDT 24 Jun 29 06:27:24 PM PDT 24 2132499388 ps
T330 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.597745728 Jun 29 06:27:13 PM PDT 24 Jun 29 06:27:20 PM PDT 24 2089907870 ps
T808 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2653606723 Jun 29 06:27:13 PM PDT 24 Jun 29 06:27:18 PM PDT 24 2077469217 ps
T809 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.1828473858 Jun 29 06:27:29 PM PDT 24 Jun 29 06:27:35 PM PDT 24 2012615909 ps
T332 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.880825833 Jun 29 06:27:23 PM PDT 24 Jun 29 06:27:51 PM PDT 24 42528921067 ps
T362 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.352046100 Jun 29 06:27:14 PM PDT 24 Jun 29 06:27:16 PM PDT 24 2122829923 ps
T810 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.1242104322 Jun 29 06:27:13 PM PDT 24 Jun 29 06:27:39 PM PDT 24 9692324489 ps
T811 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.3657905450 Jun 29 06:27:15 PM PDT 24 Jun 29 06:27:22 PM PDT 24 2015051133 ps
T812 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3279217472 Jun 29 06:27:13 PM PDT 24 Jun 29 06:27:16 PM PDT 24 2249282020 ps
T813 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.928838613 Jun 29 06:27:24 PM PDT 24 Jun 29 06:27:31 PM PDT 24 2011357689 ps
T363 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.825944983 Jun 29 06:27:09 PM PDT 24 Jun 29 06:27:11 PM PDT 24 2043161754 ps
T814 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3485288215 Jun 29 06:27:13 PM PDT 24 Jun 29 06:27:17 PM PDT 24 4072023000 ps
T815 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.2963048522 Jun 29 06:27:14 PM PDT 24 Jun 29 06:27:21 PM PDT 24 2033857426 ps
T816 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2929295542 Jun 29 06:27:15 PM PDT 24 Jun 29 06:27:18 PM PDT 24 2271334924 ps
T817 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.184796862 Jun 29 06:27:28 PM PDT 24 Jun 29 06:27:32 PM PDT 24 2021145825 ps
T818 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1164681067 Jun 29 06:27:24 PM PDT 24 Jun 29 06:27:50 PM PDT 24 10252923743 ps
T819 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.2369382601 Jun 29 06:27:14 PM PDT 24 Jun 29 06:27:24 PM PDT 24 6018430145 ps
T820 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.425114735 Jun 29 06:27:14 PM PDT 24 Jun 29 06:27:18 PM PDT 24 2023285849 ps
T821 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.172256986 Jun 29 06:27:33 PM PDT 24 Jun 29 06:27:35 PM PDT 24 2036781313 ps
T822 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.1993841811 Jun 29 06:27:11 PM PDT 24 Jun 29 06:27:24 PM PDT 24 4968752251 ps
T823 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3115280814 Jun 29 06:27:22 PM PDT 24 Jun 29 06:27:27 PM PDT 24 2014419977 ps
T333 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1112234952 Jun 29 06:27:23 PM PDT 24 Jun 29 06:27:26 PM PDT 24 2105431390 ps
T364 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.4085996420 Jun 29 06:27:13 PM PDT 24 Jun 29 06:27:18 PM PDT 24 3036530905 ps
T824 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.2517128117 Jun 29 06:27:40 PM PDT 24 Jun 29 06:27:47 PM PDT 24 2013352911 ps
T825 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.581580621 Jun 29 06:27:29 PM PDT 24 Jun 29 06:27:31 PM PDT 24 2034923107 ps
T365 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.377342000 Jun 29 06:27:23 PM PDT 24 Jun 29 06:27:28 PM PDT 24 2054639560 ps
T826 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.437583933 Jun 29 06:27:21 PM PDT 24 Jun 29 06:27:25 PM PDT 24 4491320741 ps
T827 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2559679554 Jun 29 06:27:14 PM PDT 24 Jun 29 06:27:22 PM PDT 24 5005937165 ps
T368 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3535184671 Jun 29 06:27:15 PM PDT 24 Jun 29 06:27:20 PM PDT 24 2054095102 ps
T334 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1660119070 Jun 29 06:27:15 PM PDT 24 Jun 29 06:27:35 PM PDT 24 22244187223 ps
T828 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1920666208 Jun 29 06:27:15 PM PDT 24 Jun 29 06:27:22 PM PDT 24 2068294030 ps
T829 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2089422106 Jun 29 06:27:24 PM PDT 24 Jun 29 06:27:55 PM PDT 24 42508072668 ps
T830 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1246685133 Jun 29 06:27:15 PM PDT 24 Jun 29 06:27:22 PM PDT 24 2015683465 ps
T831 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2730906572 Jun 29 06:27:22 PM PDT 24 Jun 29 06:27:28 PM PDT 24 2072456144 ps
T832 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1648950163 Jun 29 06:27:24 PM PDT 24 Jun 29 06:27:27 PM PDT 24 2126152953 ps
T833 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.397667919 Jun 29 06:27:17 PM PDT 24 Jun 29 06:27:24 PM PDT 24 2053090647 ps
T834 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.4126829117 Jun 29 06:27:29 PM PDT 24 Jun 29 06:27:36 PM PDT 24 2070593282 ps
T835 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.141749566 Jun 29 06:27:24 PM PDT 24 Jun 29 06:27:38 PM PDT 24 42909901696 ps
T366 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.527426227 Jun 29 06:27:13 PM PDT 24 Jun 29 06:27:25 PM PDT 24 2891232156 ps
T836 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3939023622 Jun 29 06:27:21 PM PDT 24 Jun 29 06:27:23 PM PDT 24 2033702930 ps
T837 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2577736064 Jun 29 06:27:08 PM PDT 24 Jun 29 06:27:10 PM PDT 24 2031812756 ps
T838 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.676912309 Jun 29 06:27:15 PM PDT 24 Jun 29 06:27:19 PM PDT 24 2217456751 ps
T839 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2061342051 Jun 29 06:27:15 PM PDT 24 Jun 29 06:27:21 PM PDT 24 2076927760 ps
T840 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1240775785 Jun 29 06:27:13 PM PDT 24 Jun 29 06:27:22 PM PDT 24 5215140882 ps
T841 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.624697379 Jun 29 06:27:14 PM PDT 24 Jun 29 06:27:19 PM PDT 24 2066969616 ps
T842 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.2644429352 Jun 29 06:27:14 PM PDT 24 Jun 29 06:27:19 PM PDT 24 2056807178 ps
T843 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2828670413 Jun 29 06:27:11 PM PDT 24 Jun 29 06:27:23 PM PDT 24 4360726267 ps
T367 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1347582779 Jun 29 06:27:12 PM PDT 24 Jun 29 06:28:07 PM PDT 24 44001860470 ps
T844 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.3085855091 Jun 29 06:27:29 PM PDT 24 Jun 29 06:27:31 PM PDT 24 2057121921 ps
T845 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.1558462570 Jun 29 06:27:16 PM PDT 24 Jun 29 06:27:21 PM PDT 24 2369792963 ps
T846 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.3789076445 Jun 29 06:27:24 PM PDT 24 Jun 29 06:28:19 PM PDT 24 22233517251 ps
T847 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1920999662 Jun 29 06:27:23 PM PDT 24 Jun 29 06:27:27 PM PDT 24 2015602517 ps
T848 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.531528309 Jun 29 06:27:40 PM PDT 24 Jun 29 06:27:47 PM PDT 24 2012918859 ps
T849 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.712073243 Jun 29 06:27:23 PM PDT 24 Jun 29 06:27:28 PM PDT 24 2563301104 ps
T850 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2756257277 Jun 29 06:27:33 PM PDT 24 Jun 29 06:27:35 PM PDT 24 2052633172 ps
T851 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1314425528 Jun 29 06:27:22 PM PDT 24 Jun 29 06:27:28 PM PDT 24 2065881559 ps
T852 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1726727524 Jun 29 06:27:15 PM PDT 24 Jun 29 06:27:18 PM PDT 24 2121099052 ps
T369 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2309676874 Jun 29 06:27:09 PM PDT 24 Jun 29 06:30:59 PM PDT 24 48759973534 ps
T853 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1696725809 Jun 29 06:27:28 PM PDT 24 Jun 29 06:27:32 PM PDT 24 2019331997 ps
T854 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.446825077 Jun 29 06:27:16 PM PDT 24 Jun 29 06:27:23 PM PDT 24 2016678635 ps
T855 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2521845959 Jun 29 06:27:17 PM PDT 24 Jun 29 06:27:24 PM PDT 24 2050994273 ps
T856 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3964162980 Jun 29 06:27:24 PM PDT 24 Jun 29 06:27:31 PM PDT 24 2017821820 ps
T857 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.515370593 Jun 29 06:27:24 PM PDT 24 Jun 29 06:27:31 PM PDT 24 7676002321 ps
T858 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.671256523 Jun 29 06:27:16 PM PDT 24 Jun 29 06:27:21 PM PDT 24 2015021320 ps
T859 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.311862262 Jun 29 06:27:24 PM PDT 24 Jun 29 06:27:27 PM PDT 24 2094593475 ps
T860 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2977849173 Jun 29 06:27:23 PM PDT 24 Jun 29 06:27:41 PM PDT 24 22277251996 ps
T861 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2477978923 Jun 29 06:27:13 PM PDT 24 Jun 29 06:27:21 PM PDT 24 2061733151 ps
T862 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.993881352 Jun 29 06:27:16 PM PDT 24 Jun 29 06:27:21 PM PDT 24 2423747390 ps
T863 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.739658439 Jun 29 06:27:14 PM PDT 24 Jun 29 06:27:18 PM PDT 24 2054243437 ps
T864 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3380368409 Jun 29 06:27:14 PM PDT 24 Jun 29 06:27:21 PM PDT 24 2050992594 ps
T865 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.874913654 Jun 29 06:27:21 PM PDT 24 Jun 29 06:27:23 PM PDT 24 2029113183 ps
T866 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1670832178 Jun 29 06:27:15 PM PDT 24 Jun 29 06:27:22 PM PDT 24 3045534146 ps
T867 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2951866366 Jun 29 06:27:24 PM PDT 24 Jun 29 06:27:34 PM PDT 24 10273356201 ps
T868 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.301710168 Jun 29 06:27:08 PM PDT 24 Jun 29 06:27:12 PM PDT 24 4059913927 ps
T869 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.905154850 Jun 29 06:27:14 PM PDT 24 Jun 29 06:27:27 PM PDT 24 22510899099 ps
T870 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3231992169 Jun 29 06:27:29 PM PDT 24 Jun 29 06:27:34 PM PDT 24 2010297360 ps
T871 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.744619534 Jun 29 06:27:28 PM PDT 24 Jun 29 06:27:30 PM PDT 24 2062947050 ps
T872 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.2683348224 Jun 29 06:27:13 PM PDT 24 Jun 29 06:27:44 PM PDT 24 42512729079 ps
T873 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1349332729 Jun 29 06:27:28 PM PDT 24 Jun 29 06:27:30 PM PDT 24 2048840300 ps
T874 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2073825937 Jun 29 06:27:22 PM PDT 24 Jun 29 06:27:29 PM PDT 24 2012645437 ps
T875 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3164735846 Jun 29 06:27:13 PM PDT 24 Jun 29 06:27:29 PM PDT 24 22280615310 ps
T876 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.711301076 Jun 29 06:27:21 PM PDT 24 Jun 29 06:29:18 PM PDT 24 42405719790 ps
T877 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2271856572 Jun 29 06:27:20 PM PDT 24 Jun 29 06:27:27 PM PDT 24 2019612801 ps
T878 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.2162278751 Jun 29 06:27:29 PM PDT 24 Jun 29 06:27:35 PM PDT 24 2015854617 ps
T879 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3968472194 Jun 29 06:27:14 PM PDT 24 Jun 29 06:27:21 PM PDT 24 2040899599 ps
T880 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1273505609 Jun 29 06:27:28 PM PDT 24 Jun 29 06:27:31 PM PDT 24 2085810847 ps
T881 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1299193993 Jun 29 06:27:27 PM PDT 24 Jun 29 06:27:29 PM PDT 24 2058332278 ps
T882 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.3508387321 Jun 29 06:27:16 PM PDT 24 Jun 29 06:27:24 PM PDT 24 2058051176 ps
T883 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.990565109 Jun 29 06:27:31 PM PDT 24 Jun 29 06:27:33 PM PDT 24 2037120207 ps
T884 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2936705249 Jun 29 06:27:15 PM PDT 24 Jun 29 06:27:21 PM PDT 24 23521328756 ps
T885 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1073497639 Jun 29 06:27:20 PM PDT 24 Jun 29 06:27:25 PM PDT 24 2061740666 ps
T886 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3895088847 Jun 29 06:27:15 PM PDT 24 Jun 29 06:27:50 PM PDT 24 42917567916 ps
T887 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.4270058009 Jun 29 06:27:17 PM PDT 24 Jun 29 06:27:22 PM PDT 24 2171665474 ps
T888 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3277111118 Jun 29 06:27:15 PM PDT 24 Jun 29 06:27:21 PM PDT 24 5348563739 ps
T889 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.4176360522 Jun 29 06:27:34 PM PDT 24 Jun 29 06:27:38 PM PDT 24 2025547631 ps
T890 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.4064028179 Jun 29 06:27:21 PM PDT 24 Jun 29 06:27:25 PM PDT 24 4447936948 ps
T891 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1536468305 Jun 29 06:27:21 PM PDT 24 Jun 29 06:27:25 PM PDT 24 2349829736 ps
T892 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.542886392 Jun 29 06:27:14 PM PDT 24 Jun 29 06:28:36 PM PDT 24 41584866396 ps
T893 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3732385234 Jun 29 06:27:23 PM PDT 24 Jun 29 06:27:27 PM PDT 24 2260612232 ps
T894 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3662620738 Jun 29 06:27:17 PM PDT 24 Jun 29 06:27:44 PM PDT 24 10272260392 ps
T895 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1660057128 Jun 29 06:27:11 PM PDT 24 Jun 29 06:27:13 PM PDT 24 2130972662 ps
T896 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3165698415 Jun 29 06:27:14 PM PDT 24 Jun 29 06:27:18 PM PDT 24 2238816958 ps
T897 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.4097123698 Jun 29 06:27:14 PM PDT 24 Jun 29 06:27:18 PM PDT 24 2044464802 ps
T898 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2486112854 Jun 29 06:27:20 PM PDT 24 Jun 29 06:27:39 PM PDT 24 9292303657 ps
T899 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3280832283 Jun 29 06:27:14 PM PDT 24 Jun 29 06:28:12 PM PDT 24 22219060407 ps
T900 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1302641361 Jun 29 06:27:39 PM PDT 24 Jun 29 06:27:46 PM PDT 24 2016185309 ps
T901 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2507853430 Jun 29 06:27:21 PM PDT 24 Jun 29 06:27:28 PM PDT 24 2085263514 ps
T902 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1995293233 Jun 29 06:27:23 PM PDT 24 Jun 29 06:27:26 PM PDT 24 2219862641 ps
T903 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3018334376 Jun 29 06:27:15 PM PDT 24 Jun 29 06:28:15 PM PDT 24 22206252759 ps
T904 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2056984431 Jun 29 06:27:12 PM PDT 24 Jun 29 06:27:21 PM PDT 24 6018860916 ps
T905 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.919212118 Jun 29 06:27:22 PM PDT 24 Jun 29 06:27:38 PM PDT 24 22473294245 ps
T906 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2464592690 Jun 29 06:27:30 PM PDT 24 Jun 29 06:27:32 PM PDT 24 2054663888 ps

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2191961089
Short name T1
Test name
Test status
Simulation time 63253724169 ps
CPU time 39.89 seconds
Started Jun 29 06:33:20 PM PDT 24
Finished Jun 29 06:34:01 PM PDT 24
Peak memory 201804 kb
Host smart-059d8a3a-fa61-4f8a-aad7-70189fff1351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191961089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_w
ith_pre_cond.2191961089
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.3696558354
Short name T10
Test name
Test status
Simulation time 78601795979 ps
CPU time 187.3 seconds
Started Jun 29 06:32:15 PM PDT 24
Finished Jun 29 06:35:23 PM PDT 24
Peak memory 210156 kb
Host smart-7037cb3a-463c-4921-83bc-1c9bf0b445b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696558354 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.3696558354
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.2433115398
Short name T36
Test name
Test status
Simulation time 40070697166 ps
CPU time 105.71 seconds
Started Jun 29 06:31:26 PM PDT 24
Finished Jun 29 06:33:13 PM PDT 24
Peak memory 201584 kb
Host smart-c970325b-546c-4a28-8d18-d33fc0e8a4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433115398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.2433115398
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1273415145
Short name T13
Test name
Test status
Simulation time 68839536471 ps
CPU time 61.18 seconds
Started Jun 29 06:32:20 PM PDT 24
Finished Jun 29 06:33:22 PM PDT 24
Peak memory 218296 kb
Host smart-8b9e3547-f104-4c91-ab11-0867eb1c4dfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273415145 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.1273415145
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.2329396001
Short name T79
Test name
Test status
Simulation time 32320642734 ps
CPU time 77.1 seconds
Started Jun 29 06:31:25 PM PDT 24
Finished Jun 29 06:32:43 PM PDT 24
Peak memory 201588 kb
Host smart-0122f542-8b75-408e-858e-1505211a14f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329396001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.2329396001
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.793695591
Short name T30
Test name
Test status
Simulation time 22269246925 ps
CPU time 19.06 seconds
Started Jun 29 06:27:07 PM PDT 24
Finished Jun 29 06:27:27 PM PDT 24
Peak memory 202260 kb
Host smart-f9c75460-de16-4a51-aad0-6658dcbaa689
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793695591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_tl_intg_err.793695591
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.4010635165
Short name T2
Test name
Test status
Simulation time 118412174139 ps
CPU time 311.47 seconds
Started Jun 29 06:31:27 PM PDT 24
Finished Jun 29 06:36:40 PM PDT 24
Peak memory 201776 kb
Host smart-fed7840f-7dab-4fd2-8eac-177603de9aa0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010635165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_combo_detect.4010635165
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.2378047751
Short name T93
Test name
Test status
Simulation time 221660151535 ps
CPU time 129.21 seconds
Started Jun 29 06:33:02 PM PDT 24
Finished Jun 29 06:35:12 PM PDT 24
Peak memory 212936 kb
Host smart-a8212c89-4ac5-4e2a-be70-3ce350fe041c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378047751 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.2378047751
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.2165880697
Short name T41
Test name
Test status
Simulation time 76746305382 ps
CPU time 49.36 seconds
Started Jun 29 06:32:28 PM PDT 24
Finished Jun 29 06:33:18 PM PDT 24
Peak memory 218380 kb
Host smart-b311f345-3ebd-4d17-a5e5-ba2d85a923aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165880697 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.2165880697
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2439905243
Short name T33
Test name
Test status
Simulation time 123766560914 ps
CPU time 316.45 seconds
Started Jun 29 06:33:29 PM PDT 24
Finished Jun 29 06:38:46 PM PDT 24
Peak memory 201884 kb
Host smart-b0ecb0a5-e5a0-4b32-b02e-7f2c75131cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439905243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_w
ith_pre_cond.2439905243
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.1444811631
Short name T412
Test name
Test status
Simulation time 86934328941 ps
CPU time 54.46 seconds
Started Jun 29 06:32:00 PM PDT 24
Finished Jun 29 06:32:55 PM PDT 24
Peak memory 214564 kb
Host smart-96a6eb7e-859a-4f3b-a268-aadeae603ff0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444811631 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.1444811631
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.398345909
Short name T149
Test name
Test status
Simulation time 38924282917 ps
CPU time 23.28 seconds
Started Jun 29 06:32:39 PM PDT 24
Finished Jun 29 06:33:03 PM PDT 24
Peak memory 210168 kb
Host smart-aa1ff298-ad00-456e-9c0f-a23c80856542
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398345909 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.398345909
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.1694053953
Short name T115
Test name
Test status
Simulation time 129050830487 ps
CPU time 104.3 seconds
Started Jun 29 06:32:36 PM PDT 24
Finished Jun 29 06:34:21 PM PDT 24
Peak memory 201848 kb
Host smart-c1827934-f6c8-46cb-a52a-442bdbe3a34e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694053953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.1694053953
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.4071038108
Short name T7
Test name
Test status
Simulation time 2526044190 ps
CPU time 2.28 seconds
Started Jun 29 06:31:38 PM PDT 24
Finished Jun 29 06:31:41 PM PDT 24
Peak memory 201516 kb
Host smart-03c8b673-bbf9-4d6e-9c2f-7ba59db0229d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071038108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.4071038108
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.3349588359
Short name T59
Test name
Test status
Simulation time 22030653162 ps
CPU time 24.39 seconds
Started Jun 29 06:31:25 PM PDT 24
Finished Jun 29 06:31:51 PM PDT 24
Peak memory 221280 kb
Host smart-a0b4f559-5d97-4f28-ab25-fa94bebcb53e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349588359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.3349588359
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.2295682413
Short name T151
Test name
Test status
Simulation time 5846961385 ps
CPU time 6.01 seconds
Started Jun 29 06:33:10 PM PDT 24
Finished Jun 29 06:33:17 PM PDT 24
Peak memory 201556 kb
Host smart-a8df57c8-a01e-4dd7-8570-ce18e37e2a71
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295682413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.2295682413
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1622573611
Short name T62
Test name
Test status
Simulation time 51494947660 ps
CPU time 122.64 seconds
Started Jun 29 06:31:53 PM PDT 24
Finished Jun 29 06:33:57 PM PDT 24
Peak memory 210224 kb
Host smart-f870ffa7-5994-4f25-8de2-e7d16a99b6a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622573611 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.1622573611
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.1436520671
Short name T85
Test name
Test status
Simulation time 182152832106 ps
CPU time 240.77 seconds
Started Jun 29 06:31:24 PM PDT 24
Finished Jun 29 06:35:25 PM PDT 24
Peak memory 201852 kb
Host smart-1d5553bd-0093-4521-94af-2acbfc7af68e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436520671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.1436520671
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.2136625797
Short name T61
Test name
Test status
Simulation time 340161628187 ps
CPU time 52.45 seconds
Started Jun 29 06:31:24 PM PDT 24
Finished Jun 29 06:32:17 PM PDT 24
Peak memory 210120 kb
Host smart-e55028cf-17ff-4b09-8583-a1594d841224
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136625797 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.2136625797
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3653312444
Short name T359
Test name
Test status
Simulation time 2064369647 ps
CPU time 3.89 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:27:19 PM PDT 24
Peak memory 201972 kb
Host smart-218c3efb-fb3d-4cf0-8f62-d32e74b472ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653312444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_r
w.3653312444
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.3812599233
Short name T298
Test name
Test status
Simulation time 155206990168 ps
CPU time 320.96 seconds
Started Jun 29 06:31:45 PM PDT 24
Finished Jun 29 06:37:07 PM PDT 24
Peak memory 201836 kb
Host smart-6622755e-9b1f-40f8-839f-643d2a4bc76d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812599233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_combo_detect.3812599233
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1705757511
Short name T101
Test name
Test status
Simulation time 522987132763 ps
CPU time 99.03 seconds
Started Jun 29 06:33:15 PM PDT 24
Finished Jun 29 06:34:55 PM PDT 24
Peak memory 214472 kb
Host smart-e869d776-6e30-46f1-9e24-fbbcf19828ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705757511 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.1705757511
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.1542088411
Short name T83
Test name
Test status
Simulation time 4127135745 ps
CPU time 3.18 seconds
Started Jun 29 06:31:37 PM PDT 24
Finished Jun 29 06:31:40 PM PDT 24
Peak memory 201520 kb
Host smart-6dcd212e-102e-4a32-8c16-e0985b23a0d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542088411 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.1542088411
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3488234739
Short name T125
Test name
Test status
Simulation time 1787159495152 ps
CPU time 28.72 seconds
Started Jun 29 06:33:13 PM PDT 24
Finished Jun 29 06:33:42 PM PDT 24
Peak memory 201576 kb
Host smart-12ca7e27-2504-4e91-bcc2-3a9410ca7a7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488234739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ultra_low_pwr.3488234739
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.223709167
Short name T318
Test name
Test status
Simulation time 2060634099 ps
CPU time 6.82 seconds
Started Jun 29 06:27:17 PM PDT 24
Finished Jun 29 06:27:25 PM PDT 24
Peak memory 202132 kb
Host smart-add24fce-1862-4ff3-b8f7-f0143a0088f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223709167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors
.223709167
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.28476217
Short name T84
Test name
Test status
Simulation time 4281981937 ps
CPU time 10.95 seconds
Started Jun 29 06:32:24 PM PDT 24
Finished Jun 29 06:32:35 PM PDT 24
Peak memory 201520 kb
Host smart-d7a63586-e326-4411-a3d5-cb44df4c1c68
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28476217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl
_edge_detect.28476217
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.4244389905
Short name T180
Test name
Test status
Simulation time 3098295321 ps
CPU time 7.5 seconds
Started Jun 29 06:32:27 PM PDT 24
Finished Jun 29 06:32:36 PM PDT 24
Peak memory 201460 kb
Host smart-f7ee38f2-5cc3-495a-8d0c-0e3254b16f4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244389905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_edge_detect.4244389905
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.248203875
Short name T377
Test name
Test status
Simulation time 85309482573 ps
CPU time 47.4 seconds
Started Jun 29 06:33:12 PM PDT 24
Finished Jun 29 06:34:00 PM PDT 24
Peak memory 201824 kb
Host smart-453817bd-4848-4732-a75f-85dc7ed6b32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248203875 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_wi
th_pre_cond.248203875
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.1593966684
Short name T9
Test name
Test status
Simulation time 165337783493 ps
CPU time 89.13 seconds
Started Jun 29 06:32:36 PM PDT 24
Finished Jun 29 06:34:06 PM PDT 24
Peak memory 201780 kb
Host smart-e1f81c20-9d56-4cb4-9d3c-d215f371e7f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593966684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_combo_detect.1593966684
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1000022405
Short name T382
Test name
Test status
Simulation time 113461476248 ps
CPU time 73.93 seconds
Started Jun 29 06:32:15 PM PDT 24
Finished Jun 29 06:33:30 PM PDT 24
Peak memory 201792 kb
Host smart-58a5f711-af97-4e58-aeb7-c680659516d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000022405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w
ith_pre_cond.1000022405
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.2508717554
Short name T194
Test name
Test status
Simulation time 142417947665 ps
CPU time 189.1 seconds
Started Jun 29 06:31:27 PM PDT 24
Finished Jun 29 06:34:37 PM PDT 24
Peak memory 218380 kb
Host smart-d67b0bf7-6f30-4f09-8688-094f53f5a56c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508717554 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.2508717554
Directory /workspace/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.793916025
Short name T391
Test name
Test status
Simulation time 116220184528 ps
CPU time 130.57 seconds
Started Jun 29 06:32:58 PM PDT 24
Finished Jun 29 06:35:10 PM PDT 24
Peak memory 201764 kb
Host smart-32509a65-34ba-42df-8a9a-51084f1154a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793916025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_wi
th_pre_cond.793916025
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.75043173
Short name T360
Test name
Test status
Simulation time 23607224456 ps
CPU time 20.35 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:27:35 PM PDT 24
Peak memory 202232 kb
Host smart-580d4db7-cdf8-41af-8cc4-de0f42c670f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75043173 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_c
sr_bit_bash.75043173
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.1437075816
Short name T424
Test name
Test status
Simulation time 2019749126 ps
CPU time 3.05 seconds
Started Jun 29 06:32:05 PM PDT 24
Finished Jun 29 06:32:09 PM PDT 24
Peak memory 201512 kb
Host smart-8d28843f-a1dd-4b61-8799-435790026158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437075816 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.1437075816
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.1465287270
Short name T146
Test name
Test status
Simulation time 8859527977 ps
CPU time 5.12 seconds
Started Jun 29 06:31:49 PM PDT 24
Finished Jun 29 06:31:56 PM PDT 24
Peak memory 201552 kb
Host smart-053c286a-6bbe-4cd1-bb28-aa48b07a0537
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465287270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ultra_low_pwr.1465287270
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.676276818
Short name T649
Test name
Test status
Simulation time 234347567081 ps
CPU time 135.98 seconds
Started Jun 29 06:32:01 PM PDT 24
Finished Jun 29 06:34:18 PM PDT 24
Peak memory 201832 kb
Host smart-d2b728af-e967-4b01-9f55-6fd1b443f16f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676276818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_st
ress_all.676276818
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.624697379
Short name T841
Test name
Test status
Simulation time 2066969616 ps
CPU time 4.49 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:27:19 PM PDT 24
Peak memory 202140 kb
Host smart-2c895dd0-65ed-4bf8-b3ec-553a72e3048c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624697379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_error
s.624697379
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.768389309
Short name T80
Test name
Test status
Simulation time 56033762595 ps
CPU time 79.49 seconds
Started Jun 29 06:33:19 PM PDT 24
Finished Jun 29 06:34:39 PM PDT 24
Peak memory 201840 kb
Host smart-c6764eca-732e-47fe-84e8-57cf7f2350cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768389309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_wi
th_pre_cond.768389309
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.3463134343
Short name T413
Test name
Test status
Simulation time 94247188039 ps
CPU time 13.75 seconds
Started Jun 29 06:31:48 PM PDT 24
Finished Jun 29 06:32:03 PM PDT 24
Peak memory 218368 kb
Host smart-0ba0a575-16fa-4df1-8eae-955d6a459d78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463134343 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.3463134343
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1029814759
Short name T389
Test name
Test status
Simulation time 96905849613 ps
CPU time 122.33 seconds
Started Jun 29 06:31:35 PM PDT 24
Finished Jun 29 06:33:38 PM PDT 24
Peak memory 201820 kb
Host smart-0e5ee46b-040a-496a-9556-79ce38cc2214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029814759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wi
th_pre_cond.1029814759
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.2004709837
Short name T100
Test name
Test status
Simulation time 121856734776 ps
CPU time 81.36 seconds
Started Jun 29 06:32:13 PM PDT 24
Finished Jun 29 06:33:35 PM PDT 24
Peak memory 201764 kb
Host smart-aff07d74-0980-4fc9-84f0-0c931ddc8623
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004709837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_combo_detect.2004709837
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.4175594055
Short name T390
Test name
Test status
Simulation time 75520776591 ps
CPU time 101.91 seconds
Started Jun 29 06:32:26 PM PDT 24
Finished Jun 29 06:34:09 PM PDT 24
Peak memory 201848 kb
Host smart-003d1b67-8955-4d12-a7e1-70674572c109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175594055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_w
ith_pre_cond.4175594055
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.3156881702
Short name T169
Test name
Test status
Simulation time 13890107448 ps
CPU time 27.76 seconds
Started Jun 29 06:32:26 PM PDT 24
Finished Jun 29 06:32:55 PM PDT 24
Peak memory 201532 kb
Host smart-73c8b141-c057-422a-8283-089541b43432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156881702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.3156881702
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.39864191
Short name T392
Test name
Test status
Simulation time 107115561688 ps
CPU time 72.91 seconds
Started Jun 29 06:32:09 PM PDT 24
Finished Jun 29 06:33:23 PM PDT 24
Peak memory 201820 kb
Host smart-086095a2-33df-42e7-910b-f6ed4b35493f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39864191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctr
l_combo_detect.39864191
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.2049772347
Short name T387
Test name
Test status
Simulation time 433723156175 ps
CPU time 259.42 seconds
Started Jun 29 06:32:59 PM PDT 24
Finished Jun 29 06:37:19 PM PDT 24
Peak memory 201736 kb
Host smart-3d4ce510-a638-4573-ac77-f3dcb2972dd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049772347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_s
tress_all.2049772347
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1203704665
Short name T294
Test name
Test status
Simulation time 192622923971 ps
CPU time 118.82 seconds
Started Jun 29 06:31:44 PM PDT 24
Finished Jun 29 06:33:43 PM PDT 24
Peak memory 201804 kb
Host smart-67777d8a-0504-4d39-8f48-1b48487748c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203704665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wi
th_pre_cond.1203704665
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.4222560094
Short name T228
Test name
Test status
Simulation time 28199512642 ps
CPU time 66.17 seconds
Started Jun 29 06:32:51 PM PDT 24
Finished Jun 29 06:33:58 PM PDT 24
Peak memory 210268 kb
Host smart-f5a99226-84f3-41b1-a7a2-df54ebea12e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222560094 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.4222560094
Directory /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.573294917
Short name T299
Test name
Test status
Simulation time 139132962146 ps
CPU time 80.07 seconds
Started Jun 29 06:32:26 PM PDT 24
Finished Jun 29 06:33:47 PM PDT 24
Peak memory 201740 kb
Host smart-3c9f9e1f-21b6-4eeb-83cf-eb2d6234a446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573294917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_st
ress_all.573294917
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1013670465
Short name T398
Test name
Test status
Simulation time 186119320414 ps
CPU time 24.71 seconds
Started Jun 29 06:33:05 PM PDT 24
Finished Jun 29 06:33:30 PM PDT 24
Peak memory 201804 kb
Host smart-ab55ff67-2bd2-4e50-81ff-84241349055b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013670465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_w
ith_pre_cond.1013670465
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.489241626
Short name T393
Test name
Test status
Simulation time 110301451177 ps
CPU time 32.72 seconds
Started Jun 29 06:33:31 PM PDT 24
Finished Jun 29 06:34:05 PM PDT 24
Peak memory 201844 kb
Host smart-92fe0fc2-bae0-40c6-9c55-8efb3a9a7f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489241626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_wi
th_pre_cond.489241626
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.3840325990
Short name T217
Test name
Test status
Simulation time 3117369218 ps
CPU time 1.25 seconds
Started Jun 29 06:31:25 PM PDT 24
Finished Jun 29 06:31:27 PM PDT 24
Peak memory 201544 kb
Host smart-d93f3496-305a-47b8-a3b0-9af518ab9097
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840325990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_edge_detect.3840325990
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1877200807
Short name T329
Test name
Test status
Simulation time 2545578470 ps
CPU time 3.56 seconds
Started Jun 29 06:27:08 PM PDT 24
Finished Jun 29 06:27:12 PM PDT 24
Peak memory 202264 kb
Host smart-c7503471-347d-413a-8872-99725690a146
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877200807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.1877200807
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.729471173
Short name T48
Test name
Test status
Simulation time 2342113362 ps
CPU time 7.69 seconds
Started Jun 29 06:27:16 PM PDT 24
Finished Jun 29 06:27:25 PM PDT 24
Peak memory 202232 kb
Host smart-52d11bb3-bf69-47c5-97dc-d3b1aa2723c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729471173 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_
csr_aliasing.729471173
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.3527370825
Short name T11
Test name
Test status
Simulation time 72218838580 ps
CPU time 51.1 seconds
Started Jun 29 06:32:28 PM PDT 24
Finished Jun 29 06:33:20 PM PDT 24
Peak memory 201860 kb
Host smart-20e9f299-d1da-4272-bf52-cbf86dbbdc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527370825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_w
ith_pre_cond.3527370825
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.2954688769
Short name T167
Test name
Test status
Simulation time 4301191265 ps
CPU time 6.43 seconds
Started Jun 29 06:32:31 PM PDT 24
Finished Jun 29 06:32:38 PM PDT 24
Peak memory 201552 kb
Host smart-f4cf176a-efe1-42dc-beed-a9f45ad72af3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954688769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.2954688769
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.905154850
Short name T869
Test name
Test status
Simulation time 22510899099 ps
CPU time 12.59 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:27:27 PM PDT 24
Peak memory 202328 kb
Host smart-8954e85d-381a-4fc9-828b-bfe92c0f7ede
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905154850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_tl_intg_err.905154850
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.1215664394
Short name T96
Test name
Test status
Simulation time 114425277307 ps
CPU time 108.06 seconds
Started Jun 29 06:32:05 PM PDT 24
Finished Jun 29 06:33:54 PM PDT 24
Peak memory 201832 kb
Host smart-7d24f5ac-9ac3-4707-b0f1-255f5a416b25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215664394 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.1215664394
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2678715982
Short name T34
Test name
Test status
Simulation time 91449592021 ps
CPU time 43.17 seconds
Started Jun 29 06:31:32 PM PDT 24
Finished Jun 29 06:32:15 PM PDT 24
Peak memory 211908 kb
Host smart-ee1a3b66-2f36-4728-93f2-924c967abec6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678715982 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.2678715982
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.1095012272
Short name T259
Test name
Test status
Simulation time 53406298227 ps
CPU time 138.72 seconds
Started Jun 29 06:32:26 PM PDT 24
Finished Jun 29 06:34:46 PM PDT 24
Peak memory 210252 kb
Host smart-8b0a5696-8084-4331-8994-b18de60f46e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095012272 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.1095012272
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3501147423
Short name T400
Test name
Test status
Simulation time 143743388251 ps
CPU time 248.09 seconds
Started Jun 29 06:32:38 PM PDT 24
Finished Jun 29 06:36:46 PM PDT 24
Peak memory 201852 kb
Host smart-5ec5e867-3981-4a17-b4a9-3ac1a73f1725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501147423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_w
ith_pre_cond.3501147423
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.899010687
Short name T410
Test name
Test status
Simulation time 63341333864 ps
CPU time 172.39 seconds
Started Jun 29 06:32:54 PM PDT 24
Finished Jun 29 06:35:47 PM PDT 24
Peak memory 201868 kb
Host smart-fd675abe-84c8-4854-acbf-60174b4385ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899010687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_wi
th_pre_cond.899010687
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.620782546
Short name T404
Test name
Test status
Simulation time 55402496240 ps
CPU time 27.06 seconds
Started Jun 29 06:31:33 PM PDT 24
Finished Jun 29 06:32:01 PM PDT 24
Peak memory 201804 kb
Host smart-49867370-b642-4d7e-ac14-5e16c47ad3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620782546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wit
h_pre_cond.620782546
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.1034300004
Short name T213
Test name
Test status
Simulation time 64077955955 ps
CPU time 156.77 seconds
Started Jun 29 06:33:21 PM PDT 24
Finished Jun 29 06:35:58 PM PDT 24
Peak memory 201740 kb
Host smart-fe19fbe7-76f6-4519-88dd-f4617caa845f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034300004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_w
ith_pre_cond.1034300004
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.866582898
Short name T401
Test name
Test status
Simulation time 57533759866 ps
CPU time 37.22 seconds
Started Jun 29 06:33:18 PM PDT 24
Finished Jun 29 06:33:56 PM PDT 24
Peak memory 201780 kb
Host smart-5cca9502-1132-4584-930e-010980b4d876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866582898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_wi
th_pre_cond.866582898
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.3149241424
Short name T295
Test name
Test status
Simulation time 121095045075 ps
CPU time 34.14 seconds
Started Jun 29 06:33:17 PM PDT 24
Finished Jun 29 06:33:52 PM PDT 24
Peak memory 201784 kb
Host smart-218464cf-39d1-42b9-8494-2e12ad8bc051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149241424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w
ith_pre_cond.3149241424
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.2816361874
Short name T396
Test name
Test status
Simulation time 87574941741 ps
CPU time 57.15 seconds
Started Jun 29 06:31:47 PM PDT 24
Finished Jun 29 06:32:45 PM PDT 24
Peak memory 201784 kb
Host smart-fc7d444f-e53e-45b6-b3c0-937aafac9a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816361874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wi
th_pre_cond.2816361874
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3173140546
Short name T288
Test name
Test status
Simulation time 41695494661 ps
CPU time 59.9 seconds
Started Jun 29 06:31:25 PM PDT 24
Finished Jun 29 06:32:25 PM PDT 24
Peak memory 201868 kb
Host smart-c27bc4c0-da43-44cf-a594-3acf6b0bb135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173140546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi
th_pre_cond.3173140546
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1035449418
Short name T373
Test name
Test status
Simulation time 3341389446 ps
CPU time 11.47 seconds
Started Jun 29 06:27:10 PM PDT 24
Finished Jun 29 06:27:22 PM PDT 24
Peak memory 202184 kb
Host smart-9ed51214-2fc4-4925-ba80-89f5c64fcc9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035449418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_aliasing.1035449418
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2309676874
Short name T369
Test name
Test status
Simulation time 48759973534 ps
CPU time 229.17 seconds
Started Jun 29 06:27:09 PM PDT 24
Finished Jun 29 06:30:59 PM PDT 24
Peak memory 202272 kb
Host smart-81a92730-6ecb-4296-87b7-8042c6c78326
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309676874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_bit_bash.2309676874
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.301710168
Short name T868
Test name
Test status
Simulation time 4059913927 ps
CPU time 3.35 seconds
Started Jun 29 06:27:08 PM PDT 24
Finished Jun 29 06:27:12 PM PDT 24
Peak memory 202000 kb
Host smart-2619e1af-8a58-4806-a028-8bc1daccc63e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301710168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_
csr_hw_reset.301710168
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.33366875
Short name T325
Test name
Test status
Simulation time 2207796367 ps
CPU time 2.46 seconds
Started Jun 29 06:27:13 PM PDT 24
Finished Jun 29 06:27:16 PM PDT 24
Peak memory 202152 kb
Host smart-ff06409e-ee49-4f80-86dd-7b70df13c5f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33366875 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.33366875
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.825944983
Short name T363
Test name
Test status
Simulation time 2043161754 ps
CPU time 2.01 seconds
Started Jun 29 06:27:09 PM PDT 24
Finished Jun 29 06:27:11 PM PDT 24
Peak memory 201884 kb
Host smart-a2ea805f-76af-4e65-8561-9007557f48fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825944983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_rw
.825944983
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2577736064
Short name T837
Test name
Test status
Simulation time 2031812756 ps
CPU time 1.84 seconds
Started Jun 29 06:27:08 PM PDT 24
Finished Jun 29 06:27:10 PM PDT 24
Peak memory 201740 kb
Host smart-df15f6ae-98b2-4377-986b-a4dc5e27ac1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577736064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_tes
t.2577736064
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3301906989
Short name T326
Test name
Test status
Simulation time 8128176324 ps
CPU time 3.77 seconds
Started Jun 29 06:27:08 PM PDT 24
Finished Jun 29 06:27:12 PM PDT 24
Peak memory 202296 kb
Host smart-4fb4dccc-ec69-473e-adb6-48992276193c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301906989 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_same_csr_outstanding.3301906989
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1670832178
Short name T866
Test name
Test status
Simulation time 3045534146 ps
CPU time 5.88 seconds
Started Jun 29 06:27:15 PM PDT 24
Finished Jun 29 06:27:22 PM PDT 24
Peak memory 202232 kb
Host smart-6f73f92f-bb03-45b1-b4ba-6f16ee8f6721
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670832178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.1670832178
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.4195729156
Short name T361
Test name
Test status
Simulation time 49162146877 ps
CPU time 114.58 seconds
Started Jun 29 06:27:16 PM PDT 24
Finished Jun 29 06:29:12 PM PDT 24
Peak memory 202216 kb
Host smart-e6bd6992-3d9e-4898-90e7-1771b6593fb4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195729156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_bit_bash.4195729156
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2056984431
Short name T904
Test name
Test status
Simulation time 6018860916 ps
CPU time 7.8 seconds
Started Jun 29 06:27:12 PM PDT 24
Finished Jun 29 06:27:21 PM PDT 24
Peak memory 202008 kb
Host smart-53b7fa6f-0467-4889-8f48-2162ba95326e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056984431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.2056984431
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2465165684
Short name T798
Test name
Test status
Simulation time 2085676317 ps
CPU time 6.33 seconds
Started Jun 29 06:27:16 PM PDT 24
Finished Jun 29 06:27:23 PM PDT 24
Peak memory 201996 kb
Host smart-04d3902e-25fe-40eb-a5b5-3a98eec118fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465165684 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2465165684
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1363168987
Short name T24
Test name
Test status
Simulation time 2050809422 ps
CPU time 6.31 seconds
Started Jun 29 06:27:13 PM PDT 24
Finished Jun 29 06:27:21 PM PDT 24
Peak memory 201980 kb
Host smart-ac0115e2-fcd3-48dc-b077-9b927fd2d033
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363168987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.1363168987
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1246685133
Short name T830
Test name
Test status
Simulation time 2015683465 ps
CPU time 5.9 seconds
Started Jun 29 06:27:15 PM PDT 24
Finished Jun 29 06:27:22 PM PDT 24
Peak memory 201764 kb
Host smart-70e5ff45-36aa-4b96-a2fa-91782141d46d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246685133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_tes
t.1246685133
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2828670413
Short name T843
Test name
Test status
Simulation time 4360726267 ps
CPU time 11.36 seconds
Started Jun 29 06:27:11 PM PDT 24
Finished Jun 29 06:27:23 PM PDT 24
Peak memory 202224 kb
Host smart-5ae9cb0b-401f-4d47-996f-941ddf6ad5b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828670413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.2828670413
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.993881352
Short name T862
Test name
Test status
Simulation time 2423747390 ps
CPU time 3.76 seconds
Started Jun 29 06:27:16 PM PDT 24
Finished Jun 29 06:27:21 PM PDT 24
Peak memory 202260 kb
Host smart-f13fcddc-bf16-4891-90a6-aafd477eac14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993881352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_errors
.993881352
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.676912309
Short name T838
Test name
Test status
Simulation time 2217456751 ps
CPU time 2.73 seconds
Started Jun 29 06:27:15 PM PDT 24
Finished Jun 29 06:27:19 PM PDT 24
Peak memory 202144 kb
Host smart-bbc98027-cb65-44b2-9d03-085dcc4ee46f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676912309 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.676912309
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2271856572
Short name T877
Test name
Test status
Simulation time 2019612801 ps
CPU time 5.94 seconds
Started Jun 29 06:27:20 PM PDT 24
Finished Jun 29 06:27:27 PM PDT 24
Peak memory 201796 kb
Host smart-4682447f-160f-4b20-a999-15de9036179d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271856572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.2271856572
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1511064743
Short name T786
Test name
Test status
Simulation time 2013079029 ps
CPU time 5.97 seconds
Started Jun 29 06:27:15 PM PDT 24
Finished Jun 29 06:27:23 PM PDT 24
Peak memory 201740 kb
Host smart-ffc8c290-4ef0-473a-a28e-603669aefd88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511064743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.1511064743
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2486112854
Short name T898
Test name
Test status
Simulation time 9292303657 ps
CPU time 18.11 seconds
Started Jun 29 06:27:20 PM PDT 24
Finished Jun 29 06:27:39 PM PDT 24
Peak memory 202116 kb
Host smart-d143fce6-9f44-4e6d-a644-5febb9c8228a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486112854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.sysrst_ctrl_same_csr_outstanding.2486112854
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.4270058009
Short name T887
Test name
Test status
Simulation time 2171665474 ps
CPU time 4.67 seconds
Started Jun 29 06:27:17 PM PDT 24
Finished Jun 29 06:27:22 PM PDT 24
Peak memory 202288 kb
Host smart-fd2019e6-396b-4f25-b9a0-168a5d8de274
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270058009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_erro
rs.4270058009
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3895088847
Short name T886
Test name
Test status
Simulation time 42917567916 ps
CPU time 32.89 seconds
Started Jun 29 06:27:15 PM PDT 24
Finished Jun 29 06:27:50 PM PDT 24
Peak memory 202272 kb
Host smart-d048852b-5a9c-46de-9236-0f63e9c9e4f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895088847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.3895088847
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.177767563
Short name T324
Test name
Test status
Simulation time 2103545021 ps
CPU time 2.15 seconds
Started Jun 29 06:27:24 PM PDT 24
Finished Jun 29 06:27:27 PM PDT 24
Peak memory 201936 kb
Host smart-ae16d2af-368e-424c-8e85-e9bc3fad9a6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177767563 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.177767563
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3964162980
Short name T856
Test name
Test status
Simulation time 2017821820 ps
CPU time 5.91 seconds
Started Jun 29 06:27:24 PM PDT 24
Finished Jun 29 06:27:31 PM PDT 24
Peak memory 201888 kb
Host smart-b2c9507b-a00a-4f31-91ae-8595d4cf3a2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964162980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_
rw.3964162980
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.874913654
Short name T865
Test name
Test status
Simulation time 2029113183 ps
CPU time 1.71 seconds
Started Jun 29 06:27:21 PM PDT 24
Finished Jun 29 06:27:23 PM PDT 24
Peak memory 201688 kb
Host smart-5d03ebaf-b7c4-48c6-8066-6f262685f472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874913654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_tes
t.874913654
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.4260947604
Short name T22
Test name
Test status
Simulation time 9727865937 ps
CPU time 25.12 seconds
Started Jun 29 06:27:20 PM PDT 24
Finished Jun 29 06:27:45 PM PDT 24
Peak memory 202240 kb
Host smart-e531a3c4-388a-42b7-bf88-c31c4370dc13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260947604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.sysrst_ctrl_same_csr_outstanding.4260947604
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3018334376
Short name T903
Test name
Test status
Simulation time 22206252759 ps
CPU time 58.99 seconds
Started Jun 29 06:27:15 PM PDT 24
Finished Jun 29 06:28:15 PM PDT 24
Peak memory 202280 kb
Host smart-d8dfebff-a5ac-4ec7-bc92-ce253b0a6a6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018334376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.3018334376
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.908843676
Short name T355
Test name
Test status
Simulation time 2093209875 ps
CPU time 3.54 seconds
Started Jun 29 06:27:23 PM PDT 24
Finished Jun 29 06:27:28 PM PDT 24
Peak memory 201940 kb
Host smart-f8073a0d-b367-4ee3-bfd4-e3f4942f5819
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908843676 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.908843676
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1314425528
Short name T851
Test name
Test status
Simulation time 2065881559 ps
CPU time 4.95 seconds
Started Jun 29 06:27:22 PM PDT 24
Finished Jun 29 06:27:28 PM PDT 24
Peak memory 201996 kb
Host smart-3db6cb51-3213-41da-8323-64d74216a4eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314425528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_
rw.1314425528
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3640008302
Short name T791
Test name
Test status
Simulation time 2011133129 ps
CPU time 5.82 seconds
Started Jun 29 06:27:24 PM PDT 24
Finished Jun 29 06:27:31 PM PDT 24
Peak memory 201868 kb
Host smart-acd0e786-bccc-4c65-869e-9a6be2e8d6aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640008302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.3640008302
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.437583933
Short name T826
Test name
Test status
Simulation time 4491320741 ps
CPU time 3.76 seconds
Started Jun 29 06:27:21 PM PDT 24
Finished Jun 29 06:27:25 PM PDT 24
Peak memory 202100 kb
Host smart-ea789e6e-cd53-4445-863d-843cfc33be12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437583933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.sysrst_ctrl_same_csr_outstanding.437583933
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2730906572
Short name T831
Test name
Test status
Simulation time 2072456144 ps
CPU time 4.87 seconds
Started Jun 29 06:27:22 PM PDT 24
Finished Jun 29 06:27:28 PM PDT 24
Peak memory 210336 kb
Host smart-8c01dcbb-209c-4e17-a15c-8282242cf6c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730906572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_erro
rs.2730906572
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2089422106
Short name T829
Test name
Test status
Simulation time 42508072668 ps
CPU time 30.04 seconds
Started Jun 29 06:27:24 PM PDT 24
Finished Jun 29 06:27:55 PM PDT 24
Peak memory 202280 kb
Host smart-63c84792-96d6-475c-b4d4-d9a5871ed391
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089422106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_tl_intg_err.2089422106
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3798031801
Short name T806
Test name
Test status
Simulation time 2076646604 ps
CPU time 6.28 seconds
Started Jun 29 06:27:25 PM PDT 24
Finished Jun 29 06:27:32 PM PDT 24
Peak memory 202000 kb
Host smart-aae7c518-24d1-4bdf-bcce-913da97af20e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798031801 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3798031801
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3120004745
Short name T358
Test name
Test status
Simulation time 2052692017 ps
CPU time 6.18 seconds
Started Jun 29 06:27:22 PM PDT 24
Finished Jun 29 06:27:29 PM PDT 24
Peak memory 201984 kb
Host smart-e8bd5752-684f-422e-a1de-0a27a761f951
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120004745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_
rw.3120004745
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3115280814
Short name T823
Test name
Test status
Simulation time 2014419977 ps
CPU time 4.18 seconds
Started Jun 29 06:27:22 PM PDT 24
Finished Jun 29 06:27:27 PM PDT 24
Peak memory 201696 kb
Host smart-4b0720f2-d9b4-4649-a777-475cedab0977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115280814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_te
st.3115280814
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.4064028179
Short name T890
Test name
Test status
Simulation time 4447936948 ps
CPU time 3.63 seconds
Started Jun 29 06:27:21 PM PDT 24
Finished Jun 29 06:27:25 PM PDT 24
Peak memory 202008 kb
Host smart-b59961d1-1189-40a6-9b41-b2bbacce920b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064028179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.4064028179
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.712073243
Short name T849
Test name
Test status
Simulation time 2563301104 ps
CPU time 3.04 seconds
Started Jun 29 06:27:23 PM PDT 24
Finished Jun 29 06:27:28 PM PDT 24
Peak memory 202264 kb
Host smart-080c2480-659a-411b-8b56-443490837e2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712073243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_error
s.712073243
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2632918542
Short name T331
Test name
Test status
Simulation time 42844098227 ps
CPU time 28.81 seconds
Started Jun 29 06:27:24 PM PDT 24
Finished Jun 29 06:27:54 PM PDT 24
Peak memory 202224 kb
Host smart-bdd9f76b-9d34-47a4-80d9-d27a6ce311da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632918542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_tl_intg_err.2632918542
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1648950163
Short name T832
Test name
Test status
Simulation time 2126152953 ps
CPU time 2.05 seconds
Started Jun 29 06:27:24 PM PDT 24
Finished Jun 29 06:27:27 PM PDT 24
Peak memory 201784 kb
Host smart-68b4ea9d-ef05-4f3b-bcfd-efddd3ffae3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648950163 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1648950163
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2827402806
Short name T371
Test name
Test status
Simulation time 2033718589 ps
CPU time 5.63 seconds
Started Jun 29 06:27:20 PM PDT 24
Finished Jun 29 06:27:26 PM PDT 24
Peak memory 201976 kb
Host smart-fa8e5d93-0945-4ee9-97c7-ad2c8a9a6aeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827402806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_
rw.2827402806
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1920999662
Short name T847
Test name
Test status
Simulation time 2015602517 ps
CPU time 3.74 seconds
Started Jun 29 06:27:23 PM PDT 24
Finished Jun 29 06:27:27 PM PDT 24
Peak memory 201768 kb
Host smart-29e79dc4-dbd6-4606-be80-9beae4e4b9ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920999662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.1920999662
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1008587366
Short name T370
Test name
Test status
Simulation time 4724746493 ps
CPU time 6.57 seconds
Started Jun 29 06:27:23 PM PDT 24
Finished Jun 29 06:27:30 PM PDT 24
Peak memory 202192 kb
Host smart-d5e957c8-da67-40dd-b5a5-22d43fde91c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008587366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_same_csr_outstanding.1008587366
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1445415147
Short name T317
Test name
Test status
Simulation time 2063360927 ps
CPU time 6.38 seconds
Started Jun 29 06:27:20 PM PDT 24
Finished Jun 29 06:27:27 PM PDT 24
Peak memory 202128 kb
Host smart-02369f10-4854-44bb-bb2c-2160c8e9dd9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445415147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.1445415147
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.3789076445
Short name T846
Test name
Test status
Simulation time 22233517251 ps
CPU time 54.19 seconds
Started Jun 29 06:27:24 PM PDT 24
Finished Jun 29 06:28:19 PM PDT 24
Peak memory 202340 kb
Host smart-9e8fb310-5db5-48c0-8b5f-fa9a0663f3ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789076445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_tl_intg_err.3789076445
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.71876682
Short name T807
Test name
Test status
Simulation time 2132499388 ps
CPU time 2.12 seconds
Started Jun 29 06:27:21 PM PDT 24
Finished Jun 29 06:27:24 PM PDT 24
Peak memory 201968 kb
Host smart-c2a9270a-6de6-4641-bd7c-315e633d8056
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71876682 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.71876682
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1073497639
Short name T885
Test name
Test status
Simulation time 2061740666 ps
CPU time 4.26 seconds
Started Jun 29 06:27:20 PM PDT 24
Finished Jun 29 06:27:25 PM PDT 24
Peak memory 201976 kb
Host smart-b4d393b8-6374-4f60-9e12-bb65c978bd26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073497639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_
rw.1073497639
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2073825937
Short name T874
Test name
Test status
Simulation time 2012645437 ps
CPU time 5.59 seconds
Started Jun 29 06:27:22 PM PDT 24
Finished Jun 29 06:27:29 PM PDT 24
Peak memory 201872 kb
Host smart-7b578776-9deb-4743-ae4a-e062b34e712e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073825937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_te
st.2073825937
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2951866366
Short name T867
Test name
Test status
Simulation time 10273356201 ps
CPU time 8.44 seconds
Started Jun 29 06:27:24 PM PDT 24
Finished Jun 29 06:27:34 PM PDT 24
Peak memory 202112 kb
Host smart-d0032da4-c518-41e1-aac4-b737fe996e52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951866366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.2951866366
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1536468305
Short name T891
Test name
Test status
Simulation time 2349829736 ps
CPU time 3.34 seconds
Started Jun 29 06:27:21 PM PDT 24
Finished Jun 29 06:27:25 PM PDT 24
Peak memory 202208 kb
Host smart-5bd0bc3c-c346-4bc1-b389-2a67c024d538
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536468305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.1536468305
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.141749566
Short name T835
Test name
Test status
Simulation time 42909901696 ps
CPU time 12.58 seconds
Started Jun 29 06:27:24 PM PDT 24
Finished Jun 29 06:27:38 PM PDT 24
Peak memory 202324 kb
Host smart-4cfb5d01-be11-4b9d-9e37-a6b52395e3df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141749566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_tl_intg_err.141749566
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2507853430
Short name T901
Test name
Test status
Simulation time 2085263514 ps
CPU time 6.11 seconds
Started Jun 29 06:27:21 PM PDT 24
Finished Jun 29 06:27:28 PM PDT 24
Peak memory 201948 kb
Host smart-1e8d9668-82d5-4ca8-bd59-c7315563edb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507853430 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2507853430
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3417422486
Short name T792
Test name
Test status
Simulation time 2041182304 ps
CPU time 3.25 seconds
Started Jun 29 06:27:28 PM PDT 24
Finished Jun 29 06:27:32 PM PDT 24
Peak memory 201884 kb
Host smart-003919e4-20c4-4a0c-be5b-6e9f5a1fdd64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417422486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.3417422486
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2777603860
Short name T790
Test name
Test status
Simulation time 2044439150 ps
CPU time 1.46 seconds
Started Jun 29 06:27:20 PM PDT 24
Finished Jun 29 06:27:22 PM PDT 24
Peak memory 201744 kb
Host smart-9a9f2267-53a5-40e3-9d04-d393b87177d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777603860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.2777603860
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2140908546
Short name T23
Test name
Test status
Simulation time 4852856711 ps
CPU time 3.89 seconds
Started Jun 29 06:27:21 PM PDT 24
Finished Jun 29 06:27:25 PM PDT 24
Peak memory 201944 kb
Host smart-a6d199b0-a821-49f8-ad2a-8e802d1e476e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140908546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_same_csr_outstanding.2140908546
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1112234952
Short name T333
Test name
Test status
Simulation time 2105431390 ps
CPU time 3.1 seconds
Started Jun 29 06:27:23 PM PDT 24
Finished Jun 29 06:27:26 PM PDT 24
Peak memory 202120 kb
Host smart-7a10e557-c13c-4ba5-acb2-ffe60eef996e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112234952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.1112234952
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.919212118
Short name T905
Test name
Test status
Simulation time 22473294245 ps
CPU time 15.5 seconds
Started Jun 29 06:27:22 PM PDT 24
Finished Jun 29 06:27:38 PM PDT 24
Peak memory 202276 kb
Host smart-944d3c10-dbe8-4e28-a6a7-c2531f27146f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919212118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_tl_intg_err.919212118
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1300640039
Short name T323
Test name
Test status
Simulation time 2159410062 ps
CPU time 3.68 seconds
Started Jun 29 06:27:22 PM PDT 24
Finished Jun 29 06:27:26 PM PDT 24
Peak memory 202152 kb
Host smart-a2a9bef5-23fe-4e48-b26b-bd9866d15973
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300640039 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1300640039
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.311862262
Short name T859
Test name
Test status
Simulation time 2094593475 ps
CPU time 1.84 seconds
Started Jun 29 06:27:24 PM PDT 24
Finished Jun 29 06:27:27 PM PDT 24
Peak memory 201976 kb
Host smart-d73aef49-6de5-4017-948b-eb85d3dbd1f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311862262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_r
w.311862262
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3939023622
Short name T836
Test name
Test status
Simulation time 2033702930 ps
CPU time 1.73 seconds
Started Jun 29 06:27:21 PM PDT 24
Finished Jun 29 06:27:23 PM PDT 24
Peak memory 201780 kb
Host smart-99a1f863-b542-45a8-9862-ce8383cffbbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939023622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_te
st.3939023622
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1164681067
Short name T818
Test name
Test status
Simulation time 10252923743 ps
CPU time 25.06 seconds
Started Jun 29 06:27:24 PM PDT 24
Finished Jun 29 06:27:50 PM PDT 24
Peak memory 202268 kb
Host smart-8231ac66-c0c1-4c93-8b83-2c676989792b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164681067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
7.sysrst_ctrl_same_csr_outstanding.1164681067
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1110491742
Short name T319
Test name
Test status
Simulation time 2089412609 ps
CPU time 2.93 seconds
Started Jun 29 06:27:22 PM PDT 24
Finished Jun 29 06:27:26 PM PDT 24
Peak memory 210364 kb
Host smart-e591513c-33d4-406a-a1db-394961225d0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110491742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_erro
rs.1110491742
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.711301076
Short name T876
Test name
Test status
Simulation time 42405719790 ps
CPU time 115.73 seconds
Started Jun 29 06:27:21 PM PDT 24
Finished Jun 29 06:29:18 PM PDT 24
Peak memory 202324 kb
Host smart-8b8f2bf6-4fd7-4e17-b500-a39c4c12f89a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711301076 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_tl_intg_err.711301076
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1273505609
Short name T880
Test name
Test status
Simulation time 2085810847 ps
CPU time 2.13 seconds
Started Jun 29 06:27:28 PM PDT 24
Finished Jun 29 06:27:31 PM PDT 24
Peak memory 202032 kb
Host smart-54efa2e8-aae6-4927-9146-2e366c1ca028
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273505609 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1273505609
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.377342000
Short name T365
Test name
Test status
Simulation time 2054639560 ps
CPU time 3.5 seconds
Started Jun 29 06:27:23 PM PDT 24
Finished Jun 29 06:27:28 PM PDT 24
Peak memory 201884 kb
Host smart-c250b8c5-2348-4c91-b9a1-2b5cece18508
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377342000 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_r
w.377342000
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1423413195
Short name T788
Test name
Test status
Simulation time 2017165874 ps
CPU time 3.08 seconds
Started Jun 29 06:27:23 PM PDT 24
Finished Jun 29 06:27:27 PM PDT 24
Peak memory 201708 kb
Host smart-3a0fce16-5f22-469d-b077-d14dc61503ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423413195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_te
st.1423413195
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.515370593
Short name T857
Test name
Test status
Simulation time 7676002321 ps
CPU time 6.11 seconds
Started Jun 29 06:27:24 PM PDT 24
Finished Jun 29 06:27:31 PM PDT 24
Peak memory 202296 kb
Host smart-46cfa93e-6ed6-4aa5-b1d0-1b41c695d977
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515370593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.sysrst_ctrl_same_csr_outstanding.515370593
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.210516318
Short name T328
Test name
Test status
Simulation time 2053513580 ps
CPU time 8.45 seconds
Started Jun 29 06:27:22 PM PDT 24
Finished Jun 29 06:27:31 PM PDT 24
Peak memory 210336 kb
Host smart-91b5087c-453d-44c1-8b57-2decd9d285e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210516318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_error
s.210516318
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.880825833
Short name T332
Test name
Test status
Simulation time 42528921067 ps
CPU time 26.92 seconds
Started Jun 29 06:27:23 PM PDT 24
Finished Jun 29 06:27:51 PM PDT 24
Peak memory 202256 kb
Host smart-0378d063-56b8-462f-8343-7d39da347cc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880825833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_tl_intg_err.880825833
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3732385234
Short name T893
Test name
Test status
Simulation time 2260612232 ps
CPU time 2.46 seconds
Started Jun 29 06:27:23 PM PDT 24
Finished Jun 29 06:27:27 PM PDT 24
Peak memory 202152 kb
Host smart-8d7d1da1-db2f-4d18-83ad-dd1ee420c879
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732385234 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3732385234
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1995293233
Short name T902
Test name
Test status
Simulation time 2219862641 ps
CPU time 1.47 seconds
Started Jun 29 06:27:23 PM PDT 24
Finished Jun 29 06:27:26 PM PDT 24
Peak memory 202096 kb
Host smart-a0cdb683-5dc7-4d18-8cdd-102970d8eb7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995293233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.1995293233
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2483079683
Short name T803
Test name
Test status
Simulation time 2037608268 ps
CPU time 1.87 seconds
Started Jun 29 06:27:22 PM PDT 24
Finished Jun 29 06:27:24 PM PDT 24
Peak memory 201868 kb
Host smart-5761bb07-205c-4d05-80be-d7bc596c0501
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483079683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.2483079683
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2822012538
Short name T327
Test name
Test status
Simulation time 9635828593 ps
CPU time 22.03 seconds
Started Jun 29 06:27:28 PM PDT 24
Finished Jun 29 06:27:51 PM PDT 24
Peak memory 202272 kb
Host smart-39205a06-8c6e-4574-a354-55fe8f3a5b0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822012538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.2822012538
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.4126829117
Short name T834
Test name
Test status
Simulation time 2070593282 ps
CPU time 6.62 seconds
Started Jun 29 06:27:29 PM PDT 24
Finished Jun 29 06:27:36 PM PDT 24
Peak memory 202152 kb
Host smart-c9277915-a216-4920-8da5-1f64b16c0920
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126829117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro
rs.4126829117
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2977849173
Short name T860
Test name
Test status
Simulation time 22277251996 ps
CPU time 16.88 seconds
Started Jun 29 06:27:23 PM PDT 24
Finished Jun 29 06:27:41 PM PDT 24
Peak memory 202324 kb
Host smart-08dcbcc6-81d4-46c9-b50f-b90278cbf044
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977849173 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_tl_intg_err.2977849173
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1347582779
Short name T367
Test name
Test status
Simulation time 44001860470 ps
CPU time 55.09 seconds
Started Jun 29 06:27:12 PM PDT 24
Finished Jun 29 06:28:07 PM PDT 24
Peak memory 202220 kb
Host smart-447330f7-fc87-4ad9-b771-fdeb3ba7ca93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347582779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_bit_bash.1347582779
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3485288215
Short name T814
Test name
Test status
Simulation time 4072023000 ps
CPU time 3.03 seconds
Started Jun 29 06:27:13 PM PDT 24
Finished Jun 29 06:27:17 PM PDT 24
Peak memory 201968 kb
Host smart-777d6f9c-8470-4f0a-b043-3fce7296bded
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485288215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.3485288215
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2929295542
Short name T816
Test name
Test status
Simulation time 2271334924 ps
CPU time 1.38 seconds
Started Jun 29 06:27:15 PM PDT 24
Finished Jun 29 06:27:18 PM PDT 24
Peak memory 202084 kb
Host smart-482e29c4-bb8a-4847-bdee-f3640f7aaf80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929295542 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2929295542
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2521845959
Short name T855
Test name
Test status
Simulation time 2050994273 ps
CPU time 6.2 seconds
Started Jun 29 06:27:17 PM PDT 24
Finished Jun 29 06:27:24 PM PDT 24
Peak memory 201972 kb
Host smart-1e07ab58-a7d5-406a-af6e-b3478dc40193
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521845959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.2521845959
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.21195921
Short name T805
Test name
Test status
Simulation time 2030072104 ps
CPU time 1.95 seconds
Started Jun 29 06:27:13 PM PDT 24
Finished Jun 29 06:27:15 PM PDT 24
Peak memory 201860 kb
Host smart-70f28585-9037-4334-8f8d-afaaafacdb16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21195921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test.21195921
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1240775785
Short name T840
Test name
Test status
Simulation time 5215140882 ps
CPU time 8.87 seconds
Started Jun 29 06:27:13 PM PDT 24
Finished Jun 29 06:27:22 PM PDT 24
Peak memory 202244 kb
Host smart-855202d4-d566-4b87-943c-0f4c17f5304f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240775785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.1240775785
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.3508387321
Short name T882
Test name
Test status
Simulation time 2058051176 ps
CPU time 6.56 seconds
Started Jun 29 06:27:16 PM PDT 24
Finished Jun 29 06:27:24 PM PDT 24
Peak memory 202132 kb
Host smart-7ae4fb7d-d042-4b52-851f-7c9391227e5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508387321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error
s.3508387321
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1660119070
Short name T334
Test name
Test status
Simulation time 22244187223 ps
CPU time 19.09 seconds
Started Jun 29 06:27:15 PM PDT 24
Finished Jun 29 06:27:35 PM PDT 24
Peak memory 202280 kb
Host smart-aec242be-348c-4200-b5dc-97edc7a2cf76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660119070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.1660119070
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1766596319
Short name T795
Test name
Test status
Simulation time 2012676324 ps
CPU time 5.98 seconds
Started Jun 29 06:27:29 PM PDT 24
Finished Jun 29 06:27:35 PM PDT 24
Peak memory 201864 kb
Host smart-eaaf0128-cec6-4238-877c-5d586885e89d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766596319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_te
st.1766596319
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.928838613
Short name T813
Test name
Test status
Simulation time 2011357689 ps
CPU time 5.72 seconds
Started Jun 29 06:27:24 PM PDT 24
Finished Jun 29 06:27:31 PM PDT 24
Peak memory 201744 kb
Host smart-f07c43d8-3b3c-46a1-991e-cd0d4bb09925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928838613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_tes
t.928838613
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.891271890
Short name T783
Test name
Test status
Simulation time 2140021084 ps
CPU time 1.1 seconds
Started Jun 29 06:27:30 PM PDT 24
Finished Jun 29 06:27:31 PM PDT 24
Peak memory 201664 kb
Host smart-15521b1f-baf5-4058-a0b4-e93f12ea633d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891271890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_tes
t.891271890
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.4176360522
Short name T889
Test name
Test status
Simulation time 2025547631 ps
CPU time 3.31 seconds
Started Jun 29 06:27:34 PM PDT 24
Finished Jun 29 06:27:38 PM PDT 24
Peak memory 201832 kb
Host smart-3b0995da-85c1-4ab4-91a9-d1f9944c9651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176360522 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.4176360522
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1041312364
Short name T796
Test name
Test status
Simulation time 2011806866 ps
CPU time 5.8 seconds
Started Jun 29 06:27:32 PM PDT 24
Finished Jun 29 06:27:38 PM PDT 24
Peak memory 201744 kb
Host smart-89a364b0-6cd9-4ea1-bba4-cc93586c2e0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041312364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_te
st.1041312364
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2464592690
Short name T906
Test name
Test status
Simulation time 2054663888 ps
CPU time 1.47 seconds
Started Jun 29 06:27:30 PM PDT 24
Finished Jun 29 06:27:32 PM PDT 24
Peak memory 201864 kb
Host smart-d9c76fff-4ffb-4539-8472-15e896567414
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464592690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te
st.2464592690
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3785340331
Short name T793
Test name
Test status
Simulation time 2012189525 ps
CPU time 6 seconds
Started Jun 29 06:27:28 PM PDT 24
Finished Jun 29 06:27:34 PM PDT 24
Peak memory 201744 kb
Host smart-728a9499-f548-44a6-8b5f-40c9a6214e08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785340331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_te
st.3785340331
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2038685856
Short name T789
Test name
Test status
Simulation time 2047079512 ps
CPU time 1.57 seconds
Started Jun 29 06:27:31 PM PDT 24
Finished Jun 29 06:27:33 PM PDT 24
Peak memory 201704 kb
Host smart-aad15416-c5dc-4f7f-8614-9525aab63b05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038685856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_te
st.2038685856
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.744619534
Short name T871
Test name
Test status
Simulation time 2062947050 ps
CPU time 1.24 seconds
Started Jun 29 06:27:28 PM PDT 24
Finished Jun 29 06:27:30 PM PDT 24
Peak memory 201744 kb
Host smart-848bb502-9e2e-466f-8598-2ffdefd54d3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744619534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_tes
t.744619534
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.2162278751
Short name T878
Test name
Test status
Simulation time 2015854617 ps
CPU time 5.4 seconds
Started Jun 29 06:27:29 PM PDT 24
Finished Jun 29 06:27:35 PM PDT 24
Peak memory 201700 kb
Host smart-78ae96ed-454a-42c1-b04e-abd4957516b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162278751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_te
st.2162278751
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.527426227
Short name T366
Test name
Test status
Simulation time 2891232156 ps
CPU time 10.78 seconds
Started Jun 29 06:27:13 PM PDT 24
Finished Jun 29 06:27:25 PM PDT 24
Peak memory 202292 kb
Host smart-1655c140-e287-46a1-9117-313162700a26
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527426227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_
csr_aliasing.527426227
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.2369382601
Short name T819
Test name
Test status
Simulation time 6018430145 ps
CPU time 8.6 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:27:24 PM PDT 24
Peak memory 202092 kb
Host smart-50157227-d738-4f72-8a4f-062d56874886
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369382601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.2369382601
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2653606723
Short name T808
Test name
Test status
Simulation time 2077469217 ps
CPU time 3.62 seconds
Started Jun 29 06:27:13 PM PDT 24
Finished Jun 29 06:27:18 PM PDT 24
Peak memory 201940 kb
Host smart-5c92c81e-fee8-4c97-92ba-b3c2cbe036e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653606723 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2653606723
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.352046100
Short name T362
Test name
Test status
Simulation time 2122829923 ps
CPU time 1.55 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:27:16 PM PDT 24
Peak memory 201980 kb
Host smart-f658f54d-a54d-4056-8e1a-42aa02fffd8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352046100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_rw
.352046100
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1660057128
Short name T895
Test name
Test status
Simulation time 2130972662 ps
CPU time 1.07 seconds
Started Jun 29 06:27:11 PM PDT 24
Finished Jun 29 06:27:13 PM PDT 24
Peak memory 201716 kb
Host smart-5a9b8a55-b52c-4bde-b71a-338928da7d7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660057128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.1660057128
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2559679554
Short name T827
Test name
Test status
Simulation time 5005937165 ps
CPU time 7.36 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:27:22 PM PDT 24
Peak memory 202244 kb
Host smart-8f8630cf-0dc4-406d-9984-9aa5e0f602e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559679554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_same_csr_outstanding.2559679554
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.4097123698
Short name T897
Test name
Test status
Simulation time 2044464802 ps
CPU time 3.04 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:27:18 PM PDT 24
Peak memory 201932 kb
Host smart-65f2e7b0-67e4-4748-959a-104cc5abaa32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097123698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error
s.4097123698
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2936705249
Short name T884
Test name
Test status
Simulation time 23521328756 ps
CPU time 4.67 seconds
Started Jun 29 06:27:15 PM PDT 24
Finished Jun 29 06:27:21 PM PDT 24
Peak memory 202328 kb
Host smart-ea26a494-a5cb-44cb-8602-25cf97f1d401
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936705249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.2936705249
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3231992169
Short name T870
Test name
Test status
Simulation time 2010297360 ps
CPU time 5.34 seconds
Started Jun 29 06:27:29 PM PDT 24
Finished Jun 29 06:27:34 PM PDT 24
Peak memory 201812 kb
Host smart-8524838b-e8ad-4f69-bbcc-ff79daa3d4b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231992169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_te
st.3231992169
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.581580621
Short name T825
Test name
Test status
Simulation time 2034923107 ps
CPU time 1.75 seconds
Started Jun 29 06:27:29 PM PDT 24
Finished Jun 29 06:27:31 PM PDT 24
Peak memory 201716 kb
Host smart-30500058-4948-46bf-b838-aa47daa1f44b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581580621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_tes
t.581580621
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2756257277
Short name T850
Test name
Test status
Simulation time 2052633172 ps
CPU time 1.29 seconds
Started Jun 29 06:27:33 PM PDT 24
Finished Jun 29 06:27:35 PM PDT 24
Peak memory 201864 kb
Host smart-67c52922-9a51-4544-aca7-2e0f9f64bbb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756257277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_te
st.2756257277
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1696725809
Short name T853
Test name
Test status
Simulation time 2019331997 ps
CPU time 3 seconds
Started Jun 29 06:27:28 PM PDT 24
Finished Jun 29 06:27:32 PM PDT 24
Peak memory 201700 kb
Host smart-1ea51b5b-bacd-4f1a-83c4-e15f78fef564
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696725809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.1696725809
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.990565109
Short name T883
Test name
Test status
Simulation time 2037120207 ps
CPU time 1.95 seconds
Started Jun 29 06:27:31 PM PDT 24
Finished Jun 29 06:27:33 PM PDT 24
Peak memory 201692 kb
Host smart-423fe8e8-aaad-4af6-aa6f-5c0dac6cf3d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990565109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_tes
t.990565109
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.1828473858
Short name T809
Test name
Test status
Simulation time 2012615909 ps
CPU time 5.89 seconds
Started Jun 29 06:27:29 PM PDT 24
Finished Jun 29 06:27:35 PM PDT 24
Peak memory 201836 kb
Host smart-6b0b91b2-1327-4549-9524-3bfc9513a8c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828473858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.1828473858
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.3497851430
Short name T794
Test name
Test status
Simulation time 2025483955 ps
CPU time 1.9 seconds
Started Jun 29 06:27:34 PM PDT 24
Finished Jun 29 06:27:36 PM PDT 24
Peak memory 201864 kb
Host smart-8e1920d0-6f50-4e29-a87d-b3edb07d003f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497851430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_te
st.3497851430
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.2133987490
Short name T784
Test name
Test status
Simulation time 2009723668 ps
CPU time 5.8 seconds
Started Jun 29 06:27:30 PM PDT 24
Finished Jun 29 06:27:36 PM PDT 24
Peak memory 201700 kb
Host smart-08aa163e-4e9e-4ba6-8979-2723fd687e80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133987490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_te
st.2133987490
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.3085855091
Short name T844
Test name
Test status
Simulation time 2057121921 ps
CPU time 1.17 seconds
Started Jun 29 06:27:29 PM PDT 24
Finished Jun 29 06:27:31 PM PDT 24
Peak memory 201740 kb
Host smart-552d0a2c-ae05-4898-bfb5-7849dea227ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085855091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_te
st.3085855091
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.184796862
Short name T817
Test name
Test status
Simulation time 2021145825 ps
CPU time 2.82 seconds
Started Jun 29 06:27:28 PM PDT 24
Finished Jun 29 06:27:32 PM PDT 24
Peak memory 201704 kb
Host smart-aa582c7f-d5ab-4164-9c07-2427f6074631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184796862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_tes
t.184796862
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.4085996420
Short name T364
Test name
Test status
Simulation time 3036530905 ps
CPU time 4.73 seconds
Started Jun 29 06:27:13 PM PDT 24
Finished Jun 29 06:27:18 PM PDT 24
Peak memory 202200 kb
Host smart-4213d176-ae65-4526-a10b-d6da51fcd0e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085996420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_aliasing.4085996420
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.542886392
Short name T892
Test name
Test status
Simulation time 41584866396 ps
CPU time 80.62 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:28:36 PM PDT 24
Peak memory 202244 kb
Host smart-8f86fef2-bf9b-4ef1-a273-776773a80266
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542886392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_bit_bash.542886392
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.239683633
Short name T357
Test name
Test status
Simulation time 6014357533 ps
CPU time 14.96 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:27:30 PM PDT 24
Peak memory 202092 kb
Host smart-6e0a03a5-caa0-4ab0-9953-20e9b2a89a71
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239683633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_hw_reset.239683633
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1920666208
Short name T828
Test name
Test status
Simulation time 2068294030 ps
CPU time 6.17 seconds
Started Jun 29 06:27:15 PM PDT 24
Finished Jun 29 06:27:22 PM PDT 24
Peak memory 201940 kb
Host smart-637cd1da-723e-4d8a-80a2-b3f438d04232
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920666208 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1920666208
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3380368409
Short name T864
Test name
Test status
Simulation time 2050992594 ps
CPU time 5.69 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:27:21 PM PDT 24
Peak memory 201972 kb
Host smart-419eff82-c15c-49a3-a946-7ffe71728f21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380368409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r
w.3380368409
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.3657905450
Short name T811
Test name
Test status
Simulation time 2015051133 ps
CPU time 5.69 seconds
Started Jun 29 06:27:15 PM PDT 24
Finished Jun 29 06:27:22 PM PDT 24
Peak memory 201864 kb
Host smart-01f025ce-807a-415b-b26c-a27cb33a93b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657905450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes
t.3657905450
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.405938227
Short name T372
Test name
Test status
Simulation time 5220682727 ps
CPU time 6.33 seconds
Started Jun 29 06:27:16 PM PDT 24
Finished Jun 29 06:27:24 PM PDT 24
Peak memory 202272 kb
Host smart-9206fef2-4a33-476a-9776-46a404d626c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405938227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
sysrst_ctrl_same_csr_outstanding.405938227
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3121673652
Short name T395
Test name
Test status
Simulation time 42394925446 ps
CPU time 104.92 seconds
Started Jun 29 06:27:15 PM PDT 24
Finished Jun 29 06:29:02 PM PDT 24
Peak memory 202252 kb
Host smart-f8a57c87-8b11-4dfd-afad-a877f9aeb557
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121673652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_tl_intg_err.3121673652
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1299193993
Short name T881
Test name
Test status
Simulation time 2058332278 ps
CPU time 1.07 seconds
Started Jun 29 06:27:27 PM PDT 24
Finished Jun 29 06:27:29 PM PDT 24
Peak memory 201684 kb
Host smart-dd7eb939-74ce-4ac0-9fee-2719bdecb9ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299193993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_te
st.1299193993
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.693424766
Short name T785
Test name
Test status
Simulation time 2012024721 ps
CPU time 5.71 seconds
Started Jun 29 06:27:32 PM PDT 24
Finished Jun 29 06:27:38 PM PDT 24
Peak memory 201872 kb
Host smart-d5a72e34-9c9c-456f-9e4f-2686d6fd8f9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693424766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_tes
t.693424766
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1239132116
Short name T797
Test name
Test status
Simulation time 2039451954 ps
CPU time 1.91 seconds
Started Jun 29 06:27:30 PM PDT 24
Finished Jun 29 06:27:32 PM PDT 24
Peak memory 201700 kb
Host smart-cb83d430-8fdc-4e6d-9af2-3f803022e66a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239132116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.1239132116
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3036916015
Short name T802
Test name
Test status
Simulation time 2021154953 ps
CPU time 3.21 seconds
Started Jun 29 06:27:30 PM PDT 24
Finished Jun 29 06:27:34 PM PDT 24
Peak memory 201860 kb
Host smart-468f82dd-ec46-4b70-8014-2c601ba64063
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036916015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_te
st.3036916015
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.172256986
Short name T821
Test name
Test status
Simulation time 2036781313 ps
CPU time 2.14 seconds
Started Jun 29 06:27:33 PM PDT 24
Finished Jun 29 06:27:35 PM PDT 24
Peak memory 201756 kb
Host smart-cbb2de2b-866e-4340-a9b7-5c05fe44a9f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172256986 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_tes
t.172256986
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1349332729
Short name T873
Test name
Test status
Simulation time 2048840300 ps
CPU time 2 seconds
Started Jun 29 06:27:28 PM PDT 24
Finished Jun 29 06:27:30 PM PDT 24
Peak memory 201684 kb
Host smart-5276a6de-4e21-4162-bbad-9ca62f7fb7ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349332729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.1349332729
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1302641361
Short name T900
Test name
Test status
Simulation time 2016185309 ps
CPU time 5.96 seconds
Started Jun 29 06:27:39 PM PDT 24
Finished Jun 29 06:27:46 PM PDT 24
Peak memory 201712 kb
Host smart-fdbd3702-a9f6-42db-ae2c-a22e6f1d3b9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302641361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_te
st.1302641361
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.2517128117
Short name T824
Test name
Test status
Simulation time 2013352911 ps
CPU time 6.06 seconds
Started Jun 29 06:27:40 PM PDT 24
Finished Jun 29 06:27:47 PM PDT 24
Peak memory 201868 kb
Host smart-1299bbce-ea6b-4f4a-a0c5-c93974a174a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517128117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_te
st.2517128117
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1718173976
Short name T799
Test name
Test status
Simulation time 2037423082 ps
CPU time 1.88 seconds
Started Jun 29 06:27:37 PM PDT 24
Finished Jun 29 06:27:40 PM PDT 24
Peak memory 201708 kb
Host smart-72d4d267-1f23-4abd-9e54-f4143086ca1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718173976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te
st.1718173976
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.531528309
Short name T848
Test name
Test status
Simulation time 2012918859 ps
CPU time 6.27 seconds
Started Jun 29 06:27:40 PM PDT 24
Finished Jun 29 06:27:47 PM PDT 24
Peak memory 201704 kb
Host smart-7216e844-d314-424c-9e69-e3da549ca54d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531528309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_tes
t.531528309
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1893004746
Short name T804
Test name
Test status
Simulation time 2101652373 ps
CPU time 6.43 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:27:21 PM PDT 24
Peak memory 201860 kb
Host smart-52891df8-3123-418e-bb90-52ab82f01deb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893004746 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1893004746
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2477978923
Short name T861
Test name
Test status
Simulation time 2061733151 ps
CPU time 6.46 seconds
Started Jun 29 06:27:13 PM PDT 24
Finished Jun 29 06:27:21 PM PDT 24
Peak memory 201992 kb
Host smart-e3aad37f-c953-460b-99f1-70c0be119db8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477978923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.2477978923
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2718801904
Short name T801
Test name
Test status
Simulation time 2043691383 ps
CPU time 1.54 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:27:17 PM PDT 24
Peak memory 201740 kb
Host smart-73d2ba6c-9104-464f-9c1c-86fcc266f48e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718801904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_tes
t.2718801904
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.1993841811
Short name T822
Test name
Test status
Simulation time 4968752251 ps
CPU time 12.37 seconds
Started Jun 29 06:27:11 PM PDT 24
Finished Jun 29 06:27:24 PM PDT 24
Peak memory 202004 kb
Host smart-e77e4eba-bb63-4cd9-8b78-0363d217ab28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993841811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.1993841811
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.1558462570
Short name T845
Test name
Test status
Simulation time 2369792963 ps
CPU time 3.23 seconds
Started Jun 29 06:27:16 PM PDT 24
Finished Jun 29 06:27:21 PM PDT 24
Peak memory 202292 kb
Host smart-ca661455-50e4-4f38-a01a-6fab5013d900
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558462570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_error
s.1558462570
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3824375495
Short name T322
Test name
Test status
Simulation time 22279578060 ps
CPU time 49.68 seconds
Started Jun 29 06:27:12 PM PDT 24
Finished Jun 29 06:28:02 PM PDT 24
Peak memory 202296 kb
Host smart-814a0ba4-e561-4c5a-a329-437166044bd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824375495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_tl_intg_err.3824375495
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3279217472
Short name T812
Test name
Test status
Simulation time 2249282020 ps
CPU time 2.54 seconds
Started Jun 29 06:27:13 PM PDT 24
Finished Jun 29 06:27:16 PM PDT 24
Peak memory 202152 kb
Host smart-c6a588c1-d9bc-427c-8597-03e385a88a40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279217472 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3279217472
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.425114735
Short name T820
Test name
Test status
Simulation time 2023285849 ps
CPU time 3.13 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:27:18 PM PDT 24
Peak memory 201704 kb
Host smart-3ff5e7a3-f084-44fe-8f22-2e396701c0a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425114735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test
.425114735
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3662620738
Short name T894
Test name
Test status
Simulation time 10272260392 ps
CPU time 26.66 seconds
Started Jun 29 06:27:17 PM PDT 24
Finished Jun 29 06:27:44 PM PDT 24
Peak memory 202292 kb
Host smart-68f95845-2b29-400a-a46c-c504e9c7fb5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662620738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.3662620738
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.397667919
Short name T833
Test name
Test status
Simulation time 2053090647 ps
CPU time 6.44 seconds
Started Jun 29 06:27:17 PM PDT 24
Finished Jun 29 06:27:24 PM PDT 24
Peak memory 202136 kb
Host smart-155ac337-38b9-469d-a077-eb8416d67064
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397667919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors
.397667919
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3164735846
Short name T875
Test name
Test status
Simulation time 22280615310 ps
CPU time 15.61 seconds
Started Jun 29 06:27:13 PM PDT 24
Finished Jun 29 06:27:29 PM PDT 24
Peak memory 202324 kb
Host smart-e1dad5cd-aa03-47ad-a815-045d9912f52f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164735846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.3164735846
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.739658439
Short name T863
Test name
Test status
Simulation time 2054243437 ps
CPU time 3.42 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:27:18 PM PDT 24
Peak memory 202036 kb
Host smart-10cbcc6c-2253-4b55-9682-509c932b55a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739658439 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.739658439
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.2963048522
Short name T815
Test name
Test status
Simulation time 2033857426 ps
CPU time 5.55 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:27:21 PM PDT 24
Peak memory 201980 kb
Host smart-cc213144-9c1d-4a7f-a4ac-bd5b14fa7c63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963048522 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_r
w.2963048522
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.671256523
Short name T858
Test name
Test status
Simulation time 2015021320 ps
CPU time 3.48 seconds
Started Jun 29 06:27:16 PM PDT 24
Finished Jun 29 06:27:21 PM PDT 24
Peak memory 201668 kb
Host smart-6b09743e-9916-4a8b-beb4-77413a35c640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671256523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test
.671256523
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.1750911292
Short name T800
Test name
Test status
Simulation time 9102374208 ps
CPU time 31.2 seconds
Started Jun 29 06:27:13 PM PDT 24
Finished Jun 29 06:27:46 PM PDT 24
Peak memory 202240 kb
Host smart-1d0edf4d-6829-48d4-bb25-d119813626c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750911292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.1750911292
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.2644429352
Short name T842
Test name
Test status
Simulation time 2056807178 ps
CPU time 4.07 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:27:19 PM PDT 24
Peak memory 202164 kb
Host smart-774e394a-ecc7-4b5e-8b35-8c48831a9103
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644429352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error
s.2644429352
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.2683348224
Short name T872
Test name
Test status
Simulation time 42512729079 ps
CPU time 30.61 seconds
Started Jun 29 06:27:13 PM PDT 24
Finished Jun 29 06:27:44 PM PDT 24
Peak memory 202276 kb
Host smart-aaa4f6be-bdbd-451d-ba53-c7bda84e77f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683348224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.2683348224
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3165698415
Short name T896
Test name
Test status
Simulation time 2238816958 ps
CPU time 2.45 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:27:18 PM PDT 24
Peak memory 202028 kb
Host smart-3419ff62-6ed5-4316-a358-32784aea1d6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165698415 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3165698415
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3535184671
Short name T368
Test name
Test status
Simulation time 2054095102 ps
CPU time 3.5 seconds
Started Jun 29 06:27:15 PM PDT 24
Finished Jun 29 06:27:20 PM PDT 24
Peak memory 201988 kb
Host smart-bca39846-ab0e-4cdb-b17f-710f16f08399
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535184671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_r
w.3535184671
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.446825077
Short name T854
Test name
Test status
Simulation time 2016678635 ps
CPU time 5.07 seconds
Started Jun 29 06:27:16 PM PDT 24
Finished Jun 29 06:27:23 PM PDT 24
Peak memory 201740 kb
Host smart-e913a73c-dcd0-4d69-a640-0ac273a66bdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446825077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test
.446825077
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.1242104322
Short name T810
Test name
Test status
Simulation time 9692324489 ps
CPU time 25.6 seconds
Started Jun 29 06:27:13 PM PDT 24
Finished Jun 29 06:27:39 PM PDT 24
Peak memory 202316 kb
Host smart-e96f0a7a-ead1-4655-9d21-28e562f6c4b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242104322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_same_csr_outstanding.1242104322
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.597745728
Short name T330
Test name
Test status
Simulation time 2089907870 ps
CPU time 6.52 seconds
Started Jun 29 06:27:13 PM PDT 24
Finished Jun 29 06:27:20 PM PDT 24
Peak memory 202112 kb
Host smart-abc5e1a5-978a-43b2-8e8b-5293448bee74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597745728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors
.597745728
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3280832283
Short name T899
Test name
Test status
Simulation time 22219060407 ps
CPU time 56.52 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:28:12 PM PDT 24
Peak memory 202296 kb
Host smart-6e4f42f2-9535-4114-a275-09903521f9ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280832283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.3280832283
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1726727524
Short name T852
Test name
Test status
Simulation time 2121099052 ps
CPU time 2 seconds
Started Jun 29 06:27:15 PM PDT 24
Finished Jun 29 06:27:18 PM PDT 24
Peak memory 202044 kb
Host smart-f5087a31-49ab-49cd-aac5-1560b4a1a23b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726727524 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1726727524
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3968472194
Short name T879
Test name
Test status
Simulation time 2040899599 ps
CPU time 6.05 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:27:21 PM PDT 24
Peak memory 201980 kb
Host smart-57712027-7389-45e9-8b44-316c39ef3a33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968472194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_r
w.3968472194
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.1070666133
Short name T787
Test name
Test status
Simulation time 2057678370 ps
CPU time 1.36 seconds
Started Jun 29 06:27:14 PM PDT 24
Finished Jun 29 06:27:16 PM PDT 24
Peak memory 201868 kb
Host smart-15af011a-00e9-4219-92b8-35a1593dacf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070666133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_tes
t.1070666133
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3277111118
Short name T888
Test name
Test status
Simulation time 5348563739 ps
CPU time 4.49 seconds
Started Jun 29 06:27:15 PM PDT 24
Finished Jun 29 06:27:21 PM PDT 24
Peak memory 202236 kb
Host smart-98ca1205-7f93-438b-9083-b1c11d5dd4a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277111118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_same_csr_outstanding.3277111118
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2061342051
Short name T839
Test name
Test status
Simulation time 2076927760 ps
CPU time 4.66 seconds
Started Jun 29 06:27:15 PM PDT 24
Finished Jun 29 06:27:21 PM PDT 24
Peak memory 202160 kb
Host smart-b490e32c-3ed3-4cf8-9f54-90d7170339e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061342051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.2061342051
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2421228568
Short name T321
Test name
Test status
Simulation time 42443939318 ps
CPU time 104.92 seconds
Started Jun 29 06:27:18 PM PDT 24
Finished Jun 29 06:29:03 PM PDT 24
Peak memory 202280 kb
Host smart-8819936b-f37f-4132-b4e5-1a4b5e369103
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421228568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.2421228568
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.692625196
Short name T480
Test name
Test status
Simulation time 2019959935 ps
CPU time 3.18 seconds
Started Jun 29 06:31:25 PM PDT 24
Finished Jun 29 06:31:28 PM PDT 24
Peak memory 201440 kb
Host smart-d3eaa7c8-f257-46a1-8cad-443e57dcb548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692625196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test
.692625196
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.3261998174
Short name T637
Test name
Test status
Simulation time 3152495961 ps
CPU time 8.46 seconds
Started Jun 29 06:31:25 PM PDT 24
Finished Jun 29 06:31:34 PM PDT 24
Peak memory 201576 kb
Host smart-e944e1a3-04d6-4e58-9de5-e9fa3b86e865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261998174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.3261998174
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.3508652237
Short name T383
Test name
Test status
Simulation time 89493732959 ps
CPU time 225.12 seconds
Started Jun 29 06:31:24 PM PDT 24
Finished Jun 29 06:35:10 PM PDT 24
Peak memory 201848 kb
Host smart-9079a24e-068c-4d0c-9a65-1d665fea49a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508652237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_combo_detect.3508652237
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2327224827
Short name T603
Test name
Test status
Simulation time 2431587081 ps
CPU time 7.16 seconds
Started Jun 29 06:31:19 PM PDT 24
Finished Jun 29 06:31:27 PM PDT 24
Peak memory 201448 kb
Host smart-fb555a21-4b59-43cb-9cfb-21979c813002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327224827 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.2327224827
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2479989167
Short name T193
Test name
Test status
Simulation time 2298521994 ps
CPU time 6.77 seconds
Started Jun 29 06:31:26 PM PDT 24
Finished Jun 29 06:31:33 PM PDT 24
Peak memory 201524 kb
Host smart-e1609511-affb-4a0f-9734-4e2e1b3338fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479989167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2479989167
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.3881310727
Short name T227
Test name
Test status
Simulation time 3162415194 ps
CPU time 6.72 seconds
Started Jun 29 06:31:23 PM PDT 24
Finished Jun 29 06:31:31 PM PDT 24
Peak memory 201492 kb
Host smart-2494a8f4-dd62-4e6b-9432-fac8e14c24be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881310727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.3881310727
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.3499545097
Short name T425
Test name
Test status
Simulation time 2627252740 ps
CPU time 2.98 seconds
Started Jun 29 06:31:25 PM PDT 24
Finished Jun 29 06:31:29 PM PDT 24
Peak memory 201512 kb
Host smart-590043ca-62f9-49f4-ab73-46bf00cce304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499545097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.3499545097
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.265583903
Short name T127
Test name
Test status
Simulation time 2461162211 ps
CPU time 4.15 seconds
Started Jun 29 06:31:26 PM PDT 24
Finished Jun 29 06:31:31 PM PDT 24
Peak memory 201720 kb
Host smart-a12ae129-c2b1-4d26-9819-42b0c5d3dc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265583903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.265583903
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.1092441491
Short name T470
Test name
Test status
Simulation time 2065948600 ps
CPU time 6.4 seconds
Started Jun 29 06:31:26 PM PDT 24
Finished Jun 29 06:31:33 PM PDT 24
Peak memory 201460 kb
Host smart-97c371ef-f4d4-4ead-9bfc-854b022ebf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092441491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.1092441491
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.1367912056
Short name T313
Test name
Test status
Simulation time 2520686038 ps
CPU time 2.3 seconds
Started Jun 29 06:31:23 PM PDT 24
Finished Jun 29 06:31:26 PM PDT 24
Peak memory 201532 kb
Host smart-1f6c45ad-fcb4-4023-ad86-a65d23094cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367912056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.1367912056
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.2684430047
Short name T447
Test name
Test status
Simulation time 2112975143 ps
CPU time 5.41 seconds
Started Jun 29 06:31:18 PM PDT 24
Finished Jun 29 06:31:25 PM PDT 24
Peak memory 201392 kb
Host smart-6bb9b0dd-d8c4-4bd4-bdb9-aabfc19a6b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684430047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.2684430047
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.1065844450
Short name T596
Test name
Test status
Simulation time 7149177965 ps
CPU time 2.42 seconds
Started Jun 29 06:31:27 PM PDT 24
Finished Jun 29 06:31:30 PM PDT 24
Peak memory 201552 kb
Host smart-1c368426-4195-47d8-b417-7add37ffdad0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065844450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ultra_low_pwr.1065844450
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.4041207175
Short name T486
Test name
Test status
Simulation time 2011326539 ps
CPU time 5.86 seconds
Started Jun 29 06:31:25 PM PDT 24
Finished Jun 29 06:31:32 PM PDT 24
Peak memory 201468 kb
Host smart-454d5a70-8b95-4a9e-a35c-061d8a186c8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041207175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_tes
t.4041207175
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.2231024989
Short name T467
Test name
Test status
Simulation time 3320910761 ps
CPU time 4.83 seconds
Started Jun 29 06:31:25 PM PDT 24
Finished Jun 29 06:31:31 PM PDT 24
Peak memory 201576 kb
Host smart-a6dcc40f-b71d-47e5-9638-c78fc28f8efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231024989 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.2231024989
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2721194608
Short name T116
Test name
Test status
Simulation time 2435810934 ps
CPU time 7.16 seconds
Started Jun 29 06:31:25 PM PDT 24
Finished Jun 29 06:31:33 PM PDT 24
Peak memory 201520 kb
Host smart-ef1697f1-ee36-4195-b904-38dff0d7478d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721194608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.2721194608
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1316121313
Short name T512
Test name
Test status
Simulation time 2527680929 ps
CPU time 6.72 seconds
Started Jun 29 06:31:25 PM PDT 24
Finished Jun 29 06:31:32 PM PDT 24
Peak memory 201532 kb
Host smart-caec79b3-7e4f-4292-9f23-9ab2c99fc0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316121313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1316121313
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.223266701
Short name T250
Test name
Test status
Simulation time 3061929380 ps
CPU time 7.4 seconds
Started Jun 29 06:31:22 PM PDT 24
Finished Jun 29 06:31:30 PM PDT 24
Peak memory 201500 kb
Host smart-99790807-2dc1-4b7a-9af4-b51126390bbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223266701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_ec_pwr_on_rst.223266701
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.1288771781
Short name T578
Test name
Test status
Simulation time 485285594584 ps
CPU time 289.19 seconds
Started Jun 29 06:31:27 PM PDT 24
Finished Jun 29 06:36:17 PM PDT 24
Peak memory 201556 kb
Host smart-3283839e-dd0b-44c7-a706-f63192abe799
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288771781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.1288771781
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.2905153429
Short name T432
Test name
Test status
Simulation time 2618335354 ps
CPU time 4.32 seconds
Started Jun 29 06:31:28 PM PDT 24
Finished Jun 29 06:31:33 PM PDT 24
Peak memory 201440 kb
Host smart-37df8557-35b4-4797-94ed-164fc5cb0479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905153429 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.2905153429
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.3490012837
Short name T25
Test name
Test status
Simulation time 2482106407 ps
CPU time 6.81 seconds
Started Jun 29 06:31:26 PM PDT 24
Finished Jun 29 06:31:34 PM PDT 24
Peak memory 201500 kb
Host smart-4b67635d-c018-4d3f-b433-e558a1db11c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490012837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.3490012837
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.1999731789
Short name T724
Test name
Test status
Simulation time 2057031434 ps
CPU time 5.82 seconds
Started Jun 29 06:31:25 PM PDT 24
Finished Jun 29 06:31:31 PM PDT 24
Peak memory 201460 kb
Host smart-7e3d45f1-2b56-499d-9b95-6fc0de47b5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999731789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.1999731789
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.1383661489
Short name T623
Test name
Test status
Simulation time 2533935460 ps
CPU time 2.42 seconds
Started Jun 29 06:31:29 PM PDT 24
Finished Jun 29 06:31:31 PM PDT 24
Peak memory 201440 kb
Host smart-ac84cc29-f678-4a29-9bdf-e5dc076313cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383661489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.1383661489
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.1540404031
Short name T337
Test name
Test status
Simulation time 42121813273 ps
CPU time 22.43 seconds
Started Jun 29 06:31:25 PM PDT 24
Finished Jun 29 06:31:48 PM PDT 24
Peak memory 221272 kb
Host smart-3e606dd8-8e08-4d3c-904f-55202618e0d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540404031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.1540404031
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.2052595263
Short name T140
Test name
Test status
Simulation time 2159666979 ps
CPU time 1.36 seconds
Started Jun 29 06:31:25 PM PDT 24
Finished Jun 29 06:31:26 PM PDT 24
Peak memory 201468 kb
Host smart-145cfd61-3ec0-4afe-b5d0-2107ac282737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052595263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.2052595263
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.4292036359
Short name T716
Test name
Test status
Simulation time 3058298000 ps
CPU time 6.29 seconds
Started Jun 29 06:31:29 PM PDT 24
Finished Jun 29 06:31:35 PM PDT 24
Peak memory 201416 kb
Host smart-c048d025-c55a-4a77-87d1-aa9e8df69d0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292036359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ultra_low_pwr.4292036359
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.1303772603
Short name T444
Test name
Test status
Simulation time 2014271804 ps
CPU time 3.64 seconds
Started Jun 29 06:31:53 PM PDT 24
Finished Jun 29 06:31:58 PM PDT 24
Peak memory 201512 kb
Host smart-89113b88-c462-4fa7-bc29-56f069ebc62f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303772603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te
st.1303772603
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.240654306
Short name T234
Test name
Test status
Simulation time 3679998580 ps
CPU time 2.46 seconds
Started Jun 29 06:31:49 PM PDT 24
Finished Jun 29 06:31:53 PM PDT 24
Peak memory 201596 kb
Host smart-8a81b840-4512-481f-9b58-4f6966e8a9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240654306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.240654306
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.2315126845
Short name T219
Test name
Test status
Simulation time 54107471221 ps
CPU time 74.58 seconds
Started Jun 29 06:31:47 PM PDT 24
Finished Jun 29 06:33:02 PM PDT 24
Peak memory 201844 kb
Host smart-0c24ddad-daf8-46f1-a98e-9a98d91556db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315126845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_combo_detect.2315126845
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1037501614
Short name T314
Test name
Test status
Simulation time 42543801120 ps
CPU time 31.26 seconds
Started Jun 29 06:31:49 PM PDT 24
Finished Jun 29 06:32:22 PM PDT 24
Peak memory 201804 kb
Host smart-31744c65-0bca-4a9e-a0eb-57a11f343e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037501614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_w
ith_pre_cond.1037501614
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2064024405
Short name T471
Test name
Test status
Simulation time 3382835691 ps
CPU time 5.89 seconds
Started Jun 29 06:31:50 PM PDT 24
Finished Jun 29 06:31:57 PM PDT 24
Peak memory 201496 kb
Host smart-5f05b067-77f3-41bd-bc72-c92466ce860e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064024405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ec_pwr_on_rst.2064024405
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.952643023
Short name T751
Test name
Test status
Simulation time 2377653282 ps
CPU time 6.4 seconds
Started Jun 29 06:31:52 PM PDT 24
Finished Jun 29 06:31:58 PM PDT 24
Peak memory 201460 kb
Host smart-31ee804a-c7ea-4a0e-8233-903af201e923
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952643023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctr
l_edge_detect.952643023
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.1627412190
Short name T248
Test name
Test status
Simulation time 2611423031 ps
CPU time 7.46 seconds
Started Jun 29 06:31:51 PM PDT 24
Finished Jun 29 06:31:59 PM PDT 24
Peak memory 201484 kb
Host smart-4345c889-1e0d-4982-9948-dbaf76ec27ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627412190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.1627412190
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.3724761874
Short name T446
Test name
Test status
Simulation time 2502911998 ps
CPU time 1.58 seconds
Started Jun 29 06:31:52 PM PDT 24
Finished Jun 29 06:31:54 PM PDT 24
Peak memory 201524 kb
Host smart-24a64347-8869-47d9-b7c3-dd61b61ff433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724761874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.3724761874
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.1926099888
Short name T519
Test name
Test status
Simulation time 2077538334 ps
CPU time 2.45 seconds
Started Jun 29 06:31:47 PM PDT 24
Finished Jun 29 06:31:51 PM PDT 24
Peak memory 201456 kb
Host smart-ae458864-7e99-45f0-9e2f-77a0c1597b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926099888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.1926099888
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.1918751214
Short name T555
Test name
Test status
Simulation time 2509463652 ps
CPU time 7.06 seconds
Started Jun 29 06:31:49 PM PDT 24
Finished Jun 29 06:31:57 PM PDT 24
Peak memory 201524 kb
Host smart-06301bcc-9afc-4395-bdfc-872b03ceb9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918751214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.1918751214
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.954318204
Short name T571
Test name
Test status
Simulation time 2124887211 ps
CPU time 2.19 seconds
Started Jun 29 06:31:54 PM PDT 24
Finished Jun 29 06:31:57 PM PDT 24
Peak memory 201448 kb
Host smart-72a42953-05b6-4f5c-8168-0380cd23568f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954318204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.954318204
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.2585707728
Short name T768
Test name
Test status
Simulation time 8238509014 ps
CPU time 23.16 seconds
Started Jun 29 06:31:53 PM PDT 24
Finished Jun 29 06:32:18 PM PDT 24
Peak memory 201564 kb
Host smart-bb7be290-7631-42d0-98d9-7df87286107e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585707728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.2585707728
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.1973158262
Short name T113
Test name
Test status
Simulation time 2153548978 ps
CPU time 0.95 seconds
Started Jun 29 06:31:53 PM PDT 24
Finished Jun 29 06:31:55 PM PDT 24
Peak memory 201576 kb
Host smart-cb86cf55-4f90-4a77-a0cc-88b2924a1257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973158262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te
st.1973158262
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2847120536
Short name T664
Test name
Test status
Simulation time 3078404205 ps
CPU time 2.7 seconds
Started Jun 29 06:31:48 PM PDT 24
Finished Jun 29 06:31:52 PM PDT 24
Peak memory 201564 kb
Host smart-15ad00f5-10ae-40f8-8c95-59c019363007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847120536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.2
847120536
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.627784898
Short name T652
Test name
Test status
Simulation time 140036723360 ps
CPU time 93.62 seconds
Started Jun 29 06:31:47 PM PDT 24
Finished Jun 29 06:33:22 PM PDT 24
Peak memory 201752 kb
Host smart-fb81cc1d-6a92-4496-8ab6-499b32103461
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627784898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_combo_detect.627784898
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3895218150
Short name T406
Test name
Test status
Simulation time 51615903133 ps
CPU time 33.23 seconds
Started Jun 29 06:31:47 PM PDT 24
Finished Jun 29 06:32:22 PM PDT 24
Peak memory 201896 kb
Host smart-f1bb470c-5d08-4f34-8d64-0ce7288311a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895218150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_w
ith_pre_cond.3895218150
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.203293555
Short name T717
Test name
Test status
Simulation time 4069471747 ps
CPU time 10.85 seconds
Started Jun 29 06:31:48 PM PDT 24
Finished Jun 29 06:32:00 PM PDT 24
Peak memory 201500 kb
Host smart-2173aa92-5585-4490-834f-6645db266d34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203293555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_ec_pwr_on_rst.203293555
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.4197315947
Short name T168
Test name
Test status
Simulation time 4413541533 ps
CPU time 11.11 seconds
Started Jun 29 06:31:49 PM PDT 24
Finished Jun 29 06:32:01 PM PDT 24
Peak memory 201552 kb
Host smart-5d929696-1f36-48f0-8395-8cf3e28474db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197315947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_edge_detect.4197315947
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.2147564136
Short name T187
Test name
Test status
Simulation time 2636827859 ps
CPU time 2.37 seconds
Started Jun 29 06:31:50 PM PDT 24
Finished Jun 29 06:31:53 PM PDT 24
Peak memory 201524 kb
Host smart-66220669-465d-4c65-8f57-a52792db2c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147564136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.2147564136
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.3222900016
Short name T499
Test name
Test status
Simulation time 2485174332 ps
CPU time 2.41 seconds
Started Jun 29 06:31:52 PM PDT 24
Finished Jun 29 06:31:55 PM PDT 24
Peak memory 201456 kb
Host smart-e7e7416f-8f9a-41b2-8038-8bfb17990219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222900016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.3222900016
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.1157819287
Short name T642
Test name
Test status
Simulation time 2214985678 ps
CPU time 1.13 seconds
Started Jun 29 06:31:49 PM PDT 24
Finished Jun 29 06:31:52 PM PDT 24
Peak memory 201512 kb
Host smart-4a754968-0dbc-4f11-b7bd-383aa460af58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157819287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.1157819287
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.3529529687
Short name T561
Test name
Test status
Simulation time 2514133483 ps
CPU time 3.94 seconds
Started Jun 29 06:31:49 PM PDT 24
Finished Jun 29 06:31:54 PM PDT 24
Peak memory 201516 kb
Host smart-9c27be5d-5541-4e44-88b2-458bfec1a28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529529687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.3529529687
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.946284872
Short name T74
Test name
Test status
Simulation time 2114288806 ps
CPU time 5.93 seconds
Started Jun 29 06:31:52 PM PDT 24
Finished Jun 29 06:31:59 PM PDT 24
Peak memory 201452 kb
Host smart-309d38b6-bbbb-44d7-ada3-974a30c21372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946284872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.946284872
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.369095044
Short name T236
Test name
Test status
Simulation time 8249822565 ps
CPU time 11.17 seconds
Started Jun 29 06:31:49 PM PDT 24
Finished Jun 29 06:32:01 PM PDT 24
Peak memory 201556 kb
Host smart-cd471e71-7b27-49f5-ad89-00dbbcd406f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369095044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_st
ress_all.369095044
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1093176670
Short name T653
Test name
Test status
Simulation time 9920699684 ps
CPU time 1.93 seconds
Started Jun 29 06:31:47 PM PDT 24
Finished Jun 29 06:31:51 PM PDT 24
Peak memory 201560 kb
Host smart-546c883d-a76c-4b46-b705-aaac7517a9d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093176670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ultra_low_pwr.1093176670
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.3777473034
Short name T157
Test name
Test status
Simulation time 2010855729 ps
CPU time 6.07 seconds
Started Jun 29 06:31:50 PM PDT 24
Finished Jun 29 06:31:57 PM PDT 24
Peak memory 201480 kb
Host smart-6ed7fb1e-a660-4d13-a9c7-9f54690a435a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777473034 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te
st.3777473034
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.1154677439
Short name T620
Test name
Test status
Simulation time 248864734134 ps
CPU time 304.95 seconds
Started Jun 29 06:31:52 PM PDT 24
Finished Jun 29 06:36:57 PM PDT 24
Peak memory 201636 kb
Host smart-994949d4-6aaf-4252-830b-7df1b80ab54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154677439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.1
154677439
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.1612952359
Short name T277
Test name
Test status
Simulation time 85402723439 ps
CPU time 23.85 seconds
Started Jun 29 06:31:49 PM PDT 24
Finished Jun 29 06:32:14 PM PDT 24
Peak memory 201764 kb
Host smart-589964bf-7449-4bc7-9664-bace85dfa48c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612952359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.1612952359
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2158209222
Short name T45
Test name
Test status
Simulation time 113920820843 ps
CPU time 143.91 seconds
Started Jun 29 06:31:53 PM PDT 24
Finished Jun 29 06:34:18 PM PDT 24
Peak memory 201848 kb
Host smart-0c6b268a-2562-484c-8777-f1cfcb4420fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158209222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_w
ith_pre_cond.2158209222
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.1399527081
Short name T745
Test name
Test status
Simulation time 4824970666 ps
CPU time 1.69 seconds
Started Jun 29 06:31:53 PM PDT 24
Finished Jun 29 06:31:56 PM PDT 24
Peak memory 201564 kb
Host smart-a9e23e2a-53d8-4d29-96ee-3b60b065c35d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399527081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ec_pwr_on_rst.1399527081
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.3195770503
Short name T82
Test name
Test status
Simulation time 2754763636 ps
CPU time 2.3 seconds
Started Jun 29 06:31:47 PM PDT 24
Finished Jun 29 06:31:51 PM PDT 24
Peak memory 201532 kb
Host smart-070050fc-90f6-4096-bd61-2096f346cb05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195770503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_edge_detect.3195770503
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.3905664963
Short name T744
Test name
Test status
Simulation time 2609882016 ps
CPU time 7.23 seconds
Started Jun 29 06:31:53 PM PDT 24
Finished Jun 29 06:32:00 PM PDT 24
Peak memory 201524 kb
Host smart-ebbca961-19cc-437f-9c78-2e5fb34b9c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905664963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.3905664963
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.2333113902
Short name T661
Test name
Test status
Simulation time 2583753676 ps
CPU time 1.14 seconds
Started Jun 29 06:31:53 PM PDT 24
Finished Jun 29 06:31:55 PM PDT 24
Peak memory 201480 kb
Host smart-32906ea9-7b06-4e92-8ff6-1991efe37281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333113902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.2333113902
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.4125375641
Short name T19
Test name
Test status
Simulation time 2139991219 ps
CPU time 6.06 seconds
Started Jun 29 06:31:49 PM PDT 24
Finished Jun 29 06:31:56 PM PDT 24
Peak memory 201464 kb
Host smart-8f7fe393-71e5-43a8-a35e-eb85bd67c6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125375641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.4125375641
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.4032282139
Short name T131
Test name
Test status
Simulation time 2508917128 ps
CPU time 7.12 seconds
Started Jun 29 06:31:49 PM PDT 24
Finished Jun 29 06:31:57 PM PDT 24
Peak memory 201524 kb
Host smart-e97268ea-50bb-436c-9ff5-182339346094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032282139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.4032282139
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.1390105894
Short name T528
Test name
Test status
Simulation time 2113185144 ps
CPU time 6.18 seconds
Started Jun 29 06:31:52 PM PDT 24
Finished Jun 29 06:31:59 PM PDT 24
Peak memory 201452 kb
Host smart-cfd1b6c4-ff11-4fd2-a540-1b51040ae8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390105894 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.1390105894
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.3897641896
Short name T773
Test name
Test status
Simulation time 10250238188 ps
CPU time 20.25 seconds
Started Jun 29 06:31:49 PM PDT 24
Finished Jun 29 06:32:11 PM PDT 24
Peak memory 201608 kb
Host smart-be2150fc-08e2-47db-8c98-15fe98c1607c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897641896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_s
tress_all.3897641896
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.2269582670
Short name T135
Test name
Test status
Simulation time 95983566402 ps
CPU time 61.86 seconds
Started Jun 29 06:31:50 PM PDT 24
Finished Jun 29 06:32:53 PM PDT 24
Peak memory 210236 kb
Host smart-97c524b7-26dd-4241-8d36-9c0962d418bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269582670 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.2269582670
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.4230538241
Short name T681
Test name
Test status
Simulation time 9982166992 ps
CPU time 7.75 seconds
Started Jun 29 06:31:48 PM PDT 24
Finished Jun 29 06:31:57 PM PDT 24
Peak memory 201564 kb
Host smart-72b3e7c5-f4c1-448a-8e1c-3a0ac68f5b0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230538241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.4230538241
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1047818015
Short name T479
Test name
Test status
Simulation time 311252410955 ps
CPU time 195.2 seconds
Started Jun 29 06:31:46 PM PDT 24
Finished Jun 29 06:35:02 PM PDT 24
Peak memory 201668 kb
Host smart-cc426939-f662-4869-acfe-242d69d58d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047818015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.1
047818015
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.204281254
Short name T310
Test name
Test status
Simulation time 164499276829 ps
CPU time 111.24 seconds
Started Jun 29 06:31:50 PM PDT 24
Finished Jun 29 06:33:42 PM PDT 24
Peak memory 201780 kb
Host smart-5bd42d8b-0f06-4184-9b6d-a93d56415a82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204281254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_combo_detect.204281254
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.851022571
Short name T46
Test name
Test status
Simulation time 33407518979 ps
CPU time 56.38 seconds
Started Jun 29 06:31:58 PM PDT 24
Finished Jun 29 06:32:55 PM PDT 24
Peak memory 201800 kb
Host smart-82c7fb75-6917-4568-a5e5-7aa9897c9709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851022571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_wi
th_pre_cond.851022571
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.3554156176
Short name T37
Test name
Test status
Simulation time 6037181602 ps
CPU time 8.63 seconds
Started Jun 29 06:31:53 PM PDT 24
Finished Jun 29 06:32:03 PM PDT 24
Peak memory 201568 kb
Host smart-ec75bfe5-bcd9-4a6d-8035-138d0637a7c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554156176 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_edge_detect.3554156176
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.2872329486
Short name T433
Test name
Test status
Simulation time 2657831194 ps
CPU time 1.67 seconds
Started Jun 29 06:31:50 PM PDT 24
Finished Jun 29 06:31:52 PM PDT 24
Peak memory 201528 kb
Host smart-6c3a5ed6-1d50-4d24-838c-0493d8e42cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872329486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.2872329486
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.167954832
Short name T494
Test name
Test status
Simulation time 2473465130 ps
CPU time 7.55 seconds
Started Jun 29 06:31:49 PM PDT 24
Finished Jun 29 06:31:58 PM PDT 24
Peak memory 201532 kb
Host smart-eca630e2-b103-4cf8-a5db-893d9bf563d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167954832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.167954832
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.3139156351
Short name T601
Test name
Test status
Simulation time 2262082784 ps
CPU time 2.17 seconds
Started Jun 29 06:31:50 PM PDT 24
Finished Jun 29 06:31:53 PM PDT 24
Peak memory 201468 kb
Host smart-b0b914c0-ed79-4ccb-9888-e692517a53fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139156351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.3139156351
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.3946255164
Short name T593
Test name
Test status
Simulation time 2520544414 ps
CPU time 4.87 seconds
Started Jun 29 06:31:47 PM PDT 24
Finished Jun 29 06:31:53 PM PDT 24
Peak memory 201472 kb
Host smart-7147e178-a898-42c4-82db-9762ae3b3875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946255164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.3946255164
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.2994182399
Short name T156
Test name
Test status
Simulation time 2136613239 ps
CPU time 1.82 seconds
Started Jun 29 06:31:46 PM PDT 24
Finished Jun 29 06:31:49 PM PDT 24
Peak memory 201428 kb
Host smart-5cb93717-65a1-4e21-b42c-294fc6eeb354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994182399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.2994182399
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.391999103
Short name T608
Test name
Test status
Simulation time 12650811623 ps
CPU time 9.38 seconds
Started Jun 29 06:31:59 PM PDT 24
Finished Jun 29 06:32:08 PM PDT 24
Peak memory 201556 kb
Host smart-8307bdb9-aecd-4d9c-9354-17cd8fc98f0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391999103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_st
ress_all.391999103
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.1342505466
Short name T18
Test name
Test status
Simulation time 4427733845 ps
CPU time 2.57 seconds
Started Jun 29 06:31:48 PM PDT 24
Finished Jun 29 06:31:52 PM PDT 24
Peak memory 201596 kb
Host smart-165a8e59-400a-4757-a108-3daa88f253be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342505466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ultra_low_pwr.1342505466
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.4013453187
Short name T518
Test name
Test status
Simulation time 2012066461 ps
CPU time 5.67 seconds
Started Jun 29 06:31:58 PM PDT 24
Finished Jun 29 06:32:04 PM PDT 24
Peak memory 201520 kb
Host smart-6d30c65b-af65-4597-b792-3567f88145e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013453187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.4013453187
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.2269622811
Short name T712
Test name
Test status
Simulation time 230569921849 ps
CPU time 556.65 seconds
Started Jun 29 06:31:55 PM PDT 24
Finished Jun 29 06:41:13 PM PDT 24
Peak memory 201620 kb
Host smart-e0091599-7d04-42f2-8837-5a79b3eef693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269622811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.2
269622811
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.71914718
Short name T166
Test name
Test status
Simulation time 93431628856 ps
CPU time 121.75 seconds
Started Jun 29 06:31:59 PM PDT 24
Finished Jun 29 06:34:01 PM PDT 24
Peak memory 201832 kb
Host smart-15ca0ff0-a8cb-48e6-a8ed-e4c8e968e6df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71914718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctr
l_combo_detect.71914718
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.919427762
Short name T172
Test name
Test status
Simulation time 50794889077 ps
CPU time 139.21 seconds
Started Jun 29 06:31:54 PM PDT 24
Finished Jun 29 06:34:14 PM PDT 24
Peak memory 201800 kb
Host smart-de364796-c6ea-46fc-a5d2-0fe4c064120b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919427762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_wi
th_pre_cond.919427762
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.2978477021
Short name T429
Test name
Test status
Simulation time 4744822647 ps
CPU time 11.05 seconds
Started Jun 29 06:31:55 PM PDT 24
Finished Jun 29 06:32:08 PM PDT 24
Peak memory 201556 kb
Host smart-9c335d47-b96f-43cf-a8bc-6017441098c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978477021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ec_pwr_on_rst.2978477021
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.749958863
Short name T153
Test name
Test status
Simulation time 3693923023 ps
CPU time 1.17 seconds
Started Jun 29 06:32:08 PM PDT 24
Finished Jun 29 06:32:09 PM PDT 24
Peak memory 201192 kb
Host smart-d54fa2c7-2d16-4d26-abea-88fb80a289bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749958863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctr
l_edge_detect.749958863
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.3111962605
Short name T658
Test name
Test status
Simulation time 2609588244 ps
CPU time 7.26 seconds
Started Jun 29 06:31:56 PM PDT 24
Finished Jun 29 06:32:05 PM PDT 24
Peak memory 201456 kb
Host smart-42b50a22-ffb6-43f6-b8de-c1f4d24d422d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111962605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.3111962605
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.3359150030
Short name T247
Test name
Test status
Simulation time 2451203269 ps
CPU time 6.27 seconds
Started Jun 29 06:31:53 PM PDT 24
Finished Jun 29 06:32:01 PM PDT 24
Peak memory 201524 kb
Host smart-f3eba7ac-18f2-4050-aa46-53ca56cb7e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359150030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.3359150030
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.777641581
Short name T14
Test name
Test status
Simulation time 2066852447 ps
CPU time 3.46 seconds
Started Jun 29 06:31:54 PM PDT 24
Finished Jun 29 06:31:59 PM PDT 24
Peak memory 201476 kb
Host smart-4cd5f2e0-de66-4009-8fbe-061bd25da5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777641581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.777641581
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.1603927372
Short name T270
Test name
Test status
Simulation time 2512349893 ps
CPU time 6.72 seconds
Started Jun 29 06:31:54 PM PDT 24
Finished Jun 29 06:32:02 PM PDT 24
Peak memory 201472 kb
Host smart-e426deb0-4752-4439-ba87-f3a2c63aef0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603927372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.1603927372
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.3666599918
Short name T476
Test name
Test status
Simulation time 2166403099 ps
CPU time 0.99 seconds
Started Jun 29 06:31:58 PM PDT 24
Finished Jun 29 06:32:00 PM PDT 24
Peak memory 201516 kb
Host smart-6e4aedd5-1c30-400c-bcbd-bff0f6724b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666599918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.3666599918
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.1466595652
Short name T634
Test name
Test status
Simulation time 6885415422 ps
CPU time 5.3 seconds
Started Jun 29 06:31:55 PM PDT 24
Finished Jun 29 06:32:02 PM PDT 24
Peak memory 201588 kb
Host smart-db94f762-5e3d-48c9-9106-29500de5a2bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466595652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.1466595652
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.576589661
Short name T629
Test name
Test status
Simulation time 51016745532 ps
CPU time 69 seconds
Started Jun 29 06:32:08 PM PDT 24
Finished Jun 29 06:33:17 PM PDT 24
Peak memory 210188 kb
Host smart-e8b797d3-1e1d-496e-a6a9-c4da00adae27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576589661 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.576589661
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.409379590
Short name T591
Test name
Test status
Simulation time 10152351703 ps
CPU time 3.99 seconds
Started Jun 29 06:31:56 PM PDT 24
Finished Jun 29 06:32:01 PM PDT 24
Peak memory 201564 kb
Host smart-8208e5a5-3109-4105-9cfa-e25e6fdeda37
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409379590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_ultra_low_pwr.409379590
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.3844542728
Short name T468
Test name
Test status
Simulation time 2026294874 ps
CPU time 2.81 seconds
Started Jun 29 06:32:08 PM PDT 24
Finished Jun 29 06:32:12 PM PDT 24
Peak memory 201504 kb
Host smart-9949a756-2dc0-4a9a-ac5d-c88baef0c1ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844542728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_te
st.3844542728
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.3974648364
Short name T142
Test name
Test status
Simulation time 3712135579 ps
CPU time 2.85 seconds
Started Jun 29 06:31:59 PM PDT 24
Finished Jun 29 06:32:03 PM PDT 24
Peak memory 201508 kb
Host smart-e1af302a-c54d-40a4-b801-6ee7cb75b729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974648364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.3
974648364
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.2442971790
Short name T704
Test name
Test status
Simulation time 97965436066 ps
CPU time 261.8 seconds
Started Jun 29 06:32:05 PM PDT 24
Finished Jun 29 06:36:28 PM PDT 24
Peak memory 201840 kb
Host smart-8822f85c-bcee-4b03-abea-1071567001ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442971790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_combo_detect.2442971790
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.4241247208
Short name T749
Test name
Test status
Simulation time 3467315538 ps
CPU time 8.89 seconds
Started Jun 29 06:32:08 PM PDT 24
Finished Jun 29 06:32:18 PM PDT 24
Peak memory 201492 kb
Host smart-4c5f16ab-ca6c-4b75-a097-10d14c10cffc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241247208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ec_pwr_on_rst.4241247208
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.107600696
Short name T690
Test name
Test status
Simulation time 3636053021 ps
CPU time 8.4 seconds
Started Jun 29 06:32:00 PM PDT 24
Finished Jun 29 06:32:09 PM PDT 24
Peak memory 201476 kb
Host smart-7b2d1671-a17f-4acc-8c07-d1a351e87d2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107600696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctr
l_edge_detect.107600696
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.1250893788
Short name T452
Test name
Test status
Simulation time 2639569025 ps
CPU time 2.36 seconds
Started Jun 29 06:31:59 PM PDT 24
Finished Jun 29 06:32:03 PM PDT 24
Peak memory 201500 kb
Host smart-0fbeca0d-22d2-4f03-9013-d52dfd14f4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250893788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.1250893788
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.908925007
Short name T556
Test name
Test status
Simulation time 2452138771 ps
CPU time 2.71 seconds
Started Jun 29 06:31:54 PM PDT 24
Finished Jun 29 06:31:58 PM PDT 24
Peak memory 201480 kb
Host smart-a001fa1b-9ee7-4d46-903e-d251e19812ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908925007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.908925007
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.3295280142
Short name T281
Test name
Test status
Simulation time 2120976676 ps
CPU time 3.22 seconds
Started Jun 29 06:31:55 PM PDT 24
Finished Jun 29 06:32:00 PM PDT 24
Peak memory 201464 kb
Host smart-ac57e772-a003-411c-993a-764686a3f915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295280142 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.3295280142
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.3763075368
Short name T237
Test name
Test status
Simulation time 2517061698 ps
CPU time 3.75 seconds
Started Jun 29 06:32:08 PM PDT 24
Finished Jun 29 06:32:13 PM PDT 24
Peak memory 201516 kb
Host smart-bc2dc607-249f-4cce-97e2-80d909c9f21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763075368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.3763075368
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.1547074240
Short name T559
Test name
Test status
Simulation time 2108740262 ps
CPU time 6.13 seconds
Started Jun 29 06:31:55 PM PDT 24
Finished Jun 29 06:32:03 PM PDT 24
Peak memory 201452 kb
Host smart-54403276-dd7d-4d0e-b573-2a828a9673ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547074240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.1547074240
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.1922122686
Short name T121
Test name
Test status
Simulation time 137507396725 ps
CPU time 344.68 seconds
Started Jun 29 06:31:56 PM PDT 24
Finished Jun 29 06:37:42 PM PDT 24
Peak memory 201912 kb
Host smart-65c1ac31-7a6d-4e2d-bffe-2b47b00bdb9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922122686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_s
tress_all.1922122686
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.892661440
Short name T592
Test name
Test status
Simulation time 3328820980585 ps
CPU time 164.51 seconds
Started Jun 29 06:31:54 PM PDT 24
Finished Jun 29 06:34:40 PM PDT 24
Peak memory 201552 kb
Host smart-504973a1-b09e-4405-9edf-4742a3c8efab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892661440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_ultra_low_pwr.892661440
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.1360178094
Short name T438
Test name
Test status
Simulation time 2033513406 ps
CPU time 1.89 seconds
Started Jun 29 06:31:55 PM PDT 24
Finished Jun 29 06:31:59 PM PDT 24
Peak memory 201512 kb
Host smart-12710f88-3d9f-4624-917b-f73758fd41cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360178094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_te
st.1360178094
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.3506569086
Short name T706
Test name
Test status
Simulation time 3412766047 ps
CPU time 2.22 seconds
Started Jun 29 06:31:55 PM PDT 24
Finished Jun 29 06:31:59 PM PDT 24
Peak memory 201552 kb
Host smart-2bce21e9-4ab0-46ea-9f31-b997a9e63d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506569086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.3
506569086
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.3514014758
Short name T94
Test name
Test status
Simulation time 51704396101 ps
CPU time 123.81 seconds
Started Jun 29 06:32:08 PM PDT 24
Finished Jun 29 06:34:13 PM PDT 24
Peak memory 201776 kb
Host smart-10f5cffb-58a7-439b-9009-a5aa3fade290
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514014758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_combo_detect.3514014758
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.2141857165
Short name T594
Test name
Test status
Simulation time 2731628013 ps
CPU time 7.78 seconds
Started Jun 29 06:31:55 PM PDT 24
Finished Jun 29 06:32:05 PM PDT 24
Peak memory 201492 kb
Host smart-7b537885-a886-4e67-8763-71b2f51e2c89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141857165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ec_pwr_on_rst.2141857165
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.1751166801
Short name T738
Test name
Test status
Simulation time 3836142549 ps
CPU time 10.33 seconds
Started Jun 29 06:31:55 PM PDT 24
Finished Jun 29 06:32:06 PM PDT 24
Peak memory 201500 kb
Host smart-e786d614-7a14-4414-ae09-eeca6800aa13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751166801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_edge_detect.1751166801
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.479824157
Short name T68
Test name
Test status
Simulation time 2613820397 ps
CPU time 3.84 seconds
Started Jun 29 06:31:55 PM PDT 24
Finished Jun 29 06:32:01 PM PDT 24
Peak memory 201524 kb
Host smart-5e9d3404-f723-4708-97c4-fd12bda131a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479824157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.479824157
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.3252707925
Short name T513
Test name
Test status
Simulation time 2500217413 ps
CPU time 2.01 seconds
Started Jun 29 06:32:05 PM PDT 24
Finished Jun 29 06:32:08 PM PDT 24
Peak memory 201520 kb
Host smart-09bb0859-f472-4ba0-85c9-9326f3fec059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252707925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.3252707925
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.3922385949
Short name T450
Test name
Test status
Simulation time 2184435414 ps
CPU time 5.92 seconds
Started Jun 29 06:31:59 PM PDT 24
Finished Jun 29 06:32:05 PM PDT 24
Peak memory 201516 kb
Host smart-94bd5530-68ab-4678-b08e-6100e6258283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922385949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.3922385949
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.1253091242
Short name T699
Test name
Test status
Simulation time 2535500437 ps
CPU time 2.23 seconds
Started Jun 29 06:32:00 PM PDT 24
Finished Jun 29 06:32:03 PM PDT 24
Peak memory 201404 kb
Host smart-fe113300-e9fa-493d-9699-3ae2a1a05af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253091242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.1253091242
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.2100564258
Short name T223
Test name
Test status
Simulation time 2123642617 ps
CPU time 1.98 seconds
Started Jun 29 06:32:08 PM PDT 24
Finished Jun 29 06:32:11 PM PDT 24
Peak memory 201440 kb
Host smart-c6174d05-03e2-4428-8ed0-969795bc0c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100564258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.2100564258
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.454191625
Short name T232
Test name
Test status
Simulation time 10401462039 ps
CPU time 26.65 seconds
Started Jun 29 06:31:58 PM PDT 24
Finished Jun 29 06:32:26 PM PDT 24
Peak memory 201548 kb
Host smart-73703dca-a5a8-4023-b13c-812075d05ea5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454191625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_st
ress_all.454191625
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.26401568
Short name T239
Test name
Test status
Simulation time 35165358480 ps
CPU time 82.19 seconds
Started Jun 29 06:31:55 PM PDT 24
Finished Jun 29 06:33:18 PM PDT 24
Peak memory 210156 kb
Host smart-e3cbf5eb-228b-45e4-87d7-0b2b5db9b336
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26401568 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.26401568
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.4291693750
Short name T260
Test name
Test status
Simulation time 11448990073 ps
CPU time 3.96 seconds
Started Jun 29 06:31:56 PM PDT 24
Finished Jun 29 06:32:01 PM PDT 24
Peak memory 201548 kb
Host smart-6fb586d4-e049-4ef3-a70c-7fc52a5aaa90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291693750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ultra_low_pwr.4291693750
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.2355502106
Short name T671
Test name
Test status
Simulation time 2013066245 ps
CPU time 3.08 seconds
Started Jun 29 06:32:03 PM PDT 24
Finished Jun 29 06:32:07 PM PDT 24
Peak memory 201512 kb
Host smart-e5ee7bb5-24cb-4629-81be-fa3491cb9484
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355502106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.2355502106
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.3475848186
Short name T733
Test name
Test status
Simulation time 3320754112 ps
CPU time 8.64 seconds
Started Jun 29 06:31:54 PM PDT 24
Finished Jun 29 06:32:04 PM PDT 24
Peak memory 201576 kb
Host smart-5cafefd2-0d08-4f0b-a7d6-e940d0918b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475848186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.3
475848186
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.794596147
Short name T301
Test name
Test status
Simulation time 59602574416 ps
CPU time 162.62 seconds
Started Jun 29 06:31:57 PM PDT 24
Finished Jun 29 06:34:40 PM PDT 24
Peak memory 201768 kb
Host smart-004eecc9-b4ce-4d95-b97b-85d998359c3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794596147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_combo_detect.794596147
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.3363020678
Short name T740
Test name
Test status
Simulation time 115686772415 ps
CPU time 299.09 seconds
Started Jun 29 06:32:07 PM PDT 24
Finished Jun 29 06:37:06 PM PDT 24
Peak memory 201876 kb
Host smart-3c688eb5-e600-4d98-906b-0a13fa8e5e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363020678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_w
ith_pre_cond.3363020678
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.2261819746
Short name T600
Test name
Test status
Simulation time 3575844240 ps
CPU time 1.23 seconds
Started Jun 29 06:32:05 PM PDT 24
Finished Jun 29 06:32:07 PM PDT 24
Peak memory 201496 kb
Host smart-6516dd5a-f429-421b-8680-3145e0746059
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261819746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ec_pwr_on_rst.2261819746
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.2377771723
Short name T548
Test name
Test status
Simulation time 3163149950 ps
CPU time 2.46 seconds
Started Jun 29 06:31:55 PM PDT 24
Finished Jun 29 06:31:59 PM PDT 24
Peak memory 201488 kb
Host smart-3a9eeec1-9250-48d2-b4e4-03dc47e1c667
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377771723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_edge_detect.2377771723
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.3923417820
Short name T474
Test name
Test status
Simulation time 2616809571 ps
CPU time 4.8 seconds
Started Jun 29 06:32:00 PM PDT 24
Finished Jun 29 06:32:05 PM PDT 24
Peak memory 201500 kb
Host smart-e96269e1-5a54-4839-ab3a-35a4cd9ef90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923417820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.3923417820
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.4194848729
Short name T268
Test name
Test status
Simulation time 2463309680 ps
CPU time 7.57 seconds
Started Jun 29 06:31:55 PM PDT 24
Finished Jun 29 06:32:05 PM PDT 24
Peak memory 201532 kb
Host smart-33b34fd9-9e6a-46cc-a64e-116d246c3b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194848729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.4194848729
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.1946826692
Short name T595
Test name
Test status
Simulation time 2215963688 ps
CPU time 6.27 seconds
Started Jun 29 06:31:53 PM PDT 24
Finished Jun 29 06:32:00 PM PDT 24
Peak memory 201520 kb
Host smart-21dd1abe-438f-4eaf-af64-820b7e7ef211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946826692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.1946826692
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.143370581
Short name T209
Test name
Test status
Simulation time 2509979468 ps
CPU time 7.28 seconds
Started Jun 29 06:31:59 PM PDT 24
Finished Jun 29 06:32:07 PM PDT 24
Peak memory 201500 kb
Host smart-37ec9127-3390-4bf3-8ebb-37f5be7771eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143370581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.143370581
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.1760491479
Short name T15
Test name
Test status
Simulation time 2127845690 ps
CPU time 2.04 seconds
Started Jun 29 06:31:55 PM PDT 24
Finished Jun 29 06:31:59 PM PDT 24
Peak memory 201448 kb
Host smart-9be90662-1234-41ba-bba5-5ee1017701d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760491479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.1760491479
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.2715024437
Short name T615
Test name
Test status
Simulation time 12305570572 ps
CPU time 33.65 seconds
Started Jun 29 06:32:05 PM PDT 24
Finished Jun 29 06:32:40 PM PDT 24
Peak memory 201556 kb
Host smart-3414da2f-55e8-45ae-9c53-4f4d77fdc501
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715024437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_s
tress_all.2715024437
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.1610677788
Short name T693
Test name
Test status
Simulation time 4488369690 ps
CPU time 1.36 seconds
Started Jun 29 06:32:00 PM PDT 24
Finished Jun 29 06:32:02 PM PDT 24
Peak memory 201540 kb
Host smart-e545392d-dca0-437d-8acd-f022d78abc64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610677788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ultra_low_pwr.1610677788
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.896828130
Short name T442
Test name
Test status
Simulation time 2011224623 ps
CPU time 5.7 seconds
Started Jun 29 06:32:03 PM PDT 24
Finished Jun 29 06:32:09 PM PDT 24
Peak memory 201444 kb
Host smart-669c8b27-c3c2-49c7-b430-69920597f6be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896828130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_tes
t.896828130
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.2308265688
Short name T780
Test name
Test status
Simulation time 466138778501 ps
CPU time 174.14 seconds
Started Jun 29 06:32:01 PM PDT 24
Finished Jun 29 06:34:56 PM PDT 24
Peak memory 201644 kb
Host smart-e64b834f-33e7-4127-820c-fc4df4c4881d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308265688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.2
308265688
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1404602745
Short name T767
Test name
Test status
Simulation time 27856547672 ps
CPU time 11.95 seconds
Started Jun 29 06:32:08 PM PDT 24
Finished Jun 29 06:32:20 PM PDT 24
Peak memory 201892 kb
Host smart-10e38fd4-e1b9-4474-8b56-5b45015feae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404602745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_w
ith_pre_cond.1404602745
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.2295810061
Short name T197
Test name
Test status
Simulation time 4177333098 ps
CPU time 11.79 seconds
Started Jun 29 06:32:09 PM PDT 24
Finished Jun 29 06:32:22 PM PDT 24
Peak memory 201428 kb
Host smart-4c7b8a40-1d68-49e9-b5ed-12d49506a663
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295810061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ec_pwr_on_rst.2295810061
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.3027127109
Short name T8
Test name
Test status
Simulation time 2752487741 ps
CPU time 1.86 seconds
Started Jun 29 06:32:03 PM PDT 24
Finished Jun 29 06:32:05 PM PDT 24
Peak memory 201496 kb
Host smart-d478a067-07f6-48a7-b558-e3406ba8f2c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027127109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_edge_detect.3027127109
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.3453761264
Short name T244
Test name
Test status
Simulation time 2633532870 ps
CPU time 2.12 seconds
Started Jun 29 06:32:04 PM PDT 24
Finished Jun 29 06:32:07 PM PDT 24
Peak memory 201504 kb
Host smart-a294e050-391d-400e-aa44-cafb7cdc030c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453761264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.3453761264
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.3910749422
Short name T348
Test name
Test status
Simulation time 2448448016 ps
CPU time 6.82 seconds
Started Jun 29 06:32:04 PM PDT 24
Finished Jun 29 06:32:11 PM PDT 24
Peak memory 201520 kb
Host smart-d2321642-be21-47ce-8921-22c1686f4309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910749422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.3910749422
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.2061045929
Short name T694
Test name
Test status
Simulation time 2277041024 ps
CPU time 2.03 seconds
Started Jun 29 06:32:05 PM PDT 24
Finished Jun 29 06:32:07 PM PDT 24
Peak memory 201480 kb
Host smart-2e826fbe-eee8-47eb-9c55-9dc0eafe33a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061045929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.2061045929
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.2433569055
Short name T579
Test name
Test status
Simulation time 2513683852 ps
CPU time 7.28 seconds
Started Jun 29 06:32:05 PM PDT 24
Finished Jun 29 06:32:13 PM PDT 24
Peak memory 201536 kb
Host smart-15e93c7a-add6-465a-803e-2355ce4e244c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433569055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.2433569055
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.517813558
Short name T563
Test name
Test status
Simulation time 2109222310 ps
CPU time 5.75 seconds
Started Jun 29 06:32:04 PM PDT 24
Finished Jun 29 06:32:10 PM PDT 24
Peak memory 201448 kb
Host smart-1f88b985-9495-4485-af74-0c2c8f0db2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517813558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.517813558
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.1721359252
Short name T152
Test name
Test status
Simulation time 182747196120 ps
CPU time 133.58 seconds
Started Jun 29 06:32:09 PM PDT 24
Finished Jun 29 06:34:23 PM PDT 24
Peak memory 201460 kb
Host smart-a0393c0e-7920-46e6-a9ae-4c608504b8d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721359252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_s
tress_all.1721359252
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.4013924610
Short name T356
Test name
Test status
Simulation time 117450964269 ps
CPU time 52.81 seconds
Started Jun 29 06:32:03 PM PDT 24
Finished Jun 29 06:32:56 PM PDT 24
Peak memory 210116 kb
Host smart-66e152fb-ff18-4eab-86f1-abf4400b79b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013924610 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.4013924610
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.598770167
Short name T573
Test name
Test status
Simulation time 2013473881 ps
CPU time 5.47 seconds
Started Jun 29 06:32:09 PM PDT 24
Finished Jun 29 06:32:15 PM PDT 24
Peak memory 201444 kb
Host smart-5cd7c3af-6bcb-44c4-b3b0-c432e4001c8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598770167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_tes
t.598770167
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1089128151
Short name T257
Test name
Test status
Simulation time 3210938881 ps
CPU time 8.34 seconds
Started Jun 29 06:32:08 PM PDT 24
Finished Jun 29 06:32:17 PM PDT 24
Peak memory 201536 kb
Host smart-7b0f3966-6152-47c3-b575-abdbbab33c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089128151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.1
089128151
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.3397638230
Short name T691
Test name
Test status
Simulation time 83958511704 ps
CPU time 56.88 seconds
Started Jun 29 06:32:03 PM PDT 24
Finished Jun 29 06:33:01 PM PDT 24
Peak memory 201784 kb
Host smart-8c267d35-7fea-4dce-9cf9-43fca035cc51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397638230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.3397638230
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.335799480
Short name T755
Test name
Test status
Simulation time 121427473026 ps
CPU time 327.39 seconds
Started Jun 29 06:32:06 PM PDT 24
Finished Jun 29 06:37:34 PM PDT 24
Peak memory 201780 kb
Host smart-8ad59265-64f4-44df-aa6d-f112f080eb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335799480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_wi
th_pre_cond.335799480
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.3335469761
Short name T759
Test name
Test status
Simulation time 4352181693 ps
CPU time 3.59 seconds
Started Jun 29 06:32:07 PM PDT 24
Finished Jun 29 06:32:11 PM PDT 24
Peak memory 201568 kb
Host smart-26ccf338-3570-4084-b183-cd1489d669ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335469761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ec_pwr_on_rst.3335469761
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.1603093553
Short name T38
Test name
Test status
Simulation time 3805305931 ps
CPU time 2.83 seconds
Started Jun 29 06:32:03 PM PDT 24
Finished Jun 29 06:32:07 PM PDT 24
Peak memory 201512 kb
Host smart-44834d36-f431-4b54-87a2-b690258b7284
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603093553 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_edge_detect.1603093553
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.154440954
Short name T457
Test name
Test status
Simulation time 2633465889 ps
CPU time 2.31 seconds
Started Jun 29 06:32:07 PM PDT 24
Finished Jun 29 06:32:10 PM PDT 24
Peak memory 201520 kb
Host smart-cd07a2f6-275a-4d51-8b21-6fbe07d3ea36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154440954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.154440954
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.1742413825
Short name T20
Test name
Test status
Simulation time 2498203102 ps
CPU time 2.44 seconds
Started Jun 29 06:32:06 PM PDT 24
Finished Jun 29 06:32:09 PM PDT 24
Peak memory 201520 kb
Host smart-8ad8b555-1a00-4f8f-aebc-6ef5c68e767a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742413825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.1742413825
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.2487516814
Short name T104
Test name
Test status
Simulation time 2075832759 ps
CPU time 6.1 seconds
Started Jun 29 06:32:02 PM PDT 24
Finished Jun 29 06:32:09 PM PDT 24
Peak memory 201472 kb
Host smart-a269957f-70b0-4601-9643-8b5ad8691c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487516814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.2487516814
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.3262962556
Short name T70
Test name
Test status
Simulation time 2515582027 ps
CPU time 5.46 seconds
Started Jun 29 06:32:04 PM PDT 24
Finished Jun 29 06:32:10 PM PDT 24
Peak memory 201472 kb
Host smart-3abe87f0-c18e-4750-b63b-a680859c92f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262962556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.3262962556
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.4017661979
Short name T427
Test name
Test status
Simulation time 2109799888 ps
CPU time 6.26 seconds
Started Jun 29 06:32:07 PM PDT 24
Finished Jun 29 06:32:14 PM PDT 24
Peak memory 201448 kb
Host smart-4f192beb-2af8-423d-9ca1-be0e68554d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017661979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.4017661979
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.617358631
Short name T184
Test name
Test status
Simulation time 685725502601 ps
CPU time 128.03 seconds
Started Jun 29 06:32:07 PM PDT 24
Finished Jun 29 06:34:15 PM PDT 24
Peak memory 201928 kb
Host smart-b99982bb-33bf-4533-af80-6fd8f741bcfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617358631 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.617358631
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.776612611
Short name T564
Test name
Test status
Simulation time 13184565476 ps
CPU time 4.47 seconds
Started Jun 29 06:32:07 PM PDT 24
Finished Jun 29 06:32:12 PM PDT 24
Peak memory 201556 kb
Host smart-d32f4f3a-8a4e-4dc0-b3ec-de9deb60c8c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776612611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_ultra_low_pwr.776612611
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.2996848565
Short name T659
Test name
Test status
Simulation time 2016781886 ps
CPU time 5.65 seconds
Started Jun 29 06:31:36 PM PDT 24
Finished Jun 29 06:31:42 PM PDT 24
Peak memory 201516 kb
Host smart-1c920944-b001-4c2e-988f-0f289e2f0353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996848565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.2996848565
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.189256700
Short name T495
Test name
Test status
Simulation time 3202534544 ps
CPU time 1.96 seconds
Started Jun 29 06:31:23 PM PDT 24
Finished Jun 29 06:31:25 PM PDT 24
Peak memory 201540 kb
Host smart-ca7ea5c8-81e6-49a9-b833-8830eaf3bebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189256700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.189256700
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.3825357733
Short name T144
Test name
Test status
Simulation time 150961101439 ps
CPU time 198.5 seconds
Started Jun 29 06:31:22 PM PDT 24
Finished Jun 29 06:34:41 PM PDT 24
Peak memory 201756 kb
Host smart-61cb64a2-d392-4b6d-aeb1-7422fe3178cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825357733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_combo_detect.3825357733
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.2216284863
Short name T454
Test name
Test status
Simulation time 2417102258 ps
CPU time 5.43 seconds
Started Jun 29 06:31:26 PM PDT 24
Finished Jun 29 06:31:32 PM PDT 24
Peak memory 201516 kb
Host smart-70d844f7-78e5-4610-a585-4db1163bad51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216284863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.2216284863
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3608752024
Short name T311
Test name
Test status
Simulation time 2324022233 ps
CPU time 2.17 seconds
Started Jun 29 06:31:27 PM PDT 24
Finished Jun 29 06:31:30 PM PDT 24
Peak memory 201516 kb
Host smart-2fb6be19-5b47-46d4-922e-285da07b7ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608752024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3608752024
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.951034903
Short name T770
Test name
Test status
Simulation time 2935408267 ps
CPU time 4.59 seconds
Started Jun 29 06:31:26 PM PDT 24
Finished Jun 29 06:31:32 PM PDT 24
Peak memory 201488 kb
Host smart-52e50247-6bf8-4f9e-9c43-106dadcb7205
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951034903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_ec_pwr_on_rst.951034903
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.2289009732
Short name T757
Test name
Test status
Simulation time 2616857967 ps
CPU time 4.02 seconds
Started Jun 29 06:31:25 PM PDT 24
Finished Jun 29 06:31:30 PM PDT 24
Peak memory 201524 kb
Host smart-10eaa297-0fa5-4d3f-836e-20c213006611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289009732 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.2289009732
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.2303672516
Short name T638
Test name
Test status
Simulation time 2437441650 ps
CPU time 7.77 seconds
Started Jun 29 06:31:26 PM PDT 24
Finished Jun 29 06:31:35 PM PDT 24
Peak memory 201512 kb
Host smart-d9615571-fb4d-468c-87bb-fbbc7e785b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303672516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.2303672516
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.3581642654
Short name T421
Test name
Test status
Simulation time 2118053654 ps
CPU time 3.06 seconds
Started Jun 29 06:31:25 PM PDT 24
Finished Jun 29 06:31:28 PM PDT 24
Peak memory 201472 kb
Host smart-330811a5-7f89-4f97-9599-afa25fc1c3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581642654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.3581642654
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.3933351942
Short name T488
Test name
Test status
Simulation time 2507541346 ps
CPU time 7.11 seconds
Started Jun 29 06:31:26 PM PDT 24
Finished Jun 29 06:31:34 PM PDT 24
Peak memory 201516 kb
Host smart-daba6095-0fb4-4df0-87fb-0f631344fdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933351942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.3933351942
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.937412994
Short name T336
Test name
Test status
Simulation time 22056328956 ps
CPU time 27.03 seconds
Started Jun 29 06:31:33 PM PDT 24
Finished Jun 29 06:32:00 PM PDT 24
Peak memory 221124 kb
Host smart-842d5071-f89e-4f49-8485-14abd148b631
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937412994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.937412994
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.2531005196
Short name T453
Test name
Test status
Simulation time 2122349920 ps
CPU time 3.17 seconds
Started Jun 29 06:31:26 PM PDT 24
Finished Jun 29 06:31:30 PM PDT 24
Peak memory 201444 kb
Host smart-4a90944c-2b33-4001-a0e2-43a002102e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531005196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.2531005196
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.587773574
Short name T26
Test name
Test status
Simulation time 8898329432 ps
CPU time 3.46 seconds
Started Jun 29 06:31:34 PM PDT 24
Finished Jun 29 06:31:38 PM PDT 24
Peak memory 201524 kb
Host smart-02b1422e-61ec-4e42-b0fa-1e832aae3337
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587773574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_str
ess_all.587773574
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.3430841861
Short name T581
Test name
Test status
Simulation time 5672783157 ps
CPU time 3.99 seconds
Started Jun 29 06:31:23 PM PDT 24
Finished Jun 29 06:31:28 PM PDT 24
Peak memory 201592 kb
Host smart-d7ae10c4-7b61-46ff-8832-47f5256968e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430841861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ultra_low_pwr.3430841861
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.2250147589
Short name T139
Test name
Test status
Simulation time 2016253841 ps
CPU time 3.24 seconds
Started Jun 29 06:32:12 PM PDT 24
Finished Jun 29 06:32:15 PM PDT 24
Peak memory 201504 kb
Host smart-c1548ce1-249e-4ce4-adf2-b919f1f79c2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250147589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.2250147589
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.548352447
Short name T485
Test name
Test status
Simulation time 248368094438 ps
CPU time 266.5 seconds
Started Jun 29 06:32:06 PM PDT 24
Finished Jun 29 06:36:33 PM PDT 24
Peak memory 201644 kb
Host smart-cf7e474d-fed9-406c-a75f-ee94a716fc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548352447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.548352447
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.1863706717
Short name T233
Test name
Test status
Simulation time 101459595292 ps
CPU time 60.37 seconds
Started Jun 29 06:32:07 PM PDT 24
Finished Jun 29 06:33:08 PM PDT 24
Peak memory 201824 kb
Host smart-add9136b-b68a-4e4a-b23f-d22136df14fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863706717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_combo_detect.1863706717
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.178364038
Short name T285
Test name
Test status
Simulation time 26078918235 ps
CPU time 70.02 seconds
Started Jun 29 06:32:11 PM PDT 24
Finished Jun 29 06:33:22 PM PDT 24
Peak memory 201852 kb
Host smart-76b1c73a-673c-4c18-8744-e45e0f662f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178364038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_wi
th_pre_cond.178364038
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3191340197
Short name T279
Test name
Test status
Simulation time 3981418967 ps
CPU time 3.37 seconds
Started Jun 29 06:32:07 PM PDT 24
Finished Jun 29 06:32:11 PM PDT 24
Peak memory 201516 kb
Host smart-e1db48c3-ac3a-426f-924e-898816f62a99
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191340197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.3191340197
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.3099325503
Short name T766
Test name
Test status
Simulation time 2677327930 ps
CPU time 2.04 seconds
Started Jun 29 06:32:09 PM PDT 24
Finished Jun 29 06:32:12 PM PDT 24
Peak memory 201428 kb
Host smart-23fa47ee-65ac-41c3-9079-65324cc2b6d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099325503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_edge_detect.3099325503
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.302968746
Short name T586
Test name
Test status
Simulation time 2620037492 ps
CPU time 4.17 seconds
Started Jun 29 06:32:06 PM PDT 24
Finished Jun 29 06:32:10 PM PDT 24
Peak memory 201364 kb
Host smart-ffb51288-5574-4a4b-9087-42bee393ce26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302968746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.302968746
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.3328060498
Short name T580
Test name
Test status
Simulation time 2461265869 ps
CPU time 4.18 seconds
Started Jun 29 06:32:08 PM PDT 24
Finished Jun 29 06:32:13 PM PDT 24
Peak memory 201484 kb
Host smart-23b2f085-1a58-4a54-83af-5770ba9e91b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328060498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.3328060498
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.1600869819
Short name T695
Test name
Test status
Simulation time 2184722274 ps
CPU time 6.82 seconds
Started Jun 29 06:32:05 PM PDT 24
Finished Jun 29 06:32:13 PM PDT 24
Peak memory 201532 kb
Host smart-8e0a45ca-36ce-4cd6-aa61-c551d171be29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600869819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.1600869819
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.476478088
Short name T352
Test name
Test status
Simulation time 2531669351 ps
CPU time 2.46 seconds
Started Jun 29 06:32:06 PM PDT 24
Finished Jun 29 06:32:09 PM PDT 24
Peak memory 201524 kb
Host smart-1f3d794e-6293-4b97-bb3f-7f978232404f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476478088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.476478088
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.1891737608
Short name T636
Test name
Test status
Simulation time 2112861131 ps
CPU time 3.36 seconds
Started Jun 29 06:32:09 PM PDT 24
Finished Jun 29 06:32:13 PM PDT 24
Peak memory 201352 kb
Host smart-11a251de-9c96-4a3c-9908-08c39a7c26ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891737608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.1891737608
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.768815440
Short name T458
Test name
Test status
Simulation time 100694861692 ps
CPU time 272.67 seconds
Started Jun 29 06:32:11 PM PDT 24
Finished Jun 29 06:36:44 PM PDT 24
Peak memory 201620 kb
Host smart-72239284-b707-4663-9c68-2fa2cc179e69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768815440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_st
ress_all.768815440
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.566569549
Short name T78
Test name
Test status
Simulation time 3860454744 ps
CPU time 1.54 seconds
Started Jun 29 06:32:05 PM PDT 24
Finished Jun 29 06:32:07 PM PDT 24
Peak memory 201532 kb
Host smart-24948c86-ebf8-41b8-8400-4a6e9dafdbe6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566569549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_ultra_low_pwr.566569549
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.3120846546
Short name T747
Test name
Test status
Simulation time 2015872926 ps
CPU time 3.15 seconds
Started Jun 29 06:32:13 PM PDT 24
Finished Jun 29 06:32:16 PM PDT 24
Peak memory 201524 kb
Host smart-20f2e0be-f39d-404f-9603-80787f12b175
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120846546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_te
st.3120846546
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.751303193
Short name T338
Test name
Test status
Simulation time 209789298080 ps
CPU time 80.27 seconds
Started Jun 29 06:32:11 PM PDT 24
Finished Jun 29 06:33:31 PM PDT 24
Peak memory 201664 kb
Host smart-445d51f8-ce87-4eec-983d-d59db3dbe130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751303193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.751303193
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2187890177
Short name T225
Test name
Test status
Simulation time 2950342915 ps
CPU time 7.84 seconds
Started Jun 29 06:32:15 PM PDT 24
Finished Jun 29 06:32:23 PM PDT 24
Peak memory 201500 kb
Host smart-b756358f-d990-41e2-bfb5-804dc54c7873
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187890177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ec_pwr_on_rst.2187890177
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.56315669
Short name T251
Test name
Test status
Simulation time 3871164614 ps
CPU time 1.33 seconds
Started Jun 29 06:32:14 PM PDT 24
Finished Jun 29 06:32:16 PM PDT 24
Peak memory 201496 kb
Host smart-52606cfe-a93d-44fc-84d7-3002a16e9f45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56315669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl
_edge_detect.56315669
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.3014502014
Short name T508
Test name
Test status
Simulation time 2719560018 ps
CPU time 1.02 seconds
Started Jun 29 06:32:14 PM PDT 24
Finished Jun 29 06:32:16 PM PDT 24
Peak memory 201524 kb
Host smart-8a1d494a-cdc6-4125-b93f-d9b007395523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014502014 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.3014502014
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.1433709765
Short name T66
Test name
Test status
Simulation time 2440134042 ps
CPU time 6.94 seconds
Started Jun 29 06:32:09 PM PDT 24
Finished Jun 29 06:32:17 PM PDT 24
Peak memory 201532 kb
Host smart-c7a4cd6d-f5f1-4c59-a799-9b6e95d6dfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433709765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.1433709765
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.2503062009
Short name T606
Test name
Test status
Simulation time 2137872444 ps
CPU time 2.01 seconds
Started Jun 29 06:32:10 PM PDT 24
Finished Jun 29 06:32:12 PM PDT 24
Peak memory 201440 kb
Host smart-b7043027-c319-4a8f-84f8-dfcc11e369a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503062009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.2503062009
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.3293890074
Short name T138
Test name
Test status
Simulation time 2511773342 ps
CPU time 7.43 seconds
Started Jun 29 06:32:10 PM PDT 24
Finished Jun 29 06:32:18 PM PDT 24
Peak memory 201516 kb
Host smart-14ba786b-dd34-433d-abc8-5372e8310966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293890074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.3293890074
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.350079209
Short name T515
Test name
Test status
Simulation time 2191861681 ps
CPU time 1.09 seconds
Started Jun 29 06:32:16 PM PDT 24
Finished Jun 29 06:32:18 PM PDT 24
Peak memory 201480 kb
Host smart-473662f3-7e5c-4866-9052-6dde9aaad9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350079209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.350079209
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.1046597574
Short name T524
Test name
Test status
Simulation time 9709073736 ps
CPU time 6.89 seconds
Started Jun 29 06:32:15 PM PDT 24
Finished Jun 29 06:32:22 PM PDT 24
Peak memory 201524 kb
Host smart-2ea43168-9f49-4e56-88b1-d8e790027541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046597574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s
tress_all.1046597574
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2272246559
Short name T342
Test name
Test status
Simulation time 75669657664 ps
CPU time 22.87 seconds
Started Jun 29 06:32:10 PM PDT 24
Finished Jun 29 06:32:33 PM PDT 24
Peak memory 210112 kb
Host smart-07993a91-5e5e-4b82-b401-6af9c2a40272
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272246559 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.2272246559
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.330906562
Short name T89
Test name
Test status
Simulation time 5263764769 ps
CPU time 2.15 seconds
Started Jun 29 06:32:12 PM PDT 24
Finished Jun 29 06:32:15 PM PDT 24
Peak memory 201560 kb
Host smart-83fc13ad-afc2-485e-8db4-a1f6649755fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330906562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_ultra_low_pwr.330906562
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.667459579
Short name T610
Test name
Test status
Simulation time 2015390323 ps
CPU time 4.51 seconds
Started Jun 29 06:32:11 PM PDT 24
Finished Jun 29 06:32:16 PM PDT 24
Peak memory 201408 kb
Host smart-cef1eb04-a10c-47a1-b312-97e5c560a71f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667459579 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_tes
t.667459579
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.3809431918
Short name T52
Test name
Test status
Simulation time 3134297502 ps
CPU time 4.64 seconds
Started Jun 29 06:32:15 PM PDT 24
Finished Jun 29 06:32:20 PM PDT 24
Peak memory 201560 kb
Host smart-e179b4e4-8514-4aa8-be62-70af3b6756a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809431918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.3
809431918
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.4086418584
Short name T622
Test name
Test status
Simulation time 67849103378 ps
CPU time 37.84 seconds
Started Jun 29 06:32:15 PM PDT 24
Finished Jun 29 06:32:53 PM PDT 24
Peak memory 201820 kb
Host smart-1b6d6b54-f2b0-4fb8-9005-fe7054e9658e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086418584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_w
ith_pre_cond.4086418584
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.1567832552
Short name T496
Test name
Test status
Simulation time 2820674808 ps
CPU time 2.18 seconds
Started Jun 29 06:32:14 PM PDT 24
Finished Jun 29 06:32:16 PM PDT 24
Peak memory 201432 kb
Host smart-de8c66dd-f4f5-4e5a-b9a0-3183824da369
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567832552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ec_pwr_on_rst.1567832552
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.3682748695
Short name T598
Test name
Test status
Simulation time 3222885792 ps
CPU time 3.43 seconds
Started Jun 29 06:32:12 PM PDT 24
Finished Jun 29 06:32:16 PM PDT 24
Peak memory 201492 kb
Host smart-ca7574f9-2cb0-40c9-bed6-9e9f670579a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682748695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_edge_detect.3682748695
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.2445788178
Short name T590
Test name
Test status
Simulation time 2613971113 ps
CPU time 7.65 seconds
Started Jun 29 06:32:14 PM PDT 24
Finished Jun 29 06:32:22 PM PDT 24
Peak memory 200744 kb
Host smart-6726d461-3318-49f0-ba10-06cc3fa1f278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445788178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.2445788178
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.4248878603
Short name T645
Test name
Test status
Simulation time 2466813917 ps
CPU time 7.39 seconds
Started Jun 29 06:32:10 PM PDT 24
Finished Jun 29 06:32:18 PM PDT 24
Peak memory 201524 kb
Host smart-8da5567c-03d7-43a6-8705-b3a7aa37c577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248878603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.4248878603
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.1119724689
Short name T511
Test name
Test status
Simulation time 2178694631 ps
CPU time 6.34 seconds
Started Jun 29 06:32:12 PM PDT 24
Finished Jun 29 06:32:18 PM PDT 24
Peak memory 201452 kb
Host smart-5e4f022a-5015-461b-9bec-d59ce578edf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119724689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.1119724689
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.739358236
Short name T71
Test name
Test status
Simulation time 2510690565 ps
CPU time 5.87 seconds
Started Jun 29 06:32:14 PM PDT 24
Finished Jun 29 06:32:21 PM PDT 24
Peak memory 201744 kb
Host smart-d5022dd3-1709-46f6-be3c-58843b29f5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739358236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.739358236
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.4188935285
Short name T175
Test name
Test status
Simulation time 2161747699 ps
CPU time 1.11 seconds
Started Jun 29 06:32:10 PM PDT 24
Finished Jun 29 06:32:12 PM PDT 24
Peak memory 201512 kb
Host smart-9fd2a04e-2d32-48c3-8b43-1afadf21521f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188935285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.4188935285
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.781156825
Short name T65
Test name
Test status
Simulation time 7103621166 ps
CPU time 5.68 seconds
Started Jun 29 06:32:16 PM PDT 24
Finished Jun 29 06:32:22 PM PDT 24
Peak memory 201780 kb
Host smart-fca62cd8-ea57-4dfb-ba21-e720ca5f1f4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781156825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_st
ress_all.781156825
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3191793830
Short name T639
Test name
Test status
Simulation time 5726653194 ps
CPU time 7.08 seconds
Started Jun 29 06:32:12 PM PDT 24
Finished Jun 29 06:32:20 PM PDT 24
Peak memory 201556 kb
Host smart-92a69aae-8646-4f59-bc49-2cd0601eab0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191793830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.3191793830
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.1014705721
Short name T774
Test name
Test status
Simulation time 2035001877 ps
CPU time 2.01 seconds
Started Jun 29 06:32:17 PM PDT 24
Finished Jun 29 06:32:20 PM PDT 24
Peak memory 201504 kb
Host smart-1e898700-62b6-4578-aebc-79e8e5a724bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014705721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te
st.1014705721
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.704015531
Short name T727
Test name
Test status
Simulation time 3559813341 ps
CPU time 9.64 seconds
Started Jun 29 06:32:12 PM PDT 24
Finished Jun 29 06:32:22 PM PDT 24
Peak memory 201604 kb
Host smart-31d648f7-c345-4db0-840e-08d910a380a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704015531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.704015531
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.3426767884
Short name T292
Test name
Test status
Simulation time 107930441065 ps
CPU time 52.69 seconds
Started Jun 29 06:32:16 PM PDT 24
Finished Jun 29 06:33:09 PM PDT 24
Peak memory 202068 kb
Host smart-b16504ff-6122-4386-9306-a83df7d18997
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426767884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_combo_detect.3426767884
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.4049823025
Short name T461
Test name
Test status
Simulation time 26356301320 ps
CPU time 16.45 seconds
Started Jun 29 06:32:14 PM PDT 24
Finished Jun 29 06:32:31 PM PDT 24
Peak memory 201164 kb
Host smart-51232dbf-ab59-4d73-a420-5151ddb0b618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049823025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_w
ith_pre_cond.4049823025
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.2256509987
Short name T414
Test name
Test status
Simulation time 1337945447544 ps
CPU time 1776.5 seconds
Started Jun 29 06:32:12 PM PDT 24
Finished Jun 29 07:01:49 PM PDT 24
Peak memory 201488 kb
Host smart-198977af-0c0d-4d01-b43d-2301b0dad2b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256509987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ec_pwr_on_rst.2256509987
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.2191726192
Short name T241
Test name
Test status
Simulation time 4082590495 ps
CPU time 3.15 seconds
Started Jun 29 06:32:11 PM PDT 24
Finished Jun 29 06:32:15 PM PDT 24
Peak memory 201444 kb
Host smart-09f97f7c-a6f3-4d0a-b921-50054a8e2b31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191726192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_edge_detect.2191726192
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.1218227944
Short name T666
Test name
Test status
Simulation time 2627844988 ps
CPU time 2.26 seconds
Started Jun 29 06:32:18 PM PDT 24
Finished Jun 29 06:32:20 PM PDT 24
Peak memory 201512 kb
Host smart-85b15402-8065-4041-885d-4e4d2df97645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218227944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.1218227944
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.2752041813
Short name T576
Test name
Test status
Simulation time 2455800464 ps
CPU time 6.81 seconds
Started Jun 29 06:32:12 PM PDT 24
Finished Jun 29 06:32:19 PM PDT 24
Peak memory 201520 kb
Host smart-5da7df45-1eae-403e-9d6c-5d1ec561b23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752041813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.2752041813
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.1996199138
Short name T436
Test name
Test status
Simulation time 2159740044 ps
CPU time 1.95 seconds
Started Jun 29 06:32:10 PM PDT 24
Finished Jun 29 06:32:12 PM PDT 24
Peak memory 201468 kb
Host smart-dbaf0f4e-faee-4037-875c-5366621dddb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996199138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.1996199138
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.4113392047
Short name T464
Test name
Test status
Simulation time 2530893304 ps
CPU time 2.47 seconds
Started Jun 29 06:32:10 PM PDT 24
Finished Jun 29 06:32:13 PM PDT 24
Peak memory 201516 kb
Host smart-30edccb8-f81f-4146-a960-2027b56b8b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113392047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.4113392047
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.4247384517
Short name T246
Test name
Test status
Simulation time 2107417410 ps
CPU time 5.9 seconds
Started Jun 29 06:32:14 PM PDT 24
Finished Jun 29 06:32:20 PM PDT 24
Peak memory 201380 kb
Host smart-3bb229c1-c721-4b6d-bdde-aa0484d3284a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247384517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.4247384517
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.3050668962
Short name T160
Test name
Test status
Simulation time 6291721001 ps
CPU time 15.43 seconds
Started Jun 29 06:32:19 PM PDT 24
Finished Jun 29 06:32:36 PM PDT 24
Peak memory 201488 kb
Host smart-059a3b05-187c-449c-91b7-05b6eec893ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050668962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.3050668962
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.1589371775
Short name T122
Test name
Test status
Simulation time 37942622323 ps
CPU time 14.25 seconds
Started Jun 29 06:32:18 PM PDT 24
Finished Jun 29 06:32:33 PM PDT 24
Peak memory 218400 kb
Host smart-12905521-c566-4b0f-abd1-470a2e3b7d08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589371775 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.1589371775
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.2609253839
Short name T12
Test name
Test status
Simulation time 5274759586 ps
CPU time 2.07 seconds
Started Jun 29 06:32:11 PM PDT 24
Finished Jun 29 06:32:14 PM PDT 24
Peak memory 201568 kb
Host smart-cf836e13-5186-4c03-8723-6e69b4e53f59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609253839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ultra_low_pwr.2609253839
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.1832151746
Short name T534
Test name
Test status
Simulation time 2061654664 ps
CPU time 1.3 seconds
Started Jun 29 06:32:24 PM PDT 24
Finished Jun 29 06:32:25 PM PDT 24
Peak memory 201504 kb
Host smart-c1677550-ffcb-4335-b3d6-ca3b317d3221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832151746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_te
st.1832151746
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.2562268021
Short name T426
Test name
Test status
Simulation time 3541666885 ps
CPU time 3.54 seconds
Started Jun 29 06:32:24 PM PDT 24
Finished Jun 29 06:32:28 PM PDT 24
Peak memory 201576 kb
Host smart-75e3cc84-8987-4fdc-8369-d7f867c45afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562268021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.2
562268021
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.2229609364
Short name T300
Test name
Test status
Simulation time 76956902139 ps
CPU time 46.05 seconds
Started Jun 29 06:32:18 PM PDT 24
Finished Jun 29 06:33:04 PM PDT 24
Peak memory 201836 kb
Host smart-8b720473-98a9-49b4-a87a-a30d065fef3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229609364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_combo_detect.2229609364
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.2605432897
Short name T405
Test name
Test status
Simulation time 60173807354 ps
CPU time 42.28 seconds
Started Jun 29 06:32:21 PM PDT 24
Finished Jun 29 06:33:03 PM PDT 24
Peak memory 201872 kb
Host smart-e95476cb-03af-4fb6-80fe-1efdb8ef280d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605432897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w
ith_pre_cond.2605432897
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.3105255499
Short name T719
Test name
Test status
Simulation time 4214838226 ps
CPU time 10.56 seconds
Started Jun 29 06:32:19 PM PDT 24
Finished Jun 29 06:32:31 PM PDT 24
Peak memory 201444 kb
Host smart-67691114-712c-49cc-944e-0dd1a19b99d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105255499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ec_pwr_on_rst.3105255499
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.731125435
Short name T42
Test name
Test status
Simulation time 4197396280 ps
CPU time 10.02 seconds
Started Jun 29 06:32:20 PM PDT 24
Finished Jun 29 06:32:31 PM PDT 24
Peak memory 201500 kb
Host smart-4eea2a7d-f553-4fb3-a9f6-052382971ffc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731125435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctr
l_edge_detect.731125435
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.903859624
Short name T707
Test name
Test status
Simulation time 2613587025 ps
CPU time 5.5 seconds
Started Jun 29 06:32:23 PM PDT 24
Finished Jun 29 06:32:29 PM PDT 24
Peak memory 201532 kb
Host smart-89c9abc2-4005-46b2-bf8e-ba91c65fd780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903859624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.903859624
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.2602217372
Short name T63
Test name
Test status
Simulation time 2548415282 ps
CPU time 1.17 seconds
Started Jun 29 06:32:24 PM PDT 24
Finished Jun 29 06:32:25 PM PDT 24
Peak memory 201516 kb
Host smart-cc481620-6b4f-4ede-b8b3-c1e91bb89c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602217372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.2602217372
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.1414872088
Short name T188
Test name
Test status
Simulation time 2050234612 ps
CPU time 1.88 seconds
Started Jun 29 06:32:20 PM PDT 24
Finished Jun 29 06:32:23 PM PDT 24
Peak memory 201444 kb
Host smart-221967f3-1da7-4918-8e14-1d596f8ed9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414872088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.1414872088
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.2747684349
Short name T473
Test name
Test status
Simulation time 2521053438 ps
CPU time 2.46 seconds
Started Jun 29 06:32:21 PM PDT 24
Finished Jun 29 06:32:24 PM PDT 24
Peak memory 201512 kb
Host smart-1c515245-d84e-4067-944d-cab74dfe0bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747684349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.2747684349
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.289774842
Short name T472
Test name
Test status
Simulation time 2108512780 ps
CPU time 5.64 seconds
Started Jun 29 06:32:22 PM PDT 24
Finished Jun 29 06:32:28 PM PDT 24
Peak memory 201436 kb
Host smart-fd5c2ef0-225f-4cd0-96bc-9396a3868096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289774842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.289774842
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.1672864059
Short name T306
Test name
Test status
Simulation time 151869525757 ps
CPU time 99.25 seconds
Started Jun 29 06:32:19 PM PDT 24
Finished Jun 29 06:33:58 PM PDT 24
Peak memory 201760 kb
Host smart-8dec4ca2-fa95-4edc-8a73-eef62df6fb0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672864059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_s
tress_all.1672864059
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.3467623846
Short name T539
Test name
Test status
Simulation time 2734826816 ps
CPU time 1.29 seconds
Started Jun 29 06:32:19 PM PDT 24
Finished Jun 29 06:32:20 PM PDT 24
Peak memory 201528 kb
Host smart-ca5c6f82-6592-4393-a02d-a8b5cf20add1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467623846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.3467623846
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.3458294520
Short name T17
Test name
Test status
Simulation time 2027622527 ps
CPU time 1.94 seconds
Started Jun 29 06:32:19 PM PDT 24
Finished Jun 29 06:32:22 PM PDT 24
Peak memory 201500 kb
Host smart-ffe03442-9eb7-4d68-9ea7-b3ee2b5568df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458294520 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te
st.3458294520
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1060031571
Short name T575
Test name
Test status
Simulation time 4107073487 ps
CPU time 3.35 seconds
Started Jun 29 06:32:20 PM PDT 24
Finished Jun 29 06:32:24 PM PDT 24
Peak memory 201612 kb
Host smart-57f31865-e34f-407c-94dc-da352ccfc9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060031571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.1
060031571
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.1716755529
Short name T91
Test name
Test status
Simulation time 136912758500 ps
CPU time 84.35 seconds
Started Jun 29 06:32:19 PM PDT 24
Finished Jun 29 06:33:44 PM PDT 24
Peak memory 201744 kb
Host smart-0d6b3295-7e16-435d-961c-463234bcc831
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716755529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.1716755529
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.434074573
Short name T535
Test name
Test status
Simulation time 3581597097 ps
CPU time 9.66 seconds
Started Jun 29 06:32:20 PM PDT 24
Finished Jun 29 06:32:30 PM PDT 24
Peak memory 201424 kb
Host smart-e8aec152-8e18-4ac5-b4d5-fda3ec3aace1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434074573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_ec_pwr_on_rst.434074573
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3425557016
Short name T723
Test name
Test status
Simulation time 2612781859 ps
CPU time 3.99 seconds
Started Jun 29 06:32:19 PM PDT 24
Finished Jun 29 06:32:24 PM PDT 24
Peak memory 201520 kb
Host smart-7fd47d62-90cd-4c9e-abd3-5a678655fa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425557016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.3425557016
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.4176168867
Short name T346
Test name
Test status
Simulation time 2475964878 ps
CPU time 4.69 seconds
Started Jun 29 06:32:18 PM PDT 24
Finished Jun 29 06:32:23 PM PDT 24
Peak memory 201520 kb
Host smart-f865ffd2-8214-4f80-aef9-1457d8c5c683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176168867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.4176168867
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.2873465070
Short name T660
Test name
Test status
Simulation time 2238173588 ps
CPU time 3.63 seconds
Started Jun 29 06:32:18 PM PDT 24
Finished Jun 29 06:32:22 PM PDT 24
Peak memory 201520 kb
Host smart-f65079f1-0c2e-4769-87b2-f84ffd1bdcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873465070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.2873465070
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.4164341252
Short name T273
Test name
Test status
Simulation time 2522708336 ps
CPU time 3.56 seconds
Started Jun 29 06:32:19 PM PDT 24
Finished Jun 29 06:32:23 PM PDT 24
Peak memory 201524 kb
Host smart-9a85bcb0-01e5-46ed-86ff-8e6a91ce579c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164341252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.4164341252
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.298891784
Short name T678
Test name
Test status
Simulation time 2137768598 ps
CPU time 1.91 seconds
Started Jun 29 06:32:20 PM PDT 24
Finished Jun 29 06:32:23 PM PDT 24
Peak memory 201464 kb
Host smart-c889ee72-46e7-4358-ab7f-9afdab26ef04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298891784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.298891784
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.3289891840
Short name T684
Test name
Test status
Simulation time 8151368240 ps
CPU time 22.44 seconds
Started Jun 29 06:32:21 PM PDT 24
Finished Jun 29 06:32:44 PM PDT 24
Peak memory 201608 kb
Host smart-b2197bdf-f946-4fab-b496-1b2acec12def
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289891840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.3289891840
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.3163996262
Short name T148
Test name
Test status
Simulation time 2092644750234 ps
CPU time 53.23 seconds
Started Jun 29 06:32:20 PM PDT 24
Finished Jun 29 06:33:14 PM PDT 24
Peak memory 201560 kb
Host smart-c49aeb37-6b99-4f4e-bf34-c27c41e4f90e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163996262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ultra_low_pwr.3163996262
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.1846159786
Short name T739
Test name
Test status
Simulation time 2010089639 ps
CPU time 6.04 seconds
Started Jun 29 06:32:31 PM PDT 24
Finished Jun 29 06:32:37 PM PDT 24
Peak memory 201504 kb
Host smart-440521d5-9e83-4408-b3a7-ca34d0dca903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846159786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.1846159786
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.4089036618
Short name T102
Test name
Test status
Simulation time 3724773599 ps
CPU time 9.96 seconds
Started Jun 29 06:32:24 PM PDT 24
Finished Jun 29 06:32:34 PM PDT 24
Peak memory 201608 kb
Host smart-0ef80c0b-0df7-4109-a799-241388214e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089036618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.4
089036618
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.4116929207
Short name T95
Test name
Test status
Simulation time 98695605862 ps
CPU time 240.11 seconds
Started Jun 29 06:32:17 PM PDT 24
Finished Jun 29 06:36:18 PM PDT 24
Peak memory 201772 kb
Host smart-66f3b561-7c74-41f1-9b5d-2261c55f1565
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116929207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_combo_detect.4116929207
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.1497867036
Short name T765
Test name
Test status
Simulation time 26096691753 ps
CPU time 14.13 seconds
Started Jun 29 06:32:28 PM PDT 24
Finished Jun 29 06:32:43 PM PDT 24
Peak memory 201844 kb
Host smart-8baf158e-01bd-4045-bf18-3dbac9ac3f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497867036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w
ith_pre_cond.1497867036
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2358524184
Short name T158
Test name
Test status
Simulation time 3446352516 ps
CPU time 5.19 seconds
Started Jun 29 06:32:19 PM PDT 24
Finished Jun 29 06:32:25 PM PDT 24
Peak memory 201496 kb
Host smart-8dff0bd6-370d-4496-8188-b7121296ae4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358524184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ec_pwr_on_rst.2358524184
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.2437566275
Short name T215
Test name
Test status
Simulation time 2836927399 ps
CPU time 2.26 seconds
Started Jun 29 06:32:28 PM PDT 24
Finished Jun 29 06:32:31 PM PDT 24
Peak memory 201496 kb
Host smart-f14f7a05-00f6-47f7-9fef-0dbad99f7d53
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437566275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_edge_detect.2437566275
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.4121967289
Short name T449
Test name
Test status
Simulation time 2618058658 ps
CPU time 3.7 seconds
Started Jun 29 06:32:23 PM PDT 24
Finished Jun 29 06:32:27 PM PDT 24
Peak memory 201536 kb
Host smart-b28a2f2c-7c9b-4346-b378-5db296eae849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121967289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.4121967289
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.611520476
Short name T509
Test name
Test status
Simulation time 2479694244 ps
CPU time 2.26 seconds
Started Jun 29 06:32:22 PM PDT 24
Finished Jun 29 06:32:25 PM PDT 24
Peak memory 201532 kb
Host smart-291256bb-374b-4e41-8ca2-8d1ba57a537a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611520476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.611520476
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.4081482907
Short name T689
Test name
Test status
Simulation time 2048216486 ps
CPU time 6.04 seconds
Started Jun 29 06:32:20 PM PDT 24
Finished Jun 29 06:32:26 PM PDT 24
Peak memory 201460 kb
Host smart-85c42a81-002d-4d9a-9533-0c654361270a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081482907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.4081482907
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.3159449451
Short name T349
Test name
Test status
Simulation time 2536006959 ps
CPU time 2.35 seconds
Started Jun 29 06:32:20 PM PDT 24
Finished Jun 29 06:32:23 PM PDT 24
Peak memory 201524 kb
Host smart-1edf052f-06d6-4ad8-8ebd-30fb8ee0ef17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159449451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.3159449451
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.2551965576
Short name T570
Test name
Test status
Simulation time 2109416321 ps
CPU time 5.27 seconds
Started Jun 29 06:32:19 PM PDT 24
Finished Jun 29 06:32:24 PM PDT 24
Peak memory 201408 kb
Host smart-cb51c4e6-780f-468c-937c-49b39ae6972a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551965576 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.2551965576
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2154413962
Short name T4
Test name
Test status
Simulation time 26387753040 ps
CPU time 62.15 seconds
Started Jun 29 06:32:26 PM PDT 24
Finished Jun 29 06:33:30 PM PDT 24
Peak memory 218352 kb
Host smart-49d15201-1ee8-4a2a-bc64-d91b06cc5578
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154413962 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.2154413962
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.2750192324
Short name T133
Test name
Test status
Simulation time 5908383789 ps
CPU time 4.11 seconds
Started Jun 29 06:32:19 PM PDT 24
Finished Jun 29 06:32:24 PM PDT 24
Peak memory 201552 kb
Host smart-3aa78ef6-df7e-4c44-b2ff-c30ad1bcfc32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750192324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ultra_low_pwr.2750192324
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.926244836
Short name T465
Test name
Test status
Simulation time 2021654883 ps
CPU time 3.16 seconds
Started Jun 29 06:32:25 PM PDT 24
Finished Jun 29 06:32:28 PM PDT 24
Peak memory 201516 kb
Host smart-7c24b759-d286-4a4a-881d-638d6437407b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926244836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_tes
t.926244836
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.3779240314
Short name T50
Test name
Test status
Simulation time 3473124959 ps
CPU time 9.2 seconds
Started Jun 29 06:32:26 PM PDT 24
Finished Jun 29 06:32:37 PM PDT 24
Peak memory 201616 kb
Host smart-b6ca52d5-0714-4546-9e41-19fb10ed572a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779240314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.3
779240314
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.4201655583
Short name T308
Test name
Test status
Simulation time 55803819813 ps
CPU time 37.41 seconds
Started Jun 29 06:32:27 PM PDT 24
Finished Jun 29 06:33:06 PM PDT 24
Peak memory 201820 kb
Host smart-bb7fb5da-fc3f-4b73-b6db-632267a535a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201655583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_combo_detect.4201655583
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.2845848002
Short name T703
Test name
Test status
Simulation time 3371048889 ps
CPU time 8.72 seconds
Started Jun 29 06:32:31 PM PDT 24
Finished Jun 29 06:32:40 PM PDT 24
Peak memory 201416 kb
Host smart-93f95ac5-9365-46f7-b859-da0368bb4898
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845848002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ec_pwr_on_rst.2845848002
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.346241980
Short name T199
Test name
Test status
Simulation time 2611422646 ps
CPU time 6.46 seconds
Started Jun 29 06:32:39 PM PDT 24
Finished Jun 29 06:32:46 PM PDT 24
Peak memory 201508 kb
Host smart-8d29cb47-20c9-490a-b879-b50d48bf135f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346241980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.346241980
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.281946025
Short name T668
Test name
Test status
Simulation time 2487612523 ps
CPU time 2.49 seconds
Started Jun 29 06:32:31 PM PDT 24
Finished Jun 29 06:32:34 PM PDT 24
Peak memory 201436 kb
Host smart-db504cc7-683e-4255-af5f-0e7714d444a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281946025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.281946025
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.1257628939
Short name T763
Test name
Test status
Simulation time 2044482511 ps
CPU time 1.38 seconds
Started Jun 29 06:32:25 PM PDT 24
Finished Jun 29 06:32:27 PM PDT 24
Peak memory 201460 kb
Host smart-017e92a4-ca62-4b41-82ed-88092e4d15a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257628939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.1257628939
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.1863401324
Short name T419
Test name
Test status
Simulation time 2515112431 ps
CPU time 3.69 seconds
Started Jun 29 06:32:26 PM PDT 24
Finished Jun 29 06:32:31 PM PDT 24
Peak memory 201516 kb
Host smart-cd99120a-19ac-4aef-b41e-dd7239255de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863401324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.1863401324
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.77637338
Short name T545
Test name
Test status
Simulation time 2168629669 ps
CPU time 1.13 seconds
Started Jun 29 06:32:31 PM PDT 24
Finished Jun 29 06:32:33 PM PDT 24
Peak memory 201308 kb
Host smart-501f283f-9934-4f2d-898c-4b70b8dd7f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77637338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.77637338
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.4048484324
Short name T103
Test name
Test status
Simulation time 18483732271 ps
CPU time 44.5 seconds
Started Jun 29 06:32:25 PM PDT 24
Finished Jun 29 06:33:09 PM PDT 24
Peak memory 201620 kb
Host smart-781423a6-f046-4a5c-91d1-814b2e480527
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048484324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.4048484324
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.3872382425
Short name T136
Test name
Test status
Simulation time 2530918117267 ps
CPU time 27.78 seconds
Started Jun 29 06:32:38 PM PDT 24
Finished Jun 29 06:33:06 PM PDT 24
Peak memory 201496 kb
Host smart-3fd0c9d7-ea99-4631-ac1c-e6c6f04dd3aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872382425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ultra_low_pwr.3872382425
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.1187232038
Short name T477
Test name
Test status
Simulation time 2031002248 ps
CPU time 2.74 seconds
Started Jun 29 06:32:27 PM PDT 24
Finished Jun 29 06:32:31 PM PDT 24
Peak memory 201512 kb
Host smart-47e7aa79-5ee2-4f31-b93b-170375934b25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187232038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te
st.1187232038
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.1350679639
Short name T208
Test name
Test status
Simulation time 3695275676 ps
CPU time 5.82 seconds
Started Jun 29 06:32:45 PM PDT 24
Finished Jun 29 06:32:51 PM PDT 24
Peak memory 201548 kb
Host smart-dfb9389b-4297-4450-8ae1-90953dba880e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350679639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.1
350679639
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.2516180906
Short name T394
Test name
Test status
Simulation time 58480646210 ps
CPU time 160.27 seconds
Started Jun 29 06:32:27 PM PDT 24
Finished Jun 29 06:35:08 PM PDT 24
Peak memory 201836 kb
Host smart-5d1c65c3-3327-4306-a48a-efae13c26cae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516180906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_combo_detect.2516180906
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2553804629
Short name T297
Test name
Test status
Simulation time 35035293755 ps
CPU time 46.59 seconds
Started Jun 29 06:32:26 PM PDT 24
Finished Jun 29 06:33:14 PM PDT 24
Peak memory 201860 kb
Host smart-557e0658-1868-447f-8685-d99a594648ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553804629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_w
ith_pre_cond.2553804629
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.1911532591
Short name T163
Test name
Test status
Simulation time 3316522808 ps
CPU time 2.54 seconds
Started Jun 29 06:32:33 PM PDT 24
Finished Jun 29 06:32:36 PM PDT 24
Peak memory 201488 kb
Host smart-4f7f6cd6-1415-4d10-bad9-6405e0970e41
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911532591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ec_pwr_on_rst.1911532591
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.2351092007
Short name T542
Test name
Test status
Simulation time 2620665527 ps
CPU time 2.29 seconds
Started Jun 29 06:32:37 PM PDT 24
Finished Jun 29 06:32:40 PM PDT 24
Peak memory 201512 kb
Host smart-812410af-00bb-44af-b92a-ddb84f72899d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351092007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.2351092007
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.745825807
Short name T316
Test name
Test status
Simulation time 2485502136 ps
CPU time 2.62 seconds
Started Jun 29 06:32:27 PM PDT 24
Finished Jun 29 06:32:31 PM PDT 24
Peak memory 201540 kb
Host smart-b8e61f20-6ee2-402a-a2f6-b3a33f929231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745825807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.745825807
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.3224446842
Short name T550
Test name
Test status
Simulation time 2050782864 ps
CPU time 1.65 seconds
Started Jun 29 06:32:27 PM PDT 24
Finished Jun 29 06:32:29 PM PDT 24
Peak memory 201460 kb
Host smart-213094ba-08c9-4e3b-80bd-fc4a6808ecf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224446842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.3224446842
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.1420031040
Short name T525
Test name
Test status
Simulation time 2513428840 ps
CPU time 5.57 seconds
Started Jun 29 06:32:26 PM PDT 24
Finished Jun 29 06:32:32 PM PDT 24
Peak memory 201536 kb
Host smart-64d645e3-a61f-4b97-b58d-c51ccdea58df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420031040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.1420031040
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.1374351477
Short name T456
Test name
Test status
Simulation time 2127527202 ps
CPU time 2.03 seconds
Started Jun 29 06:32:26 PM PDT 24
Finished Jun 29 06:32:28 PM PDT 24
Peak memory 201428 kb
Host smart-482490a1-1fb9-430c-988f-13138dd00b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374351477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.1374351477
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2818971344
Short name T31
Test name
Test status
Simulation time 4648760367 ps
CPU time 3.67 seconds
Started Jun 29 06:32:26 PM PDT 24
Finished Jun 29 06:32:31 PM PDT 24
Peak memory 201564 kb
Host smart-3ad8b82f-08d0-4ec3-8a5c-ff1a12c05d54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818971344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ultra_low_pwr.2818971344
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.610064358
Short name T558
Test name
Test status
Simulation time 2039114385 ps
CPU time 1.94 seconds
Started Jun 29 06:32:28 PM PDT 24
Finished Jun 29 06:32:31 PM PDT 24
Peak memory 201512 kb
Host smart-d374048d-7124-4aec-b61c-3521cdb4b5c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610064358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_tes
t.610064358
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.1764300070
Short name T210
Test name
Test status
Simulation time 2866758294 ps
CPU time 4.23 seconds
Started Jun 29 06:32:26 PM PDT 24
Finished Jun 29 06:32:30 PM PDT 24
Peak memory 201576 kb
Host smart-dbabd536-4972-4d76-8dda-eb94174b3d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764300070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.1
764300070
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.4109184288
Short name T388
Test name
Test status
Simulation time 109388689189 ps
CPU time 76.4 seconds
Started Jun 29 06:32:26 PM PDT 24
Finished Jun 29 06:33:44 PM PDT 24
Peak memory 201816 kb
Host smart-955323ad-44b0-4403-b75a-b14110005453
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109184288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.4109184288
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.397871767
Short name T466
Test name
Test status
Simulation time 2607749807 ps
CPU time 2.44 seconds
Started Jun 29 06:32:26 PM PDT 24
Finished Jun 29 06:32:29 PM PDT 24
Peak memory 201508 kb
Host smart-0be7be2b-20a6-4dbb-9e4c-5fbb3d17fca4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397871767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_ec_pwr_on_rst.397871767
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.518997000
Short name T640
Test name
Test status
Simulation time 3992219169 ps
CPU time 2.17 seconds
Started Jun 29 06:32:26 PM PDT 24
Finished Jun 29 06:32:28 PM PDT 24
Peak memory 201500 kb
Host smart-6ddf9238-e041-4f9e-a623-b454b132d757
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518997000 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctr
l_edge_detect.518997000
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.1094574286
Short name T155
Test name
Test status
Simulation time 2656347656 ps
CPU time 1.47 seconds
Started Jun 29 06:32:31 PM PDT 24
Finished Jun 29 06:32:33 PM PDT 24
Peak memory 201344 kb
Host smart-f6a028ee-27c3-4467-b2cc-7030f0024c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094574286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.1094574286
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.1507590671
Short name T541
Test name
Test status
Simulation time 2469554435 ps
CPU time 6.71 seconds
Started Jun 29 06:32:33 PM PDT 24
Finished Jun 29 06:32:40 PM PDT 24
Peak memory 201516 kb
Host smart-4e8a2eca-0520-49a4-b072-7493e8cbe8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507590671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.1507590671
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.3505797501
Short name T537
Test name
Test status
Simulation time 2022709905 ps
CPU time 5.7 seconds
Started Jun 29 06:32:27 PM PDT 24
Finished Jun 29 06:32:34 PM PDT 24
Peak memory 201404 kb
Host smart-5e1d6886-97c2-4880-b2a0-7f6bdea7f5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505797501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.3505797501
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.3326897050
Short name T588
Test name
Test status
Simulation time 2520474747 ps
CPU time 3.96 seconds
Started Jun 29 06:32:29 PM PDT 24
Finished Jun 29 06:32:33 PM PDT 24
Peak memory 201460 kb
Host smart-be0fcfa1-8d5d-478a-966f-84dd60fee4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326897050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.3326897050
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.59990805
Short name T261
Test name
Test status
Simulation time 2140269612 ps
CPU time 1.58 seconds
Started Jun 29 06:32:25 PM PDT 24
Finished Jun 29 06:32:27 PM PDT 24
Peak memory 201448 kb
Host smart-ec5a4833-8776-4949-8d19-f283cbadba0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59990805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.59990805
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.3467400935
Short name T39
Test name
Test status
Simulation time 14052218153 ps
CPU time 35.7 seconds
Started Jun 29 06:32:27 PM PDT 24
Finished Jun 29 06:33:04 PM PDT 24
Peak memory 201556 kb
Host smart-c6af127d-58b1-4404-95ba-ac1c25756503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467400935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_s
tress_all.3467400935
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.90584714
Short name T134
Test name
Test status
Simulation time 50946020080 ps
CPU time 120.55 seconds
Started Jun 29 06:32:26 PM PDT 24
Finished Jun 29 06:34:28 PM PDT 24
Peak memory 218364 kb
Host smart-891e145a-2e44-4163-8d1b-c9b0f4651127
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90584714 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.90584714
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.4148680616
Short name T60
Test name
Test status
Simulation time 3102721606 ps
CPU time 3.18 seconds
Started Jun 29 06:32:28 PM PDT 24
Finished Jun 29 06:32:32 PM PDT 24
Peak memory 201504 kb
Host smart-5e82b3ea-237f-43e7-b511-765abd5a38b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148680616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.4148680616
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.1574781924
Short name T491
Test name
Test status
Simulation time 2176587579 ps
CPU time 0.9 seconds
Started Jun 29 06:31:31 PM PDT 24
Finished Jun 29 06:31:33 PM PDT 24
Peak memory 201572 kb
Host smart-caf05fe6-cf07-453e-aa2d-6745ba18edb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574781924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.1574781924
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3779019409
Short name T582
Test name
Test status
Simulation time 3434223563 ps
CPU time 1.51 seconds
Started Jun 29 06:31:36 PM PDT 24
Finished Jun 29 06:31:38 PM PDT 24
Peak memory 201608 kb
Host smart-0f42e012-6683-44ad-9b7a-3fcdedcd322e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779019409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.3779019409
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.3741860422
Short name T384
Test name
Test status
Simulation time 51852890711 ps
CPU time 130.28 seconds
Started Jun 29 06:31:32 PM PDT 24
Finished Jun 29 06:33:43 PM PDT 24
Peak memory 201784 kb
Host smart-ba5fb60c-8451-47a8-b995-bd73e0eeaf83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741860422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_combo_detect.3741860422
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.3942914807
Short name T730
Test name
Test status
Simulation time 2170683179 ps
CPU time 6.26 seconds
Started Jun 29 06:31:36 PM PDT 24
Finished Jun 29 06:31:43 PM PDT 24
Peak memory 201520 kb
Host smart-97c37db0-08f7-49c7-a369-7b106f4d892a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942914807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.3942914807
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3793154406
Short name T633
Test name
Test status
Simulation time 2340429494 ps
CPU time 1.13 seconds
Started Jun 29 06:31:36 PM PDT 24
Finished Jun 29 06:31:38 PM PDT 24
Peak memory 201524 kb
Host smart-8cc1048d-1f34-4878-a8d9-51016250b71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793154406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3793154406
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1726993885
Short name T686
Test name
Test status
Simulation time 71581297436 ps
CPU time 191.62 seconds
Started Jun 29 06:31:37 PM PDT 24
Finished Jun 29 06:34:49 PM PDT 24
Peak memory 201836 kb
Host smart-a8fdf3b2-9c88-40c3-bff5-a29028994768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726993885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wi
th_pre_cond.1726993885
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2103347242
Short name T481
Test name
Test status
Simulation time 5563824076 ps
CPU time 3.85 seconds
Started Jun 29 06:31:35 PM PDT 24
Finished Jun 29 06:31:39 PM PDT 24
Peak memory 201552 kb
Host smart-bd2c2dfc-8961-4cad-9ec6-7817d41b4bdb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103347242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ec_pwr_on_rst.2103347242
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.588200544
Short name T641
Test name
Test status
Simulation time 3110945452 ps
CPU time 2.04 seconds
Started Jun 29 06:31:33 PM PDT 24
Finished Jun 29 06:31:36 PM PDT 24
Peak memory 201532 kb
Host smart-69a14eb3-68ae-4179-beb9-ea4dcd568779
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588200544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_edge_detect.588200544
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.3607667081
Short name T702
Test name
Test status
Simulation time 2611425306 ps
CPU time 4.36 seconds
Started Jun 29 06:31:33 PM PDT 24
Finished Jun 29 06:31:38 PM PDT 24
Peak memory 201456 kb
Host smart-b524bb94-a4d5-4b53-a19e-f62eb390dbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607667081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.3607667081
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.3817738736
Short name T557
Test name
Test status
Simulation time 2477225269 ps
CPU time 2.32 seconds
Started Jun 29 06:31:34 PM PDT 24
Finished Jun 29 06:31:37 PM PDT 24
Peak memory 201516 kb
Host smart-23557157-c815-4a8f-9392-0397b950b4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817738736 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.3817738736
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.4232814270
Short name T440
Test name
Test status
Simulation time 2038971251 ps
CPU time 3.28 seconds
Started Jun 29 06:31:34 PM PDT 24
Finished Jun 29 06:31:38 PM PDT 24
Peak memory 201468 kb
Host smart-398e2e53-d859-44ed-8b75-1ac5866b43a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232814270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.4232814270
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.3210924473
Short name T350
Test name
Test status
Simulation time 2521264112 ps
CPU time 4.18 seconds
Started Jun 29 06:31:32 PM PDT 24
Finished Jun 29 06:31:37 PM PDT 24
Peak memory 201520 kb
Host smart-b731a5a3-a82a-459c-a7e0-37367e7a06c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210924473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.3210924473
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.3655589200
Short name T245
Test name
Test status
Simulation time 22065758278 ps
CPU time 13.3 seconds
Started Jun 29 06:31:34 PM PDT 24
Finished Jun 29 06:31:48 PM PDT 24
Peak memory 221380 kb
Host smart-44e0e959-10aa-4c9c-9f77-68759a5fb52c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655589200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.3655589200
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.3234710558
Short name T154
Test name
Test status
Simulation time 2109888121 ps
CPU time 5.9 seconds
Started Jun 29 06:31:35 PM PDT 24
Finished Jun 29 06:31:41 PM PDT 24
Peak memory 201468 kb
Host smart-f712a3ee-2bc1-47d2-913e-5f537b0bbf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234710558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.3234710558
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.3413548619
Short name T77
Test name
Test status
Simulation time 83710040618 ps
CPU time 191.49 seconds
Started Jun 29 06:31:33 PM PDT 24
Finished Jun 29 06:34:45 PM PDT 24
Peak memory 201764 kb
Host smart-14702e22-1507-4e5f-b15d-caf1e9654fd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413548619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_st
ress_all.3413548619
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.2179521604
Short name T119
Test name
Test status
Simulation time 275971909531 ps
CPU time 27.24 seconds
Started Jun 29 06:31:33 PM PDT 24
Finished Jun 29 06:32:01 PM PDT 24
Peak memory 218276 kb
Host smart-cc93fd13-6bf5-40ea-b80a-b2e059a5ac09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179521604 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.2179521604
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.4135112562
Short name T546
Test name
Test status
Simulation time 6447407286 ps
CPU time 2.53 seconds
Started Jun 29 06:31:33 PM PDT 24
Finished Jun 29 06:31:37 PM PDT 24
Peak memory 201564 kb
Host smart-19d7b45c-d137-433b-b9ed-85f2a3c254f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135112562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.4135112562
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.2887144859
Short name T667
Test name
Test status
Simulation time 2030153421 ps
CPU time 2 seconds
Started Jun 29 06:32:38 PM PDT 24
Finished Jun 29 06:32:41 PM PDT 24
Peak memory 201732 kb
Host smart-56b4e515-181d-4a44-b1f6-e58e5aadc1e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887144859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_te
st.2887144859
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.2634821147
Short name T669
Test name
Test status
Simulation time 3522640564 ps
CPU time 9.07 seconds
Started Jun 29 06:32:44 PM PDT 24
Finished Jun 29 06:32:53 PM PDT 24
Peak memory 201576 kb
Host smart-76a46d54-7c62-4b1b-9409-137a5cab6a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634821147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.2
634821147
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.3706483606
Short name T386
Test name
Test status
Simulation time 49932210984 ps
CPU time 125.41 seconds
Started Jun 29 06:32:42 PM PDT 24
Finished Jun 29 06:34:47 PM PDT 24
Peak memory 201772 kb
Host smart-8759f77c-af3a-4238-9b16-7bfd57551c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706483606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.3706483606
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.801983095
Short name T599
Test name
Test status
Simulation time 4097674875 ps
CPU time 3.06 seconds
Started Jun 29 06:32:47 PM PDT 24
Finished Jun 29 06:32:50 PM PDT 24
Peak memory 201496 kb
Host smart-69408b56-9766-4102-9ee1-8702b2303214
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801983095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_ec_pwr_on_rst.801983095
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.3216130840
Short name T44
Test name
Test status
Simulation time 2670454733 ps
CPU time 2.21 seconds
Started Jun 29 06:32:39 PM PDT 24
Finished Jun 29 06:32:42 PM PDT 24
Peak memory 201464 kb
Host smart-a35e0bd0-9e37-4002-9316-2ea062cf8ec2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216130840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.3216130840
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.844463593
Short name T656
Test name
Test status
Simulation time 2612259382 ps
CPU time 6.47 seconds
Started Jun 29 06:32:38 PM PDT 24
Finished Jun 29 06:32:45 PM PDT 24
Peak memory 201748 kb
Host smart-0ce63a25-00a5-42bb-84e0-1b4d8869321f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844463593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.844463593
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.4079481842
Short name T529
Test name
Test status
Simulation time 2482109690 ps
CPU time 2.37 seconds
Started Jun 29 06:32:27 PM PDT 24
Finished Jun 29 06:32:30 PM PDT 24
Peak memory 201536 kb
Host smart-54608c93-250d-45dc-b5aa-a3bfd1f900aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079481842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.4079481842
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.2058704501
Short name T764
Test name
Test status
Simulation time 2067273491 ps
CPU time 5.91 seconds
Started Jun 29 06:32:36 PM PDT 24
Finished Jun 29 06:32:43 PM PDT 24
Peak memory 201456 kb
Host smart-4d3cc8bf-f960-4ca5-9e64-f31c87229927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058704501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.2058704501
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.1779494563
Short name T107
Test name
Test status
Simulation time 2594221450 ps
CPU time 1.28 seconds
Started Jun 29 06:32:42 PM PDT 24
Finished Jun 29 06:32:43 PM PDT 24
Peak memory 201516 kb
Host smart-8518abfa-739c-47ec-93c5-33ad426b131a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779494563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.1779494563
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.1183300099
Short name T21
Test name
Test status
Simulation time 2193974620 ps
CPU time 1.02 seconds
Started Jun 29 06:32:26 PM PDT 24
Finished Jun 29 06:32:28 PM PDT 24
Peak memory 201488 kb
Host smart-519dd03e-7e5a-4024-a3bf-1d8a617266de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183300099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.1183300099
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.3220407072
Short name T16
Test name
Test status
Simulation time 8547504806 ps
CPU time 6.68 seconds
Started Jun 29 06:32:34 PM PDT 24
Finished Jun 29 06:32:41 PM PDT 24
Peak memory 201620 kb
Host smart-798a3882-206e-4ee4-ac25-af175f839e63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220407072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.3220407072
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2254801809
Short name T697
Test name
Test status
Simulation time 3880163014 ps
CPU time 4.54 seconds
Started Jun 29 06:32:38 PM PDT 24
Finished Jun 29 06:32:43 PM PDT 24
Peak memory 201504 kb
Host smart-c475cf8a-2963-4f53-bb23-769045fc4bb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254801809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ultra_low_pwr.2254801809
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.3998186224
Short name T619
Test name
Test status
Simulation time 2032662046 ps
CPU time 1.98 seconds
Started Jun 29 06:32:32 PM PDT 24
Finished Jun 29 06:32:35 PM PDT 24
Peak memory 201428 kb
Host smart-a002bcb2-8309-4afb-a670-1a4d936bbc83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998186224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_te
st.3998186224
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.2202172774
Short name T145
Test name
Test status
Simulation time 3933338117 ps
CPU time 4.94 seconds
Started Jun 29 06:32:32 PM PDT 24
Finished Jun 29 06:32:37 PM PDT 24
Peak memory 201584 kb
Host smart-8dad7078-6d14-426b-9eff-dec28aab9af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202172774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.2
202172774
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.550585804
Short name T776
Test name
Test status
Simulation time 198298097138 ps
CPU time 127.7 seconds
Started Jun 29 06:32:43 PM PDT 24
Finished Jun 29 06:34:51 PM PDT 24
Peak memory 201848 kb
Host smart-6a818f80-77fe-4c7f-a81b-a44f6d48ecb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550585804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_combo_detect.550585804
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.2571578171
Short name T289
Test name
Test status
Simulation time 42267793679 ps
CPU time 29.44 seconds
Started Jun 29 06:32:43 PM PDT 24
Finished Jun 29 06:33:13 PM PDT 24
Peak memory 201736 kb
Host smart-1ab02321-3f8c-4ab2-9d45-6f91689e200b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571578171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_w
ith_pre_cond.2571578171
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.3258975273
Short name T604
Test name
Test status
Simulation time 2682338559 ps
CPU time 4.13 seconds
Started Jun 29 06:32:42 PM PDT 24
Finished Jun 29 06:32:46 PM PDT 24
Peak memory 201432 kb
Host smart-35342e91-fb69-4f50-934e-a90eebb2dbd9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258975273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ec_pwr_on_rst.3258975273
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.2172975190
Short name T150
Test name
Test status
Simulation time 4335442990 ps
CPU time 4.78 seconds
Started Jun 29 06:32:38 PM PDT 24
Finished Jun 29 06:32:43 PM PDT 24
Peak memory 201816 kb
Host smart-c3286053-9973-4644-b280-9334cfe7d6e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172975190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_edge_detect.2172975190
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2519197656
Short name T137
Test name
Test status
Simulation time 2635403468 ps
CPU time 2.53 seconds
Started Jun 29 06:32:35 PM PDT 24
Finished Jun 29 06:32:38 PM PDT 24
Peak memory 201484 kb
Host smart-e0a46d37-858c-473b-9839-8371efb6e676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519197656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.2519197656
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.1118978417
Short name T708
Test name
Test status
Simulation time 2468227212 ps
CPU time 3.27 seconds
Started Jun 29 06:32:47 PM PDT 24
Finished Jun 29 06:32:50 PM PDT 24
Peak memory 201516 kb
Host smart-efaf9350-389a-4707-b2f4-583cc29b9bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118978417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.1118978417
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.3419308470
Short name T507
Test name
Test status
Simulation time 2120790901 ps
CPU time 3.44 seconds
Started Jun 29 06:32:50 PM PDT 24
Finished Jun 29 06:32:54 PM PDT 24
Peak memory 201452 kb
Host smart-a2f89c72-4af4-44d0-9237-02e3d7bd6032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419308470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.3419308470
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.4074657641
Short name T613
Test name
Test status
Simulation time 2514227010 ps
CPU time 7.13 seconds
Started Jun 29 06:32:41 PM PDT 24
Finished Jun 29 06:32:48 PM PDT 24
Peak memory 201492 kb
Host smart-127937be-075d-4f7f-a5e7-533cd427f9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074657641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.4074657641
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.3107209664
Short name T128
Test name
Test status
Simulation time 2110604526 ps
CPU time 6.06 seconds
Started Jun 29 06:32:43 PM PDT 24
Finished Jun 29 06:32:50 PM PDT 24
Peak memory 201440 kb
Host smart-25a0700b-4600-4242-babe-c63c150e7523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107209664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.3107209664
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.3891482175
Short name T132
Test name
Test status
Simulation time 10451466163 ps
CPU time 5.47 seconds
Started Jun 29 06:32:35 PM PDT 24
Finished Jun 29 06:32:40 PM PDT 24
Peak memory 201560 kb
Host smart-b5b4d71a-979c-4a39-8a0a-b5f173c8e29b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891482175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_s
tress_all.3891482175
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.2058129858
Short name T340
Test name
Test status
Simulation time 15011488346 ps
CPU time 39.55 seconds
Started Jun 29 06:32:40 PM PDT 24
Finished Jun 29 06:33:20 PM PDT 24
Peak memory 218224 kb
Host smart-357b95a5-4ba7-4d60-9b46-9ab0dae34e92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058129858 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.2058129858
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.1185770417
Short name T430
Test name
Test status
Simulation time 2026591320 ps
CPU time 1.95 seconds
Started Jun 29 06:32:44 PM PDT 24
Finished Jun 29 06:32:47 PM PDT 24
Peak memory 201524 kb
Host smart-ce753914-7e99-4540-9ba6-037f10528d1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185770417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_te
st.1185770417
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.1769005605
Short name T732
Test name
Test status
Simulation time 6053082078 ps
CPU time 4.24 seconds
Started Jun 29 06:32:48 PM PDT 24
Finished Jun 29 06:32:53 PM PDT 24
Peak memory 201676 kb
Host smart-5e9886cd-b28f-40d5-b184-3ffb3000e498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769005605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.1
769005605
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.729883766
Short name T714
Test name
Test status
Simulation time 156584030400 ps
CPU time 192.92 seconds
Started Jun 29 06:32:39 PM PDT 24
Finished Jun 29 06:35:52 PM PDT 24
Peak memory 201792 kb
Host smart-3bdae004-d7ac-49d6-9b24-24af32fcdd3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729883766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_combo_detect.729883766
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.114166829
Short name T411
Test name
Test status
Simulation time 28348191312 ps
CPU time 21.63 seconds
Started Jun 29 06:32:48 PM PDT 24
Finished Jun 29 06:33:10 PM PDT 24
Peak memory 201836 kb
Host smart-9abdd46f-db10-445d-a5f0-3e7be265da65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114166829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_wi
th_pre_cond.114166829
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.2202034984
Short name T500
Test name
Test status
Simulation time 3077987986 ps
CPU time 8.32 seconds
Started Jun 29 06:32:43 PM PDT 24
Finished Jun 29 06:32:52 PM PDT 24
Peak memory 201468 kb
Host smart-988ccfae-201f-4ed0-8cfe-15331df3bf5d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202034984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.2202034984
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.3022120669
Short name T701
Test name
Test status
Simulation time 2594184532 ps
CPU time 2.49 seconds
Started Jun 29 06:32:35 PM PDT 24
Finished Jun 29 06:32:38 PM PDT 24
Peak memory 201500 kb
Host smart-c9b59698-92e8-4cb8-a1d2-5edd6c3e1f01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022120669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.3022120669
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3602513958
Short name T178
Test name
Test status
Simulation time 2623456930 ps
CPU time 2.38 seconds
Started Jun 29 06:32:35 PM PDT 24
Finished Jun 29 06:32:37 PM PDT 24
Peak memory 201528 kb
Host smart-516c9aad-3348-4127-b3e4-eaa98ab8b62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602513958 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.3602513958
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.1356675166
Short name T238
Test name
Test status
Simulation time 2567952890 ps
CPU time 1.1 seconds
Started Jun 29 06:32:33 PM PDT 24
Finished Jun 29 06:32:35 PM PDT 24
Peak memory 201520 kb
Host smart-fd46eb8e-7d20-44f7-9934-910ab7d30add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356675166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.1356675166
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.4127095077
Short name T772
Test name
Test status
Simulation time 2056572238 ps
CPU time 5.93 seconds
Started Jun 29 06:32:48 PM PDT 24
Finished Jun 29 06:32:54 PM PDT 24
Peak memory 201408 kb
Host smart-2f2ec350-b8d6-43d3-8879-a81f9462ea78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127095077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.4127095077
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.763215627
Short name T69
Test name
Test status
Simulation time 2519885224 ps
CPU time 2.46 seconds
Started Jun 29 06:32:38 PM PDT 24
Finished Jun 29 06:32:41 PM PDT 24
Peak memory 201476 kb
Host smart-fecdd828-108e-4d27-82bc-3933f49f56a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763215627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.763215627
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.2836640484
Short name T423
Test name
Test status
Simulation time 2109380674 ps
CPU time 5.68 seconds
Started Jun 29 06:32:45 PM PDT 24
Finished Jun 29 06:32:51 PM PDT 24
Peak memory 201400 kb
Host smart-31020d38-6a03-4da7-90d9-31d7ecd7ffc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836640484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.2836640484
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.664991434
Short name T753
Test name
Test status
Simulation time 11942984176 ps
CPU time 7.15 seconds
Started Jun 29 06:32:37 PM PDT 24
Finished Jun 29 06:32:44 PM PDT 24
Peak memory 201556 kb
Host smart-74ade0a7-6e97-4592-a9e0-92bc84327ca2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664991434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_st
ress_all.664991434
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.2764258015
Short name T224
Test name
Test status
Simulation time 46160318285 ps
CPU time 31.69 seconds
Started Jun 29 06:32:33 PM PDT 24
Finished Jun 29 06:33:05 PM PDT 24
Peak memory 210208 kb
Host smart-a82ff87e-7227-46b4-81f5-0aeed10a265c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764258015 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.2764258015
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.3854573223
Short name T353
Test name
Test status
Simulation time 6987498336 ps
CPU time 1.18 seconds
Started Jun 29 06:32:47 PM PDT 24
Finished Jun 29 06:32:48 PM PDT 24
Peak memory 201552 kb
Host smart-02352d27-8d5a-4896-bb03-fcaaa57bfc0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854573223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ultra_low_pwr.3854573223
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.1370366672
Short name T249
Test name
Test status
Simulation time 2038811778 ps
CPU time 1.78 seconds
Started Jun 29 06:32:48 PM PDT 24
Finished Jun 29 06:32:50 PM PDT 24
Peak memory 201500 kb
Host smart-e11d371e-81e8-472d-be0a-0ff16bfaa4a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370366672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.1370366672
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.3281644588
Short name T679
Test name
Test status
Simulation time 3606136457 ps
CPU time 2.92 seconds
Started Jun 29 06:32:47 PM PDT 24
Finished Jun 29 06:32:51 PM PDT 24
Peak memory 201576 kb
Host smart-fd445ea4-8190-4b54-a227-44c58ebe2764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281644588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.3
281644588
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.2242065252
Short name T108
Test name
Test status
Simulation time 62278287739 ps
CPU time 43.21 seconds
Started Jun 29 06:32:36 PM PDT 24
Finished Jun 29 06:33:19 PM PDT 24
Peak memory 201860 kb
Host smart-782f025b-e2ae-4c99-b4c9-0073ffd132f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242065252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.2242065252
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.3982201603
Short name T191
Test name
Test status
Simulation time 4277142479 ps
CPU time 10.79 seconds
Started Jun 29 06:32:39 PM PDT 24
Finished Jun 29 06:32:51 PM PDT 24
Peak memory 201468 kb
Host smart-ab377bd8-d6ac-453e-9326-11e7e749f147
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982201603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.3982201603
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.790221931
Short name T190
Test name
Test status
Simulation time 4164366612 ps
CPU time 4.43 seconds
Started Jun 29 06:32:38 PM PDT 24
Finished Jun 29 06:32:43 PM PDT 24
Peak memory 201480 kb
Host smart-bc576106-5118-4a4a-8712-50315d116e5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790221931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctr
l_edge_detect.790221931
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.4025205808
Short name T527
Test name
Test status
Simulation time 2614390522 ps
CPU time 7.4 seconds
Started Jun 29 06:32:47 PM PDT 24
Finished Jun 29 06:32:55 PM PDT 24
Peak memory 201520 kb
Host smart-119511fe-7d9b-4965-8f1e-9e29da859f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025205808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.4025205808
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.2886648650
Short name T777
Test name
Test status
Simulation time 2457372951 ps
CPU time 7.82 seconds
Started Jun 29 06:32:38 PM PDT 24
Finished Jun 29 06:32:46 PM PDT 24
Peak memory 201524 kb
Host smart-f2c01269-1074-429c-b868-13968f6f7216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886648650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.2886648650
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.383797145
Short name T521
Test name
Test status
Simulation time 2283861765 ps
CPU time 2.02 seconds
Started Jun 29 06:32:40 PM PDT 24
Finished Jun 29 06:32:42 PM PDT 24
Peak memory 201496 kb
Host smart-a4f8d3ce-fd1f-4a06-9a97-60fbfd94e4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383797145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.383797145
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.561612796
Short name T162
Test name
Test status
Simulation time 2510924985 ps
CPU time 7.51 seconds
Started Jun 29 06:32:48 PM PDT 24
Finished Jun 29 06:32:56 PM PDT 24
Peak memory 201532 kb
Host smart-2b7d4f9e-2778-40d4-9ce7-30cffbecf65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561612796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.561612796
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.4195751294
Short name T670
Test name
Test status
Simulation time 2130230937 ps
CPU time 1.97 seconds
Started Jun 29 06:32:33 PM PDT 24
Finished Jun 29 06:32:35 PM PDT 24
Peak memory 201448 kb
Host smart-885beecd-4ed6-43cb-97c1-ea860d650599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195751294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.4195751294
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.2396283844
Short name T87
Test name
Test status
Simulation time 12856917086 ps
CPU time 8.73 seconds
Started Jun 29 06:32:49 PM PDT 24
Finished Jun 29 06:32:58 PM PDT 24
Peak memory 201552 kb
Host smart-617ade54-308e-4a15-8e9d-bc42e9f856d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396283844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_s
tress_all.2396283844
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.902164469
Short name T126
Test name
Test status
Simulation time 7766370434 ps
CPU time 4.63 seconds
Started Jun 29 06:32:45 PM PDT 24
Finished Jun 29 06:32:50 PM PDT 24
Peak memory 201604 kb
Host smart-88c0cf94-04bf-4468-83db-ae43e64d2a88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902164469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_ultra_low_pwr.902164469
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.2661260216
Short name T463
Test name
Test status
Simulation time 2014193057 ps
CPU time 5.83 seconds
Started Jun 29 06:32:39 PM PDT 24
Finished Jun 29 06:32:46 PM PDT 24
Peak memory 201508 kb
Host smart-30300835-6c83-441f-b630-fbc91d7f1ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661260216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_te
st.2661260216
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.1981833304
Short name T98
Test name
Test status
Simulation time 83048259896 ps
CPU time 229.14 seconds
Started Jun 29 06:32:43 PM PDT 24
Finished Jun 29 06:36:32 PM PDT 24
Peak memory 201640 kb
Host smart-810270ac-f9f0-410f-9657-5eba1c968e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981833304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.1
981833304
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.2188314081
Short name T662
Test name
Test status
Simulation time 74945934076 ps
CPU time 41.81 seconds
Started Jun 29 06:32:45 PM PDT 24
Finished Jun 29 06:33:28 PM PDT 24
Peak memory 201836 kb
Host smart-c4e32349-021d-4648-b902-1658a0250706
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188314081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_combo_detect.2188314081
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.3200992480
Short name T756
Test name
Test status
Simulation time 3387852972 ps
CPU time 9.08 seconds
Started Jun 29 06:32:41 PM PDT 24
Finished Jun 29 06:32:50 PM PDT 24
Peak memory 201492 kb
Host smart-dd196287-f90a-4a02-83f6-bbb08f214c4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200992480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ec_pwr_on_rst.3200992480
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.3053028325
Short name T229
Test name
Test status
Simulation time 3533882910 ps
CPU time 2.7 seconds
Started Jun 29 06:32:48 PM PDT 24
Finished Jun 29 06:32:52 PM PDT 24
Peak memory 201520 kb
Host smart-05c09cf1-a799-4275-84d9-a4d917fad845
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053028325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.3053028325
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.3876366741
Short name T484
Test name
Test status
Simulation time 2619745594 ps
CPU time 4.02 seconds
Started Jun 29 06:32:50 PM PDT 24
Finished Jun 29 06:32:55 PM PDT 24
Peak memory 201520 kb
Host smart-5a99192b-2f11-4be6-967d-b57d5b38cf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876366741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.3876366741
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.4234847342
Short name T176
Test name
Test status
Simulation time 2442712748 ps
CPU time 4.82 seconds
Started Jun 29 06:32:50 PM PDT 24
Finished Jun 29 06:32:56 PM PDT 24
Peak memory 201516 kb
Host smart-c531167f-00ae-44ac-b376-56db6f7d825d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234847342 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.4234847342
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.1593125220
Short name T460
Test name
Test status
Simulation time 2206582663 ps
CPU time 2.61 seconds
Started Jun 29 06:32:50 PM PDT 24
Finished Jun 29 06:32:53 PM PDT 24
Peak memory 201532 kb
Host smart-ad3c5cc8-0c47-4bc0-841e-57a6a25f47fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593125220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.1593125220
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.3711868166
Short name T498
Test name
Test status
Simulation time 2511317302 ps
CPU time 6.84 seconds
Started Jun 29 06:32:46 PM PDT 24
Finished Jun 29 06:32:53 PM PDT 24
Peak memory 201532 kb
Host smart-628e254e-d36a-47c6-9890-622fccee4c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711868166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.3711868166
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.660232145
Short name T462
Test name
Test status
Simulation time 2141215416 ps
CPU time 1.41 seconds
Started Jun 29 06:32:47 PM PDT 24
Finished Jun 29 06:32:48 PM PDT 24
Peak memory 201468 kb
Host smart-e12c7ec8-461b-48d8-b7c3-109fde1a9542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660232145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.660232145
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.1631786666
Short name T385
Test name
Test status
Simulation time 103771144102 ps
CPU time 141.04 seconds
Started Jun 29 06:32:41 PM PDT 24
Finished Jun 29 06:35:03 PM PDT 24
Peak memory 201832 kb
Host smart-a20d5c09-2afb-45fd-9acd-15ab74fbb0cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631786666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s
tress_all.1631786666
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.448284215
Short name T335
Test name
Test status
Simulation time 67450708884 ps
CPU time 29.98 seconds
Started Jun 29 06:32:43 PM PDT 24
Finished Jun 29 06:33:14 PM PDT 24
Peak memory 210076 kb
Host smart-77a7815d-1003-49b8-a4ba-6d450dae5672
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448284215 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.448284215
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.3333640435
Short name T715
Test name
Test status
Simulation time 2019661739 ps
CPU time 5.23 seconds
Started Jun 29 06:32:46 PM PDT 24
Finished Jun 29 06:32:52 PM PDT 24
Peak memory 201484 kb
Host smart-bfb84e45-5244-4231-a11a-7d100d0829b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333640435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te
st.3333640435
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.427185046
Short name T117
Test name
Test status
Simulation time 3475619392 ps
CPU time 2.99 seconds
Started Jun 29 06:32:38 PM PDT 24
Finished Jun 29 06:32:42 PM PDT 24
Peak memory 201596 kb
Host smart-a1228c76-fa5f-491b-9bd9-3782f817438b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427185046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.427185046
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.200962709
Short name T291
Test name
Test status
Simulation time 60384708403 ps
CPU time 41.92 seconds
Started Jun 29 06:32:50 PM PDT 24
Finished Jun 29 06:33:33 PM PDT 24
Peak memory 201824 kb
Host smart-ce8866fd-9f64-426f-a07a-40196aff4186
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200962709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_combo_detect.200962709
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.805869852
Short name T711
Test name
Test status
Simulation time 96040343610 ps
CPU time 235.3 seconds
Started Jun 29 06:32:48 PM PDT 24
Finished Jun 29 06:36:44 PM PDT 24
Peak memory 201800 kb
Host smart-c27634b1-91ca-4b98-8006-e83b3ff78b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805869852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_wi
th_pre_cond.805869852
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.954031947
Short name T441
Test name
Test status
Simulation time 4215157422 ps
CPU time 1.47 seconds
Started Jun 29 06:32:50 PM PDT 24
Finished Jun 29 06:32:52 PM PDT 24
Peak memory 201472 kb
Host smart-92bfe542-5e88-469c-b9c4-3869359c9d28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954031947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_ec_pwr_on_rst.954031947
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.4239077118
Short name T40
Test name
Test status
Simulation time 3252765146 ps
CPU time 6.44 seconds
Started Jun 29 06:32:40 PM PDT 24
Finished Jun 29 06:32:47 PM PDT 24
Peak memory 201500 kb
Host smart-5273bd35-e7b6-48fc-93f2-936bbeeb146b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239077118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_edge_detect.4239077118
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2089617479
Short name T646
Test name
Test status
Simulation time 2633822241 ps
CPU time 2.34 seconds
Started Jun 29 06:32:39 PM PDT 24
Finished Jun 29 06:32:41 PM PDT 24
Peak memory 201524 kb
Host smart-2464e07f-13fd-4be1-bbad-383818972c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089617479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.2089617479
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.733919362
Short name T624
Test name
Test status
Simulation time 2449473707 ps
CPU time 8.32 seconds
Started Jun 29 06:32:46 PM PDT 24
Finished Jun 29 06:32:55 PM PDT 24
Peak memory 201512 kb
Host smart-f0accbb9-92c3-475b-b724-e1419fa45fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733919362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.733919362
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.3778672979
Short name T635
Test name
Test status
Simulation time 2172763994 ps
CPU time 1.19 seconds
Started Jun 29 06:32:40 PM PDT 24
Finished Jun 29 06:32:41 PM PDT 24
Peak memory 201516 kb
Host smart-ea1dc6b1-0298-4a88-8cd6-24c0d61ac3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778672979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.3778672979
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.4209885714
Short name T663
Test name
Test status
Simulation time 2509710920 ps
CPU time 7.16 seconds
Started Jun 29 06:32:39 PM PDT 24
Finished Jun 29 06:32:47 PM PDT 24
Peak memory 201520 kb
Host smart-dfc033ee-aaa8-45c9-b3d2-342c5e2dfb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209885714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.4209885714
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.555752363
Short name T781
Test name
Test status
Simulation time 2130354088 ps
CPU time 1.99 seconds
Started Jun 29 06:32:39 PM PDT 24
Finished Jun 29 06:32:42 PM PDT 24
Peak memory 201448 kb
Host smart-2b83e2c7-d88a-4abc-9cbb-0b3b82706ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555752363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.555752363
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.3503400425
Short name T57
Test name
Test status
Simulation time 13526415165 ps
CPU time 34.89 seconds
Started Jun 29 06:32:47 PM PDT 24
Finished Jun 29 06:33:22 PM PDT 24
Peak memory 201592 kb
Host smart-8bdc1911-392b-4f6d-ad89-8ae79e94bfeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503400425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_s
tress_all.3503400425
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.270057825
Short name T88
Test name
Test status
Simulation time 13407231461 ps
CPU time 3.58 seconds
Started Jun 29 06:32:38 PM PDT 24
Finished Jun 29 06:32:42 PM PDT 24
Peak memory 201592 kb
Host smart-8401c64d-e7d1-4ad9-b3ca-46215854abc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270057825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_ultra_low_pwr.270057825
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.3095792335
Short name T264
Test name
Test status
Simulation time 2019309805 ps
CPU time 3.24 seconds
Started Jun 29 06:32:46 PM PDT 24
Finished Jun 29 06:32:49 PM PDT 24
Peak memory 201512 kb
Host smart-7baa54ae-bee1-4631-ae39-edd11b846699
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095792335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_te
st.3095792335
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3856031251
Short name T478
Test name
Test status
Simulation time 3832235975 ps
CPU time 3.34 seconds
Started Jun 29 06:32:38 PM PDT 24
Finished Jun 29 06:32:42 PM PDT 24
Peak memory 201544 kb
Host smart-72ea7c32-739e-45af-a030-0f058ecb99c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856031251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.3
856031251
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.2194039603
Short name T97
Test name
Test status
Simulation time 79692900037 ps
CPU time 52.51 seconds
Started Jun 29 06:32:48 PM PDT 24
Finished Jun 29 06:33:42 PM PDT 24
Peak memory 201744 kb
Host smart-9339da07-64d7-450b-a11e-f32d977e2ce6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194039603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_combo_detect.2194039603
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.760414207
Short name T627
Test name
Test status
Simulation time 5226485668 ps
CPU time 4.02 seconds
Started Jun 29 06:32:48 PM PDT 24
Finished Jun 29 06:32:53 PM PDT 24
Peak memory 201504 kb
Host smart-39184b30-f6cb-496e-81f3-9fe2efc16ecc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760414207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_ec_pwr_on_rst.760414207
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.1949977920
Short name T632
Test name
Test status
Simulation time 4025481030 ps
CPU time 1.78 seconds
Started Jun 29 06:32:38 PM PDT 24
Finished Jun 29 06:32:40 PM PDT 24
Peak memory 201488 kb
Host smart-7ba46a8a-6b56-4277-a3b0-4e1ab3862ee0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949977920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.1949977920
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.1482040570
Short name T698
Test name
Test status
Simulation time 2611613854 ps
CPU time 7.1 seconds
Started Jun 29 06:32:42 PM PDT 24
Finished Jun 29 06:32:50 PM PDT 24
Peak memory 201524 kb
Host smart-4bc63f57-99ae-4798-a438-51c24fc74ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482040570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.1482040570
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.311961171
Short name T720
Test name
Test status
Simulation time 2461623601 ps
CPU time 5.57 seconds
Started Jun 29 06:32:38 PM PDT 24
Finished Jun 29 06:32:44 PM PDT 24
Peak memory 201524 kb
Host smart-c34a7810-8c4d-4f23-8863-e1dd59741b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311961171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.311961171
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.110657367
Short name T540
Test name
Test status
Simulation time 2188409086 ps
CPU time 3.41 seconds
Started Jun 29 06:32:40 PM PDT 24
Finished Jun 29 06:32:44 PM PDT 24
Peak memory 201520 kb
Host smart-72b151d1-81bc-400e-9c0b-14eead52da6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110657367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.110657367
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.3014453567
Short name T775
Test name
Test status
Simulation time 2514577330 ps
CPU time 7.29 seconds
Started Jun 29 06:32:44 PM PDT 24
Finished Jun 29 06:32:52 PM PDT 24
Peak memory 201512 kb
Host smart-a9e7d8ce-53b7-4d8a-9b07-f54d25c03282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014453567 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.3014453567
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.2945485737
Short name T189
Test name
Test status
Simulation time 2130993229 ps
CPU time 1.87 seconds
Started Jun 29 06:32:49 PM PDT 24
Finished Jun 29 06:32:52 PM PDT 24
Peak memory 201400 kb
Host smart-7fd923e8-0c0e-40b4-82ac-05203e420c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945485737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.2945485737
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.1049443368
Short name T343
Test name
Test status
Simulation time 14035145043 ps
CPU time 38.24 seconds
Started Jun 29 06:32:54 PM PDT 24
Finished Jun 29 06:33:33 PM PDT 24
Peak memory 201780 kb
Host smart-f18a3fdd-dada-4bc8-b455-094fcf3c0034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049443368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_s
tress_all.1049443368
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2679095737
Short name T182
Test name
Test status
Simulation time 47906195553 ps
CPU time 115.39 seconds
Started Jun 29 06:32:50 PM PDT 24
Finished Jun 29 06:34:46 PM PDT 24
Peak memory 210120 kb
Host smart-cfa02ad2-7f45-46ef-8bee-29cbc6c24a75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679095737 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.2679095737
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.2605007369
Short name T271
Test name
Test status
Simulation time 3602073604 ps
CPU time 6.12 seconds
Started Jun 29 06:32:49 PM PDT 24
Finished Jun 29 06:32:56 PM PDT 24
Peak memory 201496 kb
Host smart-f25ceac8-2cd9-4719-b438-3aeabe50201e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605007369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ultra_low_pwr.2605007369
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.3126711978
Short name T105
Test name
Test status
Simulation time 2020786775 ps
CPU time 3.14 seconds
Started Jun 29 06:32:49 PM PDT 24
Finished Jun 29 06:32:53 PM PDT 24
Peak memory 201444 kb
Host smart-469f63d4-4f8d-4172-94e0-08b243adc865
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126711978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.3126711978
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.609799527
Short name T435
Test name
Test status
Simulation time 3105857898 ps
CPU time 8.93 seconds
Started Jun 29 06:32:49 PM PDT 24
Finished Jun 29 06:32:59 PM PDT 24
Peak memory 201596 kb
Host smart-31cf2f42-98e8-40b4-8f6a-c2b38be527d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609799527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.609799527
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.3944081217
Short name T380
Test name
Test status
Simulation time 140797802330 ps
CPU time 88.51 seconds
Started Jun 29 06:32:57 PM PDT 24
Finished Jun 29 06:34:26 PM PDT 24
Peak memory 201724 kb
Host smart-df5e7ffd-333d-4e45-8e2d-908fc4dfbad2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944081217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_combo_detect.3944081217
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.775589308
Short name T407
Test name
Test status
Simulation time 114664430618 ps
CPU time 284.03 seconds
Started Jun 29 06:32:58 PM PDT 24
Finished Jun 29 06:37:43 PM PDT 24
Peak memory 201796 kb
Host smart-0f04ff60-d468-480b-9e5d-250c2118b443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775589308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_wi
th_pre_cond.775589308
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.1333911039
Short name T106
Test name
Test status
Simulation time 2713917493 ps
CPU time 2.44 seconds
Started Jun 29 06:32:49 PM PDT 24
Finished Jun 29 06:32:52 PM PDT 24
Peak memory 201496 kb
Host smart-e0ef0331-20d2-4ea6-9af8-93a27d9e345a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333911039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.1333911039
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.2376808378
Short name T240
Test name
Test status
Simulation time 5264784249 ps
CPU time 3.3 seconds
Started Jun 29 06:32:51 PM PDT 24
Finished Jun 29 06:32:55 PM PDT 24
Peak memory 201592 kb
Host smart-e8116418-cc70-4f48-bee4-333e9f1012e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376808378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_edge_detect.2376808378
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.13712877
Short name T735
Test name
Test status
Simulation time 2609799164 ps
CPU time 7.5 seconds
Started Jun 29 06:32:46 PM PDT 24
Finished Jun 29 06:32:54 PM PDT 24
Peak memory 201520 kb
Host smart-3a818c15-296c-4710-9fd1-4b06474a2a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13712877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.13712877
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.2137870974
Short name T674
Test name
Test status
Simulation time 2523399272 ps
CPU time 1.47 seconds
Started Jun 29 06:32:55 PM PDT 24
Finished Jun 29 06:32:57 PM PDT 24
Peak memory 201504 kb
Host smart-5eba44ca-b2a5-453a-ab8b-1f6c3e284cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137870974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.2137870974
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.2049031206
Short name T276
Test name
Test status
Simulation time 2174577526 ps
CPU time 2.03 seconds
Started Jun 29 06:32:58 PM PDT 24
Finished Jun 29 06:33:01 PM PDT 24
Peak memory 200984 kb
Host smart-b881f2d5-4d9e-42df-b6c3-bd30628e155a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049031206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.2049031206
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.495406429
Short name T266
Test name
Test status
Simulation time 2512591562 ps
CPU time 7.32 seconds
Started Jun 29 06:32:52 PM PDT 24
Finished Jun 29 06:33:00 PM PDT 24
Peak memory 201536 kb
Host smart-316bef72-e2b7-4c23-aabe-49d375bdc1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495406429 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.495406429
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.1148613312
Short name T455
Test name
Test status
Simulation time 2111986847 ps
CPU time 5.9 seconds
Started Jun 29 06:32:52 PM PDT 24
Finished Jun 29 06:32:58 PM PDT 24
Peak memory 201448 kb
Host smart-d3ba0236-069f-420d-b372-86e4d584737a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148613312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.1148613312
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.4116572099
Short name T86
Test name
Test status
Simulation time 9072740261 ps
CPU time 3.73 seconds
Started Jun 29 06:32:59 PM PDT 24
Finished Jun 29 06:33:03 PM PDT 24
Peak memory 201548 kb
Host smart-4326a259-38aa-417c-b95e-00eff6a650c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116572099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_s
tress_all.4116572099
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3419016991
Short name T341
Test name
Test status
Simulation time 19315143504 ps
CPU time 47 seconds
Started Jun 29 06:32:47 PM PDT 24
Finished Jun 29 06:33:34 PM PDT 24
Peak memory 210152 kb
Host smart-1174ef32-86c8-4f53-b2d2-271c584b955c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419016991 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.3419016991
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.2957511970
Short name T416
Test name
Test status
Simulation time 584158761344 ps
CPU time 70.66 seconds
Started Jun 29 06:32:54 PM PDT 24
Finished Jun 29 06:34:05 PM PDT 24
Peak memory 201564 kb
Host smart-c0251ce5-8c2a-4d08-9532-7815d22517fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957511970 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ultra_low_pwr.2957511970
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.3901685302
Short name T315
Test name
Test status
Simulation time 2010659221 ps
CPU time 6.12 seconds
Started Jun 29 06:32:49 PM PDT 24
Finished Jun 29 06:32:56 PM PDT 24
Peak memory 201508 kb
Host smart-0f41e4d7-1517-4ad3-9fb1-33c833a814c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901685302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_te
st.3901685302
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.2378157723
Short name T207
Test name
Test status
Simulation time 3048137500 ps
CPU time 2.68 seconds
Started Jun 29 06:32:52 PM PDT 24
Finished Jun 29 06:32:55 PM PDT 24
Peak memory 201592 kb
Host smart-fa197959-c138-41b7-9038-2f9dd74f6b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378157723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.2
378157723
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.2514794297
Short name T49
Test name
Test status
Simulation time 63031004753 ps
CPU time 171.49 seconds
Started Jun 29 06:32:52 PM PDT 24
Finished Jun 29 06:35:44 PM PDT 24
Peak memory 201776 kb
Host smart-63b3092a-b998-4339-9f49-a09e8ed6052c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514794297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_combo_detect.2514794297
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.2156322880
Short name T302
Test name
Test status
Simulation time 58130457789 ps
CPU time 142.66 seconds
Started Jun 29 06:32:52 PM PDT 24
Finished Jun 29 06:35:15 PM PDT 24
Peak memory 201860 kb
Host smart-c68ba7ee-4985-452d-80bb-7de9597e85bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156322880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.2156322880
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.2438896389
Short name T752
Test name
Test status
Simulation time 4008807839 ps
CPU time 9.6 seconds
Started Jun 29 06:32:52 PM PDT 24
Finished Jun 29 06:33:02 PM PDT 24
Peak memory 201724 kb
Host smart-29121b51-4fe8-4c4b-89f3-a50fd820dd69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438896389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ec_pwr_on_rst.2438896389
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.2585427428
Short name T226
Test name
Test status
Simulation time 4539766233 ps
CPU time 5.15 seconds
Started Jun 29 06:32:49 PM PDT 24
Finished Jun 29 06:32:54 PM PDT 24
Peak memory 201592 kb
Host smart-f162d3b5-e170-4d27-9817-771f72c04b11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585427428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_edge_detect.2585427428
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1506243930
Short name T618
Test name
Test status
Simulation time 2615612392 ps
CPU time 5.2 seconds
Started Jun 29 06:32:57 PM PDT 24
Finished Jun 29 06:33:03 PM PDT 24
Peak memory 201496 kb
Host smart-b9016ef8-5105-4e7e-81d3-509a85c6349e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506243930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.1506243930
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.1527126574
Short name T700
Test name
Test status
Simulation time 2484231288 ps
CPU time 2.04 seconds
Started Jun 29 06:32:52 PM PDT 24
Finished Jun 29 06:32:55 PM PDT 24
Peak memory 201456 kb
Host smart-5b1e176f-41d2-462b-a4af-924c217c1a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527126574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.1527126574
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.590461588
Short name T269
Test name
Test status
Simulation time 2277355952 ps
CPU time 2.12 seconds
Started Jun 29 06:32:58 PM PDT 24
Finished Jun 29 06:33:01 PM PDT 24
Peak memory 201156 kb
Host smart-9ce0d9b1-bd7d-47ea-8dfe-556295034467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590461588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.590461588
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.1812129394
Short name T522
Test name
Test status
Simulation time 2551232904 ps
CPU time 1.44 seconds
Started Jun 29 06:32:54 PM PDT 24
Finished Jun 29 06:32:56 PM PDT 24
Peak memory 201516 kb
Host smart-887096ff-4620-4fff-ab79-8dcc9eacde81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812129394 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.1812129394
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.748356720
Short name T530
Test name
Test status
Simulation time 2132063231 ps
CPU time 2.07 seconds
Started Jun 29 06:32:59 PM PDT 24
Finished Jun 29 06:33:02 PM PDT 24
Peak memory 201436 kb
Host smart-a5331ef8-21b4-4e44-b0d2-907cf78b9239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748356720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.748356720
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.1182609256
Short name T417
Test name
Test status
Simulation time 723080272591 ps
CPU time 91.51 seconds
Started Jun 29 06:32:54 PM PDT 24
Finished Jun 29 06:34:26 PM PDT 24
Peak memory 201588 kb
Host smart-c34afe76-1bf5-4dbe-a720-f12ca2d25196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182609256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_s
tress_all.1182609256
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.2576772941
Short name T28
Test name
Test status
Simulation time 46350872372 ps
CPU time 120.63 seconds
Started Jun 29 06:32:58 PM PDT 24
Finished Jun 29 06:34:59 PM PDT 24
Peak memory 210240 kb
Host smart-2e14d731-4d32-405c-acb1-33a12708f00d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576772941 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.2576772941
Directory /workspace/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.1109988087
Short name T650
Test name
Test status
Simulation time 5030336090 ps
CPU time 8.02 seconds
Started Jun 29 06:32:58 PM PDT 24
Finished Jun 29 06:33:07 PM PDT 24
Peak memory 201564 kb
Host smart-2e2b328d-f8b4-4bb3-a955-ff04c817597c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109988087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ultra_low_pwr.1109988087
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.1346483041
Short name T5
Test name
Test status
Simulation time 2041000410 ps
CPU time 1.76 seconds
Started Jun 29 06:33:02 PM PDT 24
Finished Jun 29 06:33:04 PM PDT 24
Peak memory 201524 kb
Host smart-cabbfcdf-1eca-4799-858a-3170b5141ee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346483041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te
st.1346483041
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1215098112
Short name T547
Test name
Test status
Simulation time 3736406681 ps
CPU time 2.87 seconds
Started Jun 29 06:32:58 PM PDT 24
Finished Jun 29 06:33:02 PM PDT 24
Peak memory 201560 kb
Host smart-81780458-04de-46a6-8b96-406791da72fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215098112 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.1
215098112
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.1282667826
Short name T305
Test name
Test status
Simulation time 111246934656 ps
CPU time 297.6 seconds
Started Jun 29 06:33:00 PM PDT 24
Finished Jun 29 06:37:58 PM PDT 24
Peak memory 201796 kb
Host smart-5dc8fe33-420e-4f60-8a61-e5f5f1ed7474
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282667826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.1282667826
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.3434688116
Short name T130
Test name
Test status
Simulation time 3789688647 ps
CPU time 2.09 seconds
Started Jun 29 06:32:51 PM PDT 24
Finished Jun 29 06:32:54 PM PDT 24
Peak memory 201500 kb
Host smart-2ba9191b-b2ca-484d-901e-ec1299a550e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434688116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.3434688116
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.2836670891
Short name T262
Test name
Test status
Simulation time 4425653467 ps
CPU time 2.6 seconds
Started Jun 29 06:32:49 PM PDT 24
Finished Jun 29 06:32:53 PM PDT 24
Peak memory 201556 kb
Host smart-9bb0666b-4c4e-44ae-baac-fa6866872806
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836670891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ct
rl_edge_detect.2836670891
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.3808015215
Short name T725
Test name
Test status
Simulation time 2621638169 ps
CPU time 2.39 seconds
Started Jun 29 06:32:46 PM PDT 24
Finished Jun 29 06:32:49 PM PDT 24
Peak memory 201524 kb
Host smart-e51f80c8-cb34-462a-afd1-54d36d64f968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808015215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.3808015215
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.3427575784
Short name T566
Test name
Test status
Simulation time 2473315057 ps
CPU time 6.79 seconds
Started Jun 29 06:32:58 PM PDT 24
Finished Jun 29 06:33:06 PM PDT 24
Peak memory 201508 kb
Host smart-3b674c10-be1c-403d-8a33-1b6d5af2a23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427575784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.3427575784
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.1704878949
Short name T626
Test name
Test status
Simulation time 2066861923 ps
CPU time 1.73 seconds
Started Jun 29 06:32:50 PM PDT 24
Finished Jun 29 06:32:53 PM PDT 24
Peak memory 201460 kb
Host smart-2836f536-8a13-4615-95f7-29690f5f9e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704878949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.1704878949
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.1187146259
Short name T267
Test name
Test status
Simulation time 2531630940 ps
CPU time 2.79 seconds
Started Jun 29 06:32:49 PM PDT 24
Finished Jun 29 06:32:52 PM PDT 24
Peak memory 201472 kb
Host smart-a3842e85-fcdd-449e-a374-cfe40ddcc9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187146259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.1187146259
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.1138371695
Short name T676
Test name
Test status
Simulation time 2113277199 ps
CPU time 5.75 seconds
Started Jun 29 06:32:50 PM PDT 24
Finished Jun 29 06:32:57 PM PDT 24
Peak memory 201452 kb
Host smart-6c972d8f-2cde-4063-b2c9-6ffa1b2626fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138371695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.1138371695
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.1556188007
Short name T602
Test name
Test status
Simulation time 17006954024 ps
CPU time 11.28 seconds
Started Jun 29 06:32:58 PM PDT 24
Finished Jun 29 06:33:10 PM PDT 24
Peak memory 201632 kb
Host smart-2c290294-53e3-458e-a1a5-0109a62f2624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556188007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.1556188007
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.3754294320
Short name T124
Test name
Test status
Simulation time 4896528443 ps
CPU time 7.77 seconds
Started Jun 29 06:32:45 PM PDT 24
Finished Jun 29 06:32:53 PM PDT 24
Peak memory 201556 kb
Host smart-73625452-b7f5-4e16-8df9-c264b71a9d16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754294320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.3754294320
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.4132277204
Short name T553
Test name
Test status
Simulation time 2013574886 ps
CPU time 5.78 seconds
Started Jun 29 06:31:33 PM PDT 24
Finished Jun 29 06:31:40 PM PDT 24
Peak memory 201512 kb
Host smart-33f42281-8243-4c97-a438-d036ac3937ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132277204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_tes
t.4132277204
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.2810882295
Short name T531
Test name
Test status
Simulation time 3497879965 ps
CPU time 10.05 seconds
Started Jun 29 06:31:31 PM PDT 24
Finished Jun 29 06:31:41 PM PDT 24
Peak memory 201576 kb
Host smart-07ebf85d-987c-4ed1-8fb1-cc74577229bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810882295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.2810882295
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.2573194428
Short name T92
Test name
Test status
Simulation time 121978258746 ps
CPU time 41.91 seconds
Started Jun 29 06:31:34 PM PDT 24
Finished Jun 29 06:32:16 PM PDT 24
Peak memory 201760 kb
Host smart-3784fc58-a72a-4eb0-99ba-d78303441a33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573194428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_combo_detect.2573194428
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.3204037116
Short name T628
Test name
Test status
Simulation time 2186310204 ps
CPU time 3.27 seconds
Started Jun 29 06:31:33 PM PDT 24
Finished Jun 29 06:31:37 PM PDT 24
Peak memory 201528 kb
Host smart-e7218fb4-d533-491e-851b-7d4d5e7d0715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204037116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.3204037116
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3818574413
Short name T533
Test name
Test status
Simulation time 2534762281 ps
CPU time 2.37 seconds
Started Jun 29 06:31:32 PM PDT 24
Finished Jun 29 06:31:34 PM PDT 24
Peak memory 201500 kb
Host smart-e3c1e188-601d-427f-996d-4302e107aa5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818574413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3818574413
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3475886140
Short name T544
Test name
Test status
Simulation time 2773387813 ps
CPU time 8.51 seconds
Started Jun 29 06:31:35 PM PDT 24
Finished Jun 29 06:31:44 PM PDT 24
Peak memory 201452 kb
Host smart-85535781-1307-45bb-b3d7-a6c1b04c9e64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475886140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ec_pwr_on_rst.3475886140
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.3161059309
Short name T526
Test name
Test status
Simulation time 2610760275 ps
CPU time 7.21 seconds
Started Jun 29 06:31:33 PM PDT 24
Finished Jun 29 06:31:41 PM PDT 24
Peak memory 201512 kb
Host smart-1bb0d7b8-d6fc-43c4-9d61-fe5628c83466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161059309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.3161059309
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.1159640880
Short name T754
Test name
Test status
Simulation time 2458330632 ps
CPU time 3.84 seconds
Started Jun 29 06:31:35 PM PDT 24
Finished Jun 29 06:31:40 PM PDT 24
Peak memory 201536 kb
Host smart-74022217-a3ab-4a45-9741-6c8e34aea33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159640880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.1159640880
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.1066121967
Short name T265
Test name
Test status
Simulation time 2246362935 ps
CPU time 6.74 seconds
Started Jun 29 06:31:36 PM PDT 24
Finished Jun 29 06:31:43 PM PDT 24
Peak memory 201524 kb
Host smart-aa7a110a-75ab-4a5d-a160-c12398168995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066121967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.1066121967
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.772490224
Short name T748
Test name
Test status
Simulation time 2510142831 ps
CPU time 6.81 seconds
Started Jun 29 06:31:35 PM PDT 24
Finished Jun 29 06:31:43 PM PDT 24
Peak memory 201536 kb
Host smart-b779effa-f401-44c4-9c69-a99b2297dfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772490224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.772490224
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.1568340097
Short name T320
Test name
Test status
Simulation time 22010730998 ps
CPU time 59.39 seconds
Started Jun 29 06:31:36 PM PDT 24
Finished Jun 29 06:32:36 PM PDT 24
Peak memory 221272 kb
Host smart-da6b8a48-a28d-4d03-aa38-67fd77e9f10d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568340097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.1568340097
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.2816248240
Short name T490
Test name
Test status
Simulation time 2109298870 ps
CPU time 6.15 seconds
Started Jun 29 06:31:31 PM PDT 24
Finished Jun 29 06:31:38 PM PDT 24
Peak memory 201448 kb
Host smart-68d18cea-61f3-48a2-adb4-cb7f40cc7bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816248240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.2816248240
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.3318638946
Short name T43
Test name
Test status
Simulation time 7461663341 ps
CPU time 6.14 seconds
Started Jun 29 06:31:33 PM PDT 24
Finished Jun 29 06:31:40 PM PDT 24
Peak memory 201488 kb
Host smart-3c541f69-9c9c-4e24-95a1-348baa22f2c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318638946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_st
ress_all.3318638946
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.952568919
Short name T114
Test name
Test status
Simulation time 5521695385 ps
CPU time 5.68 seconds
Started Jun 29 06:31:37 PM PDT 24
Finished Jun 29 06:31:43 PM PDT 24
Peak memory 201548 kb
Host smart-63ce84d1-0852-4888-91e9-9cd3cca78dea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952568919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_ultra_low_pwr.952568919
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.2751961296
Short name T501
Test name
Test status
Simulation time 2018117811 ps
CPU time 5.61 seconds
Started Jun 29 06:32:58 PM PDT 24
Finished Jun 29 06:33:04 PM PDT 24
Peak memory 201516 kb
Host smart-e9767557-27fd-4b46-bf91-92452abc2851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751961296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_te
st.2751961296
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3788872564
Short name T551
Test name
Test status
Simulation time 3800170037 ps
CPU time 3.1 seconds
Started Jun 29 06:32:56 PM PDT 24
Finished Jun 29 06:32:59 PM PDT 24
Peak memory 201584 kb
Host smart-6d65ae07-dc87-4898-a19e-0d909daa037f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788872564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.3
788872564
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.3615457146
Short name T253
Test name
Test status
Simulation time 92844057430 ps
CPU time 126.61 seconds
Started Jun 29 06:32:59 PM PDT 24
Finished Jun 29 06:35:06 PM PDT 24
Peak memory 201832 kb
Host smart-b1a17435-4483-45d0-8a12-189d5ede011d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615457146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.3615457146
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.4224774472
Short name T287
Test name
Test status
Simulation time 92983002332 ps
CPU time 16.53 seconds
Started Jun 29 06:33:03 PM PDT 24
Finished Jun 29 06:33:20 PM PDT 24
Peak memory 201784 kb
Host smart-8fb81d5f-da80-43d8-b562-239bab3de87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224774472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w
ith_pre_cond.4224774472
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2380514285
Short name T6
Test name
Test status
Simulation time 2687520788 ps
CPU time 7.09 seconds
Started Jun 29 06:33:01 PM PDT 24
Finished Jun 29 06:33:09 PM PDT 24
Peak memory 201500 kb
Host smart-0f0e9255-7840-467c-a138-25a20fd62551
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380514285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ec_pwr_on_rst.2380514285
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.2565877221
Short name T183
Test name
Test status
Simulation time 5185191423 ps
CPU time 7.53 seconds
Started Jun 29 06:32:55 PM PDT 24
Finished Jun 29 06:33:03 PM PDT 24
Peak memory 201544 kb
Host smart-6ab9d793-9406-4ec0-83a6-7755f8c3c43d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565877221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_edge_detect.2565877221
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2994586459
Short name T428
Test name
Test status
Simulation time 2608912252 ps
CPU time 7.4 seconds
Started Jun 29 06:33:01 PM PDT 24
Finished Jun 29 06:33:09 PM PDT 24
Peak memory 201484 kb
Host smart-1f3769a3-c1ba-48ec-b6f2-56e505193d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994586459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.2994586459
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.3881994638
Short name T731
Test name
Test status
Simulation time 2454839197 ps
CPU time 6.82 seconds
Started Jun 29 06:32:59 PM PDT 24
Finished Jun 29 06:33:06 PM PDT 24
Peak memory 201496 kb
Host smart-436db5bc-2c27-4f7d-bd59-76836ed212d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881994638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.3881994638
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.2144153192
Short name T552
Test name
Test status
Simulation time 2236368027 ps
CPU time 3.39 seconds
Started Jun 29 06:32:58 PM PDT 24
Finished Jun 29 06:33:02 PM PDT 24
Peak memory 201540 kb
Host smart-14d96858-be11-4703-9943-7e75b1995f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144153192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.2144153192
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.918151249
Short name T351
Test name
Test status
Simulation time 2510871719 ps
CPU time 7.65 seconds
Started Jun 29 06:32:58 PM PDT 24
Finished Jun 29 06:33:06 PM PDT 24
Peak memory 201448 kb
Host smart-dcfe5ccf-669e-411f-b880-26d42a19d054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918151249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.918151249
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.1107538201
Short name T568
Test name
Test status
Simulation time 2112809739 ps
CPU time 3.45 seconds
Started Jun 29 06:32:59 PM PDT 24
Finished Jun 29 06:33:03 PM PDT 24
Peak memory 201444 kb
Host smart-7e266abe-8d61-4cc6-95a7-a458415be132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107538201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.1107538201
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.2218743156
Short name T275
Test name
Test status
Simulation time 2067598306 ps
CPU time 1.33 seconds
Started Jun 29 06:32:54 PM PDT 24
Finished Jun 29 06:32:56 PM PDT 24
Peak memory 201504 kb
Host smart-a6b4d9df-518f-4d13-81f6-75d7292dd683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218743156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_te
st.2218743156
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.1615764944
Short name T685
Test name
Test status
Simulation time 3743159227 ps
CPU time 10 seconds
Started Jun 29 06:33:02 PM PDT 24
Finished Jun 29 06:33:12 PM PDT 24
Peak memory 201604 kb
Host smart-eef6f149-b33a-4e44-9d3a-bc61d507815e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615764944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.1
615764944
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.396176156
Short name T307
Test name
Test status
Simulation time 164837740176 ps
CPU time 105.72 seconds
Started Jun 29 06:32:58 PM PDT 24
Finished Jun 29 06:34:45 PM PDT 24
Peak memory 201828 kb
Host smart-46e0d7e9-7c8a-4cde-81da-103a456d2cd2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396176156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_combo_detect.396176156
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.3903598589
Short name T296
Test name
Test status
Simulation time 35088383705 ps
CPU time 21.59 seconds
Started Jun 29 06:33:02 PM PDT 24
Finished Jun 29 06:33:25 PM PDT 24
Peak memory 201856 kb
Host smart-5355aa46-2f3a-4e18-8722-b1624f19b624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903598589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_w
ith_pre_cond.3903598589
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.3577302029
Short name T577
Test name
Test status
Simulation time 3591313093 ps
CPU time 2.83 seconds
Started Jun 29 06:33:01 PM PDT 24
Finished Jun 29 06:33:04 PM PDT 24
Peak memory 201452 kb
Host smart-9046c502-4198-4fa5-ae5a-54229e69e5c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577302029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ec_pwr_on_rst.3577302029
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.430895993
Short name T750
Test name
Test status
Simulation time 2687025084 ps
CPU time 6.87 seconds
Started Jun 29 06:32:56 PM PDT 24
Finished Jun 29 06:33:04 PM PDT 24
Peak memory 201456 kb
Host smart-166dfe78-6071-447c-80ff-e727b3c2a27e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430895993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctr
l_edge_detect.430895993
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1284759553
Short name T614
Test name
Test status
Simulation time 2611586201 ps
CPU time 7.37 seconds
Started Jun 29 06:32:55 PM PDT 24
Finished Jun 29 06:33:03 PM PDT 24
Peak memory 201520 kb
Host smart-0d85b356-3f26-4a76-9e48-2d5ab4970eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284759553 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.1284759553
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.3124230255
Short name T736
Test name
Test status
Simulation time 2486992895 ps
CPU time 2.39 seconds
Started Jun 29 06:32:57 PM PDT 24
Finished Jun 29 06:33:00 PM PDT 24
Peak memory 201452 kb
Host smart-43e70345-6f7d-447d-a2b2-5dcb8ea336c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124230255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.3124230255
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.2157867560
Short name T165
Test name
Test status
Simulation time 2094758888 ps
CPU time 2.09 seconds
Started Jun 29 06:32:57 PM PDT 24
Finished Jun 29 06:33:00 PM PDT 24
Peak memory 201384 kb
Host smart-8b80c8a8-1789-4664-a74d-e5cfc2472905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157867560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.2157867560
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.1506103017
Short name T420
Test name
Test status
Simulation time 2524470617 ps
CPU time 2.24 seconds
Started Jun 29 06:32:57 PM PDT 24
Finished Jun 29 06:33:00 PM PDT 24
Peak memory 201516 kb
Host smart-d959e0b5-deec-40e3-9f11-f7276d6c77c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506103017 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.1506103017
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.3321848197
Short name T677
Test name
Test status
Simulation time 2131807921 ps
CPU time 1.88 seconds
Started Jun 29 06:32:58 PM PDT 24
Finished Jun 29 06:33:00 PM PDT 24
Peak memory 201436 kb
Host smart-9183692a-a341-4d87-aa3b-b60316dc68b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321848197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.3321848197
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.2235916185
Short name T280
Test name
Test status
Simulation time 12485245483 ps
CPU time 33.52 seconds
Started Jun 29 06:32:59 PM PDT 24
Finished Jun 29 06:33:33 PM PDT 24
Peak memory 201552 kb
Host smart-19f46601-e04d-43ca-87e0-1fae869f87b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235916185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_s
tress_all.2235916185
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.3731189827
Short name T205
Test name
Test status
Simulation time 63416119205 ps
CPU time 41.61 seconds
Started Jun 29 06:32:57 PM PDT 24
Finished Jun 29 06:33:39 PM PDT 24
Peak memory 210184 kb
Host smart-53593264-ece0-4105-a324-2a2dda770c70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731189827 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.3731189827
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1755406393
Short name T118
Test name
Test status
Simulation time 5787257301 ps
CPU time 3.87 seconds
Started Jun 29 06:33:02 PM PDT 24
Finished Jun 29 06:33:07 PM PDT 24
Peak memory 201516 kb
Host smart-5ce7e6fb-ebab-47b7-ac3e-edb3c8e13902
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755406393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ultra_low_pwr.1755406393
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.1359944664
Short name T631
Test name
Test status
Simulation time 2017754405 ps
CPU time 3.1 seconds
Started Jun 29 06:33:13 PM PDT 24
Finished Jun 29 06:33:17 PM PDT 24
Peak memory 201428 kb
Host smart-1d2bad0a-1d5d-4125-a347-493e14a3613e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359944664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_te
st.1359944664
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.1891323423
Short name T201
Test name
Test status
Simulation time 3208519905 ps
CPU time 2.71 seconds
Started Jun 29 06:33:01 PM PDT 24
Finished Jun 29 06:33:05 PM PDT 24
Peak memory 201576 kb
Host smart-86eea7bc-1b2e-485a-8864-868e0ed668cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891323423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.1
891323423
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.1187305407
Short name T654
Test name
Test status
Simulation time 141768779729 ps
CPU time 98.29 seconds
Started Jun 29 06:33:05 PM PDT 24
Finished Jun 29 06:34:43 PM PDT 24
Peak memory 201760 kb
Host smart-e498df78-fc4a-4854-b52e-bb61663ba528
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187305407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.1187305407
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.1646519297
Short name T771
Test name
Test status
Simulation time 26108083782 ps
CPU time 19.17 seconds
Started Jun 29 06:33:04 PM PDT 24
Finished Jun 29 06:33:24 PM PDT 24
Peak memory 201852 kb
Host smart-958a1972-63d8-46bb-89e3-70224b05cd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646519297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_w
ith_pre_cond.1646519297
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3754414520
Short name T680
Test name
Test status
Simulation time 3778374630 ps
CPU time 5.69 seconds
Started Jun 29 06:33:01 PM PDT 24
Finished Jun 29 06:33:08 PM PDT 24
Peak memory 201476 kb
Host smart-c9a6280c-bdf4-4b22-b133-cdfbe663277e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754414520 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ec_pwr_on_rst.3754414520
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.2380136174
Short name T705
Test name
Test status
Simulation time 2397397715 ps
CPU time 5.9 seconds
Started Jun 29 06:33:03 PM PDT 24
Finished Jun 29 06:33:10 PM PDT 24
Peak memory 201456 kb
Host smart-a4e78cc1-bd8d-45ba-bede-8116499f9407
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380136174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_edge_detect.2380136174
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.1055946843
Short name T516
Test name
Test status
Simulation time 2646906237 ps
CPU time 1.43 seconds
Started Jun 29 06:32:57 PM PDT 24
Finished Jun 29 06:32:59 PM PDT 24
Peak memory 201504 kb
Host smart-9e5e00de-9e1c-4166-9efc-c6e1395948e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055946843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.1055946843
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2912085895
Short name T312
Test name
Test status
Simulation time 2484259528 ps
CPU time 2.34 seconds
Started Jun 29 06:33:00 PM PDT 24
Finished Jun 29 06:33:02 PM PDT 24
Peak memory 201536 kb
Host smart-dc7705b2-fda2-4f6c-82ad-956767945a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912085895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.2912085895
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3121324972
Short name T710
Test name
Test status
Simulation time 2233826860 ps
CPU time 3.4 seconds
Started Jun 29 06:33:01 PM PDT 24
Finished Jun 29 06:33:05 PM PDT 24
Peak memory 201484 kb
Host smart-58415519-faf6-4382-8402-cad920eba3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121324972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.3121324972
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.3327126004
Short name T459
Test name
Test status
Simulation time 2519118937 ps
CPU time 3.15 seconds
Started Jun 29 06:32:56 PM PDT 24
Finished Jun 29 06:33:00 PM PDT 24
Peak memory 201520 kb
Host smart-2e705443-e02b-4c84-9f88-b279992a6aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327126004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.3327126004
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.2753031160
Short name T448
Test name
Test status
Simulation time 2203174855 ps
CPU time 1.04 seconds
Started Jun 29 06:32:54 PM PDT 24
Finished Jun 29 06:32:55 PM PDT 24
Peak memory 201488 kb
Host smart-36e8b821-1375-4c96-9683-b9896715cd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753031160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.2753031160
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.588713773
Short name T309
Test name
Test status
Simulation time 65877434918 ps
CPU time 135.51 seconds
Started Jun 29 06:33:12 PM PDT 24
Finished Jun 29 06:35:28 PM PDT 24
Peak memory 201844 kb
Host smart-9d0ebe85-c6c7-42be-9022-7a09bca62dcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588713773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_st
ress_all.588713773
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.1718070324
Short name T630
Test name
Test status
Simulation time 2017761294 ps
CPU time 2.92 seconds
Started Jun 29 06:33:01 PM PDT 24
Finished Jun 29 06:33:04 PM PDT 24
Peak memory 201516 kb
Host smart-4423f005-8fd5-44fd-826e-06f1a9e3281e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718070324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_te
st.1718070324
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.2923232366
Short name T543
Test name
Test status
Simulation time 119386757461 ps
CPU time 308.47 seconds
Started Jun 29 06:33:12 PM PDT 24
Finished Jun 29 06:38:22 PM PDT 24
Peak memory 201656 kb
Host smart-e9c8f2ab-c82b-4dd5-a436-1a37d456e348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923232366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.2
923232366
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.745440352
Short name T293
Test name
Test status
Simulation time 83132890239 ps
CPU time 103.28 seconds
Started Jun 29 06:33:03 PM PDT 24
Finished Jun 29 06:34:47 PM PDT 24
Peak memory 201816 kb
Host smart-daae136f-22cb-446d-b7a4-62c39871002f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745440352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_combo_detect.745440352
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.1353295760
Short name T562
Test name
Test status
Simulation time 27834675158 ps
CPU time 74.32 seconds
Started Jun 29 06:33:06 PM PDT 24
Finished Jun 29 06:34:21 PM PDT 24
Peak memory 201876 kb
Host smart-d69cfdeb-b5d1-465b-9e9b-a9e76a933987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353295760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_w
ith_pre_cond.1353295760
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3175795913
Short name T431
Test name
Test status
Simulation time 4596146299 ps
CPU time 12.77 seconds
Started Jun 29 06:33:05 PM PDT 24
Finished Jun 29 06:33:18 PM PDT 24
Peak memory 201560 kb
Host smart-b7c0aa66-5d9d-4080-b9f3-f6da51940d91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175795913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.3175795913
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.677390323
Short name T181
Test name
Test status
Simulation time 1633034448737 ps
CPU time 328.35 seconds
Started Jun 29 06:33:04 PM PDT 24
Finished Jun 29 06:38:33 PM PDT 24
Peak memory 201560 kb
Host smart-0dc9829f-9b09-41fa-9e15-ef84580b7444
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677390323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctr
l_edge_detect.677390323
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.487889800
Short name T560
Test name
Test status
Simulation time 2610273686 ps
CPU time 6.95 seconds
Started Jun 29 06:33:10 PM PDT 24
Finished Jun 29 06:33:17 PM PDT 24
Peak memory 201524 kb
Host smart-4b4bb302-0f35-4d4c-b47d-391ccfb83baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487889800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.487889800
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.957292741
Short name T648
Test name
Test status
Simulation time 2463246930 ps
CPU time 8.31 seconds
Started Jun 29 06:33:04 PM PDT 24
Finished Jun 29 06:33:13 PM PDT 24
Peak memory 201512 kb
Host smart-861e6ec9-37c6-4008-96cb-cb04122be87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957292741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.957292741
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.2076263684
Short name T196
Test name
Test status
Simulation time 2037845904 ps
CPU time 6.04 seconds
Started Jun 29 06:33:13 PM PDT 24
Finished Jun 29 06:33:20 PM PDT 24
Peak memory 201468 kb
Host smart-af90abb6-1306-40e0-a4b9-cb21a9a2efd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076263684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.2076263684
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.2827676429
Short name T565
Test name
Test status
Simulation time 2532673624 ps
CPU time 1.95 seconds
Started Jun 29 06:33:04 PM PDT 24
Finished Jun 29 06:33:06 PM PDT 24
Peak memory 201524 kb
Host smart-baa13dc6-7bdc-4ac6-b8d4-90554bed49e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827676429 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.2827676429
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.1812975764
Short name T643
Test name
Test status
Simulation time 2133181409 ps
CPU time 1.98 seconds
Started Jun 29 06:33:07 PM PDT 24
Finished Jun 29 06:33:09 PM PDT 24
Peak memory 201672 kb
Host smart-0fc59615-bdcd-4b54-b6c2-0ab6f0c36017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812975764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.1812975764
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.3816968577
Short name T737
Test name
Test status
Simulation time 7901633993 ps
CPU time 1.97 seconds
Started Jun 29 06:33:09 PM PDT 24
Finished Jun 29 06:33:12 PM PDT 24
Peak memory 201556 kb
Host smart-dd0c7983-4c14-4aa4-b509-4d6cb6b236ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816968577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_s
tress_all.3816968577
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1309250653
Short name T76
Test name
Test status
Simulation time 5945414244 ps
CPU time 2.45 seconds
Started Jun 29 06:33:02 PM PDT 24
Finished Jun 29 06:33:06 PM PDT 24
Peak memory 201556 kb
Host smart-76c7c632-b3d3-4526-83bf-5d4639b8ac17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309250653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ultra_low_pwr.1309250653
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.2890071658
Short name T616
Test name
Test status
Simulation time 2039983342 ps
CPU time 1.91 seconds
Started Jun 29 06:33:13 PM PDT 24
Finished Jun 29 06:33:15 PM PDT 24
Peak memory 201524 kb
Host smart-73b979da-cc75-49b5-8d16-a6ae39a0375e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890071658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_te
st.2890071658
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3180998989
Short name T696
Test name
Test status
Simulation time 136829766438 ps
CPU time 352.35 seconds
Started Jun 29 06:33:02 PM PDT 24
Finished Jun 29 06:38:55 PM PDT 24
Peak memory 201676 kb
Host smart-748966d2-25fa-44df-891d-19b70ac37796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180998989 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.3
180998989
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.1272165812
Short name T304
Test name
Test status
Simulation time 122692021738 ps
CPU time 84.75 seconds
Started Jun 29 06:33:04 PM PDT 24
Finished Jun 29 06:34:30 PM PDT 24
Peak memory 201708 kb
Host smart-37363a27-2a11-4955-9127-ffced6875316
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272165812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_combo_detect.1272165812
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.4222284876
Short name T186
Test name
Test status
Simulation time 3871510511 ps
CPU time 5.67 seconds
Started Jun 29 06:33:02 PM PDT 24
Finished Jun 29 06:33:08 PM PDT 24
Peak memory 201500 kb
Host smart-38f8fd17-f589-4c88-90c4-2aacbe7b2368
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222284876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ec_pwr_on_rst.4222284876
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.2757029978
Short name T743
Test name
Test status
Simulation time 2953178840 ps
CPU time 3.17 seconds
Started Jun 29 06:33:03 PM PDT 24
Finished Jun 29 06:33:07 PM PDT 24
Peak memory 201508 kb
Host smart-9b756e84-28eb-4478-ba63-9943abbc34df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757029978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.2757029978
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1445187320
Short name T520
Test name
Test status
Simulation time 2610453211 ps
CPU time 6.97 seconds
Started Jun 29 06:33:02 PM PDT 24
Finished Jun 29 06:33:10 PM PDT 24
Peak memory 201476 kb
Host smart-6ffb5903-2356-436d-a7c6-ddee05d7a69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445187320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.1445187320
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3280621216
Short name T256
Test name
Test status
Simulation time 2469563792 ps
CPU time 2.56 seconds
Started Jun 29 06:33:06 PM PDT 24
Finished Jun 29 06:33:09 PM PDT 24
Peak memory 201724 kb
Host smart-c78f2e60-0934-4a1c-8f48-2d227347bd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280621216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.3280621216
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3762039115
Short name T549
Test name
Test status
Simulation time 2062873410 ps
CPU time 5.88 seconds
Started Jun 29 06:33:07 PM PDT 24
Finished Jun 29 06:33:13 PM PDT 24
Peak memory 201444 kb
Host smart-f92ed4dc-eda2-43d0-87e0-9b925ff1a91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762039115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.3762039115
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.866601420
Short name T272
Test name
Test status
Simulation time 2544159890 ps
CPU time 1.61 seconds
Started Jun 29 06:33:01 PM PDT 24
Finished Jun 29 06:33:03 PM PDT 24
Peak memory 201520 kb
Host smart-59d28045-dfea-4b2d-85d7-78e673f9f31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866601420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.866601420
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.3995412895
Short name T597
Test name
Test status
Simulation time 2112027917 ps
CPU time 5.54 seconds
Started Jun 29 06:33:03 PM PDT 24
Finished Jun 29 06:33:10 PM PDT 24
Peak memory 201448 kb
Host smart-29869ad5-d3f7-4eeb-9669-9b17cc9c18af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995412895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.3995412895
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.3539392752
Short name T493
Test name
Test status
Simulation time 12284204762 ps
CPU time 29.5 seconds
Started Jun 29 06:33:04 PM PDT 24
Finished Jun 29 06:33:34 PM PDT 24
Peak memory 201484 kb
Host smart-7dc3ad38-66ed-4a98-b492-13f626c96b9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539392752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.3539392752
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3119823062
Short name T354
Test name
Test status
Simulation time 21310147163 ps
CPU time 42.9 seconds
Started Jun 29 06:33:12 PM PDT 24
Finished Jun 29 06:33:56 PM PDT 24
Peak memory 210148 kb
Host smart-b201d1b9-2a2a-4443-bede-3e42cf0bcb71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119823062 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.3119823062
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.4037051778
Short name T198
Test name
Test status
Simulation time 6187730278 ps
CPU time 7.22 seconds
Started Jun 29 06:33:04 PM PDT 24
Finished Jun 29 06:33:12 PM PDT 24
Peak memory 201544 kb
Host smart-7dca677a-e633-4916-a67c-0ea5b09ae247
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037051778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ultra_low_pwr.4037051778
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.2716420212
Short name T718
Test name
Test status
Simulation time 2031297162 ps
CPU time 1.86 seconds
Started Jun 29 06:33:10 PM PDT 24
Finished Jun 29 06:33:12 PM PDT 24
Peak memory 201512 kb
Host smart-5287d236-768f-4e6f-adf1-8fccf97234ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716420212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_te
st.2716420212
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1166247719
Short name T339
Test name
Test status
Simulation time 3013660999 ps
CPU time 8.55 seconds
Started Jun 29 06:33:01 PM PDT 24
Finished Jun 29 06:33:10 PM PDT 24
Peak memory 201616 kb
Host smart-cd1471a6-1945-4aac-9b94-1a757fb541db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166247719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.1
166247719
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.3717349010
Short name T231
Test name
Test status
Simulation time 180081801359 ps
CPU time 470.1 seconds
Started Jun 29 06:33:05 PM PDT 24
Finished Jun 29 06:40:56 PM PDT 24
Peak memory 201048 kb
Host smart-d2d103b8-79de-4175-a1d9-2f4944ab76e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717349010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.3717349010
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.854587589
Short name T609
Test name
Test status
Simulation time 26169598429 ps
CPU time 8.55 seconds
Started Jun 29 06:33:03 PM PDT 24
Finished Jun 29 06:33:13 PM PDT 24
Peak memory 201844 kb
Host smart-7f650360-01de-4531-8c32-69be560a0437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854587589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_wi
th_pre_cond.854587589
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.277304134
Short name T617
Test name
Test status
Simulation time 3955931283 ps
CPU time 1.78 seconds
Started Jun 29 06:33:03 PM PDT 24
Finished Jun 29 06:33:06 PM PDT 24
Peak memory 201484 kb
Host smart-7c3376a5-ead2-4fbb-8849-231c288c7b9a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277304134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_ec_pwr_on_rst.277304134
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.2822202978
Short name T283
Test name
Test status
Simulation time 4686047226 ps
CPU time 8.35 seconds
Started Jun 29 06:33:04 PM PDT 24
Finished Jun 29 06:33:13 PM PDT 24
Peak memory 201560 kb
Host smart-210133a2-c331-4382-a4f1-c08ee133a9dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822202978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_edge_detect.2822202978
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2341758180
Short name T587
Test name
Test status
Simulation time 2634645768 ps
CPU time 2.5 seconds
Started Jun 29 06:33:05 PM PDT 24
Finished Jun 29 06:33:08 PM PDT 24
Peak memory 201520 kb
Host smart-1a4c6590-b38b-47c3-89bf-81e62029eefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341758180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.2341758180
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.1936389555
Short name T497
Test name
Test status
Simulation time 2471016242 ps
CPU time 4 seconds
Started Jun 29 06:33:02 PM PDT 24
Finished Jun 29 06:33:06 PM PDT 24
Peak memory 201524 kb
Host smart-496d1c6a-b612-4171-b080-e04fa656fa97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936389555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.1936389555
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.1250775018
Short name T782
Test name
Test status
Simulation time 2095999074 ps
CPU time 6.24 seconds
Started Jun 29 06:33:01 PM PDT 24
Finished Jun 29 06:33:08 PM PDT 24
Peak memory 201432 kb
Host smart-518dd82b-10b8-4182-9bf5-b6527f5fe91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250775018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.1250775018
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.4168930716
Short name T729
Test name
Test status
Simulation time 2511822616 ps
CPU time 7.8 seconds
Started Jun 29 06:33:03 PM PDT 24
Finished Jun 29 06:33:12 PM PDT 24
Peak memory 201520 kb
Host smart-6badca3e-4e64-4bd2-b4f5-f2067c9a29f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168930716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.4168930716
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.4034227075
Short name T445
Test name
Test status
Simulation time 2138375602 ps
CPU time 1.78 seconds
Started Jun 29 06:33:05 PM PDT 24
Finished Jun 29 06:33:07 PM PDT 24
Peak memory 200712 kb
Host smart-42e64c94-72bb-481d-a52f-639b31ee5f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034227075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.4034227075
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.2071764023
Short name T672
Test name
Test status
Simulation time 12459612399 ps
CPU time 8.09 seconds
Started Jun 29 06:33:07 PM PDT 24
Finished Jun 29 06:33:15 PM PDT 24
Peak memory 201544 kb
Host smart-9c093d3e-b84a-446a-93e1-b32432aa5933
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071764023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s
tress_all.2071764023
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3854347513
Short name T418
Test name
Test status
Simulation time 83032719229 ps
CPU time 44.44 seconds
Started Jun 29 06:33:03 PM PDT 24
Finished Jun 29 06:33:48 PM PDT 24
Peak memory 210152 kb
Host smart-a22f71f3-e841-47e1-be00-febc264bfd4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854347513 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.3854347513
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.1739249371
Short name T437
Test name
Test status
Simulation time 2012988973 ps
CPU time 6.16 seconds
Started Jun 29 06:33:12 PM PDT 24
Finished Jun 29 06:33:19 PM PDT 24
Peak memory 201508 kb
Host smart-f637ddf2-dfb2-4d90-a401-7a3400c5e350
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739249371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.1739249371
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3178140149
Short name T54
Test name
Test status
Simulation time 3332335480 ps
CPU time 4.79 seconds
Started Jun 29 06:33:09 PM PDT 24
Finished Jun 29 06:33:14 PM PDT 24
Peak memory 201576 kb
Host smart-8366ad3d-de2c-4d60-9cf4-af444dfb1935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178140149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.3
178140149
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.1368531348
Short name T32
Test name
Test status
Simulation time 118729367181 ps
CPU time 300.4 seconds
Started Jun 29 06:33:12 PM PDT 24
Finished Jun 29 06:38:14 PM PDT 24
Peak memory 201760 kb
Host smart-ca8ba53a-c4cd-4384-94c9-01bdab6eea0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368531348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_combo_detect.1368531348
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.603931579
Short name T109
Test name
Test status
Simulation time 2692286224 ps
CPU time 2.51 seconds
Started Jun 29 06:33:13 PM PDT 24
Finished Jun 29 06:33:16 PM PDT 24
Peak memory 201492 kb
Host smart-025e56a2-2cea-40d4-b597-0b158d24c1be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603931579 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_ec_pwr_on_rst.603931579
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.2384260772
Short name T242
Test name
Test status
Simulation time 5998336820 ps
CPU time 3.05 seconds
Started Jun 29 06:33:10 PM PDT 24
Finished Jun 29 06:33:14 PM PDT 24
Peak memory 201520 kb
Host smart-5ceb664b-9cc2-45b3-abd8-47eb0c435536
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384260772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.2384260772
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.982079874
Short name T625
Test name
Test status
Simulation time 2609251725 ps
CPU time 7.46 seconds
Started Jun 29 06:33:10 PM PDT 24
Finished Jun 29 06:33:18 PM PDT 24
Peak memory 201532 kb
Host smart-d8574189-f5ce-4bb5-afef-f9e310c53ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982079874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.982079874
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3702016671
Short name T347
Test name
Test status
Simulation time 2472381983 ps
CPU time 6.83 seconds
Started Jun 29 06:33:03 PM PDT 24
Finished Jun 29 06:33:11 PM PDT 24
Peak memory 201476 kb
Host smart-650ce84b-91df-4cdd-90d8-2a9c7a290a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702016671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.3702016671
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2821122925
Short name T523
Test name
Test status
Simulation time 2044145594 ps
CPU time 1.79 seconds
Started Jun 29 06:33:10 PM PDT 24
Finished Jun 29 06:33:12 PM PDT 24
Peak memory 201448 kb
Host smart-0da6bad1-cee9-48c9-a978-a2aaea4c7f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821122925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.2821122925
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2104300806
Short name T726
Test name
Test status
Simulation time 2679201891 ps
CPU time 1.19 seconds
Started Jun 29 06:33:08 PM PDT 24
Finished Jun 29 06:33:10 PM PDT 24
Peak memory 201520 kb
Host smart-c18d3af4-1a28-4678-a410-6099312002e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104300806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.2104300806
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.1401396308
Short name T222
Test name
Test status
Simulation time 2135431763 ps
CPU time 1.93 seconds
Started Jun 29 06:33:10 PM PDT 24
Finished Jun 29 06:33:12 PM PDT 24
Peak memory 201452 kb
Host smart-0ff7c540-1a4c-4df9-b6f7-2efa1911e933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401396308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.1401396308
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.2666853906
Short name T345
Test name
Test status
Simulation time 11585192282 ps
CPU time 8.36 seconds
Started Jun 29 06:33:11 PM PDT 24
Finished Jun 29 06:33:20 PM PDT 24
Peak memory 201600 kb
Host smart-06b3265d-f4d5-4fba-a0f0-3252cc34a71d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666853906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_s
tress_all.2666853906
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3611278693
Short name T147
Test name
Test status
Simulation time 2729680447 ps
CPU time 3.41 seconds
Started Jun 29 06:33:11 PM PDT 24
Finished Jun 29 06:33:15 PM PDT 24
Peak memory 201436 kb
Host smart-f78fb588-46c5-4f54-ba4a-cdbbf5a8f738
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611278693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ultra_low_pwr.3611278693
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.1843577552
Short name T67
Test name
Test status
Simulation time 2023192207 ps
CPU time 1.74 seconds
Started Jun 29 06:33:11 PM PDT 24
Finished Jun 29 06:33:13 PM PDT 24
Peak memory 201428 kb
Host smart-0c0ebb12-0928-4023-86e0-6cb87f5f3526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843577552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.1843577552
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1255736597
Short name T487
Test name
Test status
Simulation time 3299524171 ps
CPU time 2.55 seconds
Started Jun 29 06:33:10 PM PDT 24
Finished Jun 29 06:33:14 PM PDT 24
Peak memory 201560 kb
Host smart-ee06e19e-9167-4be7-8c91-56c5043a4f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255736597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.1
255736597
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.3996295050
Short name T381
Test name
Test status
Simulation time 174986788158 ps
CPU time 85.85 seconds
Started Jun 29 06:33:11 PM PDT 24
Finished Jun 29 06:34:38 PM PDT 24
Peak memory 201836 kb
Host smart-747dd8dd-a49f-4b03-8350-18a77a4db32f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996295050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.3996295050
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3529605025
Short name T235
Test name
Test status
Simulation time 26328965696 ps
CPU time 72.29 seconds
Started Jun 29 06:33:10 PM PDT 24
Finished Jun 29 06:34:23 PM PDT 24
Peak memory 201824 kb
Host smart-1d30d57c-eb97-4a83-8f42-2eb664581075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529605025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_w
ith_pre_cond.3529605025
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.737976362
Short name T585
Test name
Test status
Simulation time 4000484067 ps
CPU time 9.99 seconds
Started Jun 29 06:33:14 PM PDT 24
Finished Jun 29 06:33:25 PM PDT 24
Peak memory 201412 kb
Host smart-5ba81ab8-4245-46a7-a401-2e05b4ab0344
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737976362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_ec_pwr_on_rst.737976362
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.3519289636
Short name T179
Test name
Test status
Simulation time 3106274240 ps
CPU time 1.57 seconds
Started Jun 29 06:33:12 PM PDT 24
Finished Jun 29 06:33:15 PM PDT 24
Peak memory 201428 kb
Host smart-26a555ea-04c3-40ac-a5c1-9d3730d4daf0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519289636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ct
rl_edge_detect.3519289636
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1965462382
Short name T611
Test name
Test status
Simulation time 2624936742 ps
CPU time 2.47 seconds
Started Jun 29 06:33:10 PM PDT 24
Finished Jun 29 06:33:13 PM PDT 24
Peak memory 201520 kb
Host smart-f35d827a-fbf0-4009-bb08-35a2b06586c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965462382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.1965462382
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.1842340686
Short name T64
Test name
Test status
Simulation time 2463066713 ps
CPU time 7.46 seconds
Started Jun 29 06:33:09 PM PDT 24
Finished Jun 29 06:33:17 PM PDT 24
Peak memory 201520 kb
Host smart-f6052416-b5e7-4ceb-96cc-69fcbbb1347b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842340686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.1842340686
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.738817922
Short name T514
Test name
Test status
Simulation time 2237668790 ps
CPU time 3.42 seconds
Started Jun 29 06:33:16 PM PDT 24
Finished Jun 29 06:33:20 PM PDT 24
Peak memory 201532 kb
Host smart-a94b8cc5-fc54-412d-8e8c-3aa6c5526490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738817922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.738817922
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.3431212212
Short name T110
Test name
Test status
Simulation time 2523752212 ps
CPU time 2.31 seconds
Started Jun 29 06:33:11 PM PDT 24
Finished Jun 29 06:33:14 PM PDT 24
Peak memory 201456 kb
Host smart-c3db5f91-023b-44f2-b0a3-0619363ea0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431212212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.3431212212
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.1522855331
Short name T728
Test name
Test status
Simulation time 2110494559 ps
CPU time 6.04 seconds
Started Jun 29 06:33:16 PM PDT 24
Finished Jun 29 06:33:23 PM PDT 24
Peak memory 201452 kb
Host smart-a9ac40e8-1a66-4345-9212-f3beb7f87063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522855331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.1522855331
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.2855576457
Short name T682
Test name
Test status
Simulation time 360794893030 ps
CPU time 119.45 seconds
Started Jun 29 06:33:11 PM PDT 24
Finished Jun 29 06:35:11 PM PDT 24
Peak memory 201836 kb
Host smart-d33b7f78-978a-4328-b20a-9ce673e458db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855576457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_s
tress_all.2855576457
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1801331682
Short name T374
Test name
Test status
Simulation time 151045844635 ps
CPU time 60.68 seconds
Started Jun 29 06:33:16 PM PDT 24
Finished Jun 29 06:34:17 PM PDT 24
Peak memory 211520 kb
Host smart-1f1daac6-43de-47c9-8a87-2cdb9ac3f34a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801331682 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.1801331682
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3446472643
Short name T722
Test name
Test status
Simulation time 2471682648 ps
CPU time 1.97 seconds
Started Jun 29 06:33:09 PM PDT 24
Finished Jun 29 06:33:11 PM PDT 24
Peak memory 201532 kb
Host smart-c6874650-8672-4821-ad8f-194cbca32ec2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446472643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.3446472643
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.4123214464
Short name T72
Test name
Test status
Simulation time 2021943809 ps
CPU time 3.04 seconds
Started Jun 29 06:33:13 PM PDT 24
Finished Jun 29 06:33:17 PM PDT 24
Peak memory 201528 kb
Host smart-84a2a5e9-4f82-48b1-b2ce-9094e3113180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123214464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.4123214464
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2446870938
Short name T177
Test name
Test status
Simulation time 292406568982 ps
CPU time 375.73 seconds
Started Jun 29 06:33:11 PM PDT 24
Finished Jun 29 06:39:27 PM PDT 24
Peak memory 201628 kb
Host smart-85aace2a-e408-4861-a0b6-b7e1382368f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446870938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.2
446870938
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.1724969274
Short name T376
Test name
Test status
Simulation time 166945477898 ps
CPU time 64.51 seconds
Started Jun 29 06:33:15 PM PDT 24
Finished Jun 29 06:34:20 PM PDT 24
Peak memory 201836 kb
Host smart-3e2210d8-e3d1-461c-83cc-55ea62e12e47
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724969274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_combo_detect.1724969274
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3718905658
Short name T517
Test name
Test status
Simulation time 39041954342 ps
CPU time 8.13 seconds
Started Jun 29 06:33:09 PM PDT 24
Finished Jun 29 06:33:18 PM PDT 24
Peak memory 201820 kb
Host smart-78b25b2a-7465-4ac4-8968-73e4ad34a910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718905658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w
ith_pre_cond.3718905658
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2125875329
Short name T607
Test name
Test status
Simulation time 4490002591 ps
CPU time 2.39 seconds
Started Jun 29 06:33:11 PM PDT 24
Finished Jun 29 06:33:14 PM PDT 24
Peak memory 201564 kb
Host smart-e055e50a-7d0e-43eb-96ce-558725ee026a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125875329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ec_pwr_on_rst.2125875329
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1679944206
Short name T683
Test name
Test status
Simulation time 2613135648 ps
CPU time 7.27 seconds
Started Jun 29 06:33:12 PM PDT 24
Finished Jun 29 06:33:20 PM PDT 24
Peak memory 201520 kb
Host smart-d1fabe64-b521-49d3-9b65-9da155818135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679944206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.1679944206
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2983882717
Short name T143
Test name
Test status
Simulation time 2473852899 ps
CPU time 2.16 seconds
Started Jun 29 06:33:15 PM PDT 24
Finished Jun 29 06:33:18 PM PDT 24
Peak memory 201440 kb
Host smart-f1fe4f33-4e7d-4eb4-b5d6-b864c2063eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983882717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.2983882717
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.935340006
Short name T688
Test name
Test status
Simulation time 2191495980 ps
CPU time 5.96 seconds
Started Jun 29 06:33:15 PM PDT 24
Finished Jun 29 06:33:21 PM PDT 24
Peak memory 201444 kb
Host smart-3f3bdbaa-d814-4413-928c-a2bd3a87fe33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935340006 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.935340006
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.2445607325
Short name T141
Test name
Test status
Simulation time 2510138799 ps
CPU time 7.21 seconds
Started Jun 29 06:33:16 PM PDT 24
Finished Jun 29 06:33:24 PM PDT 24
Peak memory 201520 kb
Host smart-3f6b6431-4417-40a6-843a-f117abb8a6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445607325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.2445607325
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.3999445761
Short name T73
Test name
Test status
Simulation time 2124709566 ps
CPU time 1.69 seconds
Started Jun 29 06:33:13 PM PDT 24
Finished Jun 29 06:33:15 PM PDT 24
Peak memory 201448 kb
Host smart-a3bd76e3-94da-4dd7-992b-9c723a5a325d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999445761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.3999445761
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.1140117851
Short name T243
Test name
Test status
Simulation time 16767018089 ps
CPU time 10.33 seconds
Started Jun 29 06:33:10 PM PDT 24
Finished Jun 29 06:33:21 PM PDT 24
Peak memory 201620 kb
Host smart-e9fb4b13-9303-4c2d-83ed-a9b08050cd82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140117851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_s
tress_all.1140117851
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3256604191
Short name T206
Test name
Test status
Simulation time 49023248350 ps
CPU time 104.74 seconds
Started Jun 29 06:33:10 PM PDT 24
Finished Jun 29 06:34:56 PM PDT 24
Peak memory 210252 kb
Host smart-445c3162-cb85-4d49-9a40-c9583776cf1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256604191 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.3256604191
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2982936341
Short name T504
Test name
Test status
Simulation time 7615873396 ps
CPU time 4.13 seconds
Started Jun 29 06:33:16 PM PDT 24
Finished Jun 29 06:33:21 PM PDT 24
Peak memory 201564 kb
Host smart-5b939673-98d9-4874-b8ae-ae44b56738a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982936341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.2982936341
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.3277776794
Short name T762
Test name
Test status
Simulation time 2010922365 ps
CPU time 5.86 seconds
Started Jun 29 06:33:20 PM PDT 24
Finished Jun 29 06:33:26 PM PDT 24
Peak memory 201512 kb
Host smart-679417e6-393b-4c8f-99a9-a261155ab492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277776794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.3277776794
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.3685713556
Short name T673
Test name
Test status
Simulation time 3792209526 ps
CPU time 3.11 seconds
Started Jun 29 06:33:16 PM PDT 24
Finished Jun 29 06:33:20 PM PDT 24
Peak memory 201500 kb
Host smart-53cf9c2f-fda2-453c-bf3d-7529e99f035c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685713556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.3
685713556
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.3662029777
Short name T721
Test name
Test status
Simulation time 132922077951 ps
CPU time 336.86 seconds
Started Jun 29 06:33:18 PM PDT 24
Finished Jun 29 06:38:56 PM PDT 24
Peak memory 201764 kb
Host smart-b3365e3a-9112-4be5-9485-37526107fde1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662029777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_combo_detect.3662029777
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.2588071186
Short name T399
Test name
Test status
Simulation time 73331277827 ps
CPU time 176.37 seconds
Started Jun 29 06:33:17 PM PDT 24
Finished Jun 29 06:36:15 PM PDT 24
Peak memory 201788 kb
Host smart-8b9fc215-8721-4b43-b2c4-6b5cd0bbb7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588071186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_w
ith_pre_cond.2588071186
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.816186953
Short name T692
Test name
Test status
Simulation time 2668859896 ps
CPU time 2.15 seconds
Started Jun 29 06:33:18 PM PDT 24
Finished Jun 29 06:33:21 PM PDT 24
Peak memory 201428 kb
Host smart-c63c918c-6eef-431e-a43e-e060895f052b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816186953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_ec_pwr_on_rst.816186953
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.652239443
Short name T274
Test name
Test status
Simulation time 5982498350 ps
CPU time 15.11 seconds
Started Jun 29 06:33:21 PM PDT 24
Finished Jun 29 06:33:37 PM PDT 24
Peak memory 201552 kb
Host smart-7414f0c9-19d8-443c-871f-e9b96008c4d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652239443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctr
l_edge_detect.652239443
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1841557799
Short name T612
Test name
Test status
Simulation time 2627276498 ps
CPU time 2.25 seconds
Started Jun 29 06:33:18 PM PDT 24
Finished Jun 29 06:33:21 PM PDT 24
Peak memory 201512 kb
Host smart-c05aed9b-81c8-4c08-8d9c-b01afb1c65e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841557799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.1841557799
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.801686134
Short name T161
Test name
Test status
Simulation time 2475186045 ps
CPU time 3.71 seconds
Started Jun 29 06:33:12 PM PDT 24
Finished Jun 29 06:33:16 PM PDT 24
Peak memory 201500 kb
Host smart-1756b481-b1a2-4bf3-b902-6c0c19c6d017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801686134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.801686134
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3959180067
Short name T58
Test name
Test status
Simulation time 2105547376 ps
CPU time 4.52 seconds
Started Jun 29 06:33:17 PM PDT 24
Finished Jun 29 06:33:23 PM PDT 24
Peak memory 201448 kb
Host smart-52f75779-814c-4ef0-9753-a2b7311f0e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959180067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.3959180067
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.3291932556
Short name T510
Test name
Test status
Simulation time 2518021197 ps
CPU time 4 seconds
Started Jun 29 06:33:18 PM PDT 24
Finished Jun 29 06:33:23 PM PDT 24
Peak memory 201468 kb
Host smart-44eddc4f-bc1c-4948-a26b-8602a69327ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291932556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.3291932556
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.3979737275
Short name T221
Test name
Test status
Simulation time 2143294421 ps
CPU time 1.62 seconds
Started Jun 29 06:33:10 PM PDT 24
Finished Jun 29 06:33:12 PM PDT 24
Peak memory 201452 kb
Host smart-84c42c7a-a3f9-4dc1-8dca-4858e7d2010b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979737275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.3979737275
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.2553331492
Short name T344
Test name
Test status
Simulation time 158517187156 ps
CPU time 100.33 seconds
Started Jun 29 06:33:19 PM PDT 24
Finished Jun 29 06:35:00 PM PDT 24
Peak memory 201652 kb
Host smart-b6394d62-2aa6-45b6-b9ef-e5984f601ca7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553331492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_s
tress_all.2553331492
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3758725948
Short name T202
Test name
Test status
Simulation time 45943918542 ps
CPU time 32.19 seconds
Started Jun 29 06:33:19 PM PDT 24
Finished Jun 29 06:33:52 PM PDT 24
Peak memory 210196 kb
Host smart-c09eb479-0a8e-494f-aaef-7a57acb02050
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758725948 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.3758725948
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.4148223791
Short name T469
Test name
Test status
Simulation time 6864189674 ps
CPU time 5.64 seconds
Started Jun 29 06:33:17 PM PDT 24
Finished Jun 29 06:33:24 PM PDT 24
Peak memory 201564 kb
Host smart-0a55a089-879d-4b9a-9d98-61e997fc9c18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148223791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.4148223791
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.4162686765
Short name T503
Test name
Test status
Simulation time 2024296092 ps
CPU time 1.85 seconds
Started Jun 29 06:31:38 PM PDT 24
Finished Jun 29 06:31:40 PM PDT 24
Peak memory 201516 kb
Host smart-73916814-e32d-4896-a07f-8f20263e9162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162686765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.4162686765
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3475359569
Short name T56
Test name
Test status
Simulation time 3216045042 ps
CPU time 2.53 seconds
Started Jun 29 06:31:47 PM PDT 24
Finished Jun 29 06:31:50 PM PDT 24
Peak memory 201580 kb
Host smart-25998fd7-4f6a-4320-a517-28d6da7459ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475359569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.3475359569
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.3114207455
Short name T99
Test name
Test status
Simulation time 101521379196 ps
CPU time 82.85 seconds
Started Jun 29 06:31:40 PM PDT 24
Finished Jun 29 06:33:03 PM PDT 24
Peak memory 201752 kb
Host smart-802560f8-11a7-4c08-9cf6-5e6445be2089
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114207455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_combo_detect.3114207455
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.283377977
Short name T758
Test name
Test status
Simulation time 4093767759 ps
CPU time 6.05 seconds
Started Jun 29 06:31:38 PM PDT 24
Finished Jun 29 06:31:45 PM PDT 24
Peak memory 201444 kb
Host smart-53bd1d61-48e1-4470-aa5f-29f81861d5de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283377977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_ec_pwr_on_rst.283377977
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.3136953171
Short name T282
Test name
Test status
Simulation time 2651690952 ps
CPU time 7.6 seconds
Started Jun 29 06:31:38 PM PDT 24
Finished Jun 29 06:31:47 PM PDT 24
Peak memory 201496 kb
Host smart-1971fff4-df6d-4596-8e2c-a508e62bc7a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136953171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_edge_detect.3136953171
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1848300741
Short name T439
Test name
Test status
Simulation time 2615429314 ps
CPU time 3.95 seconds
Started Jun 29 06:31:38 PM PDT 24
Finished Jun 29 06:31:42 PM PDT 24
Peak memory 201508 kb
Host smart-3ca8acc6-95a0-4f29-ad35-c405ae35f057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848300741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.1848300741
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.3603757824
Short name T483
Test name
Test status
Simulation time 2463983624 ps
CPU time 7.19 seconds
Started Jun 29 06:31:36 PM PDT 24
Finished Jun 29 06:31:43 PM PDT 24
Peak memory 201528 kb
Host smart-44cd9996-1dff-432b-9ef8-6411fcacef36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603757824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.3603757824
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.1230488767
Short name T475
Test name
Test status
Simulation time 2187067518 ps
CPU time 1.33 seconds
Started Jun 29 06:31:30 PM PDT 24
Finished Jun 29 06:31:32 PM PDT 24
Peak memory 201452 kb
Host smart-1dd0779c-5e71-4efd-af92-6e2326de1a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230488767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.1230488767
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.2270565990
Short name T492
Test name
Test status
Simulation time 2123172786 ps
CPU time 2.05 seconds
Started Jun 29 06:31:38 PM PDT 24
Finished Jun 29 06:31:40 PM PDT 24
Peak memory 201448 kb
Host smart-b168480a-56c5-477c-9cb7-ae88cf71971c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270565990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.2270565990
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.1824097224
Short name T123
Test name
Test status
Simulation time 298988556666 ps
CPU time 370.58 seconds
Started Jun 29 06:31:41 PM PDT 24
Finished Jun 29 06:37:52 PM PDT 24
Peak memory 201612 kb
Host smart-69f2bfa3-c146-4bc1-8b6d-6d6fdee18d7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824097224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st
ress_all.1824097224
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1234900033
Short name T216
Test name
Test status
Simulation time 35677734002 ps
CPU time 67.84 seconds
Started Jun 29 06:31:40 PM PDT 24
Finished Jun 29 06:32:48 PM PDT 24
Peak memory 210216 kb
Host smart-8900a5af-004b-4bb0-9f1e-38c7150790bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234900033 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.1234900033
Directory /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3815980530
Short name T415
Test name
Test status
Simulation time 1054625018736 ps
CPU time 122.36 seconds
Started Jun 29 06:31:42 PM PDT 24
Finished Jun 29 06:33:45 PM PDT 24
Peak memory 201560 kb
Host smart-0eb666e9-c46c-4a43-9006-aa415a2106f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815980530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.3815980530
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1338322076
Short name T286
Test name
Test status
Simulation time 144883468961 ps
CPU time 25.7 seconds
Started Jun 29 06:33:24 PM PDT 24
Finished Jun 29 06:33:50 PM PDT 24
Peak memory 202052 kb
Host smart-2fddc25a-fae6-47a6-bd30-cfb0dfcfe16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338322076 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_w
ith_pre_cond.1338322076
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.485081167
Short name T173
Test name
Test status
Simulation time 95067215306 ps
CPU time 129.63 seconds
Started Jun 29 06:33:18 PM PDT 24
Finished Jun 29 06:35:28 PM PDT 24
Peak memory 201800 kb
Host smart-a48ecd6c-aa08-4faf-b073-1d6a0d601bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485081167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_wi
th_pre_cond.485081167
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2038467008
Short name T769
Test name
Test status
Simulation time 53572539357 ps
CPU time 35.93 seconds
Started Jun 29 06:33:20 PM PDT 24
Finished Jun 29 06:33:57 PM PDT 24
Peak memory 201812 kb
Host smart-8a8f59ad-46da-4261-9864-ee7c85f2410e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038467008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_w
ith_pre_cond.2038467008
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.4085722787
Short name T204
Test name
Test status
Simulation time 24840686396 ps
CPU time 30.92 seconds
Started Jun 29 06:33:18 PM PDT 24
Finished Jun 29 06:33:51 PM PDT 24
Peak memory 201844 kb
Host smart-fd13010b-9255-4762-98c0-a8a7cfb72cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085722787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_w
ith_pre_cond.4085722787
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1824499780
Short name T397
Test name
Test status
Simulation time 145636636328 ps
CPU time 345.53 seconds
Started Jun 29 06:33:20 PM PDT 24
Finished Jun 29 06:39:06 PM PDT 24
Peak memory 201720 kb
Host smart-0b8ac908-9a23-456e-a891-40ec0f3b14d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824499780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_w
ith_pre_cond.1824499780
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3863913667
Short name T53
Test name
Test status
Simulation time 24329345486 ps
CPU time 54.35 seconds
Started Jun 29 06:33:20 PM PDT 24
Finished Jun 29 06:34:15 PM PDT 24
Peak memory 201852 kb
Host smart-2826b738-8e20-4939-993e-b9a0d60ce4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863913667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_w
ith_pre_cond.3863913667
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.130385291
Short name T506
Test name
Test status
Simulation time 2014954074 ps
CPU time 5.84 seconds
Started Jun 29 06:31:41 PM PDT 24
Finished Jun 29 06:31:47 PM PDT 24
Peak memory 201524 kb
Host smart-3ea4531e-e3a5-4afc-b639-879867d3596d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130385291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test
.130385291
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1253422966
Short name T657
Test name
Test status
Simulation time 3230395982 ps
CPU time 3.09 seconds
Started Jun 29 06:31:47 PM PDT 24
Finished Jun 29 06:31:51 PM PDT 24
Peak memory 201576 kb
Host smart-4be8976a-dd67-408b-aced-e302968ccd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253422966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.1253422966
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.1738511117
Short name T303
Test name
Test status
Simulation time 168207779650 ps
CPU time 441.07 seconds
Started Jun 29 06:31:47 PM PDT 24
Finished Jun 29 06:39:09 PM PDT 24
Peak memory 201816 kb
Host smart-02efa02e-578f-4bc0-827c-8b928d36ff32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738511117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_combo_detect.1738511117
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3069915366
Short name T379
Test name
Test status
Simulation time 113876510788 ps
CPU time 78.43 seconds
Started Jun 29 06:31:40 PM PDT 24
Finished Jun 29 06:32:59 PM PDT 24
Peak memory 201892 kb
Host smart-55721dd2-4c4b-4915-9d0c-b3645f221fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069915366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_wi
th_pre_cond.3069915366
Directory /workspace/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1051026610
Short name T583
Test name
Test status
Simulation time 3207491477 ps
CPU time 2.65 seconds
Started Jun 29 06:31:45 PM PDT 24
Finished Jun 29 06:31:49 PM PDT 24
Peak memory 201432 kb
Host smart-1b61723e-617d-4bf2-ace2-93f066755b03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051026610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.1051026610
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.3115681038
Short name T230
Test name
Test status
Simulation time 4810302140 ps
CPU time 3.09 seconds
Started Jun 29 06:31:40 PM PDT 24
Finished Jun 29 06:31:44 PM PDT 24
Peak memory 201560 kb
Host smart-d02582f5-88ce-4b0d-9272-051e4feb47df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115681038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_edge_detect.3115681038
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1586670751
Short name T27
Test name
Test status
Simulation time 2621836676 ps
CPU time 3.87 seconds
Started Jun 29 06:31:44 PM PDT 24
Finished Jun 29 06:31:49 PM PDT 24
Peak memory 201452 kb
Host smart-5b4f0989-801f-4e36-826b-f6504fc30db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586670751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.1586670751
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.2318414371
Short name T171
Test name
Test status
Simulation time 2480469105 ps
CPU time 3.47 seconds
Started Jun 29 06:31:47 PM PDT 24
Finished Jun 29 06:31:52 PM PDT 24
Peak memory 201520 kb
Host smart-bea73406-833f-4d19-956b-6a5afceb1767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318414371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.2318414371
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.3398949588
Short name T434
Test name
Test status
Simulation time 2145029983 ps
CPU time 6.38 seconds
Started Jun 29 06:31:39 PM PDT 24
Finished Jun 29 06:31:46 PM PDT 24
Peak memory 201376 kb
Host smart-6469158c-2a25-4386-a6e7-9eeeb1f7c1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398949588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.3398949588
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3636217752
Short name T255
Test name
Test status
Simulation time 2517493131 ps
CPU time 3.93 seconds
Started Jun 29 06:31:41 PM PDT 24
Finished Jun 29 06:31:45 PM PDT 24
Peak memory 201536 kb
Host smart-35f0f2bb-935c-4e68-b258-dbaf9bb8d38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636217752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.3636217752
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.3002590097
Short name T502
Test name
Test status
Simulation time 2118893548 ps
CPU time 3.17 seconds
Started Jun 29 06:31:45 PM PDT 24
Finished Jun 29 06:31:49 PM PDT 24
Peak memory 201388 kb
Host smart-a05108e9-0ce6-4a41-a78b-aa13f385a1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002590097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.3002590097
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.4164528775
Short name T443
Test name
Test status
Simulation time 8276328112 ps
CPU time 21.97 seconds
Started Jun 29 06:31:42 PM PDT 24
Finished Jun 29 06:32:04 PM PDT 24
Peak memory 201608 kb
Host smart-fca09ebd-7a27-4012-bb02-655096bafdc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164528775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st
ress_all.4164528775
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1469993752
Short name T254
Test name
Test status
Simulation time 42384228510 ps
CPU time 57.3 seconds
Started Jun 29 06:31:45 PM PDT 24
Finished Jun 29 06:32:43 PM PDT 24
Peak memory 210188 kb
Host smart-1df2fc10-3106-4283-ab97-cb4a375fb8c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469993752 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.1469993752
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1682029828
Short name T120
Test name
Test status
Simulation time 4104314993 ps
CPU time 2.3 seconds
Started Jun 29 06:31:38 PM PDT 24
Finished Jun 29 06:31:41 PM PDT 24
Peak memory 201532 kb
Host smart-bc5a228b-0257-40e8-874b-5a1a6caaa3f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682029828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ultra_low_pwr.1682029828
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.4054228764
Short name T536
Test name
Test status
Simulation time 25581409888 ps
CPU time 37 seconds
Started Jun 29 06:33:18 PM PDT 24
Finished Jun 29 06:33:56 PM PDT 24
Peak memory 201852 kb
Host smart-3d702b47-2754-49dc-b29d-fd6804dd1413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054228764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_w
ith_pre_cond.4054228764
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2414840661
Short name T375
Test name
Test status
Simulation time 82405546653 ps
CPU time 55.68 seconds
Started Jun 29 06:33:18 PM PDT 24
Finished Jun 29 06:34:14 PM PDT 24
Peak memory 201804 kb
Host smart-d4473068-9712-4b8e-b336-5ad2ae4248c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414840661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.2414840661
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.2148834708
Short name T159
Test name
Test status
Simulation time 63916502875 ps
CPU time 168.79 seconds
Started Jun 29 06:33:19 PM PDT 24
Finished Jun 29 06:36:09 PM PDT 24
Peak memory 201904 kb
Host smart-9be1d986-0033-4233-8f62-7da2de6a3c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148834708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_w
ith_pre_cond.2148834708
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.852437558
Short name T402
Test name
Test status
Simulation time 71583774212 ps
CPU time 198.16 seconds
Started Jun 29 06:33:21 PM PDT 24
Finished Jun 29 06:36:40 PM PDT 24
Peak memory 201852 kb
Host smart-50043b51-d3c1-4b2d-bde9-6c74fb6349e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852437558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_wi
th_pre_cond.852437558
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.17542589
Short name T644
Test name
Test status
Simulation time 67088997367 ps
CPU time 177.43 seconds
Started Jun 29 06:33:22 PM PDT 24
Finished Jun 29 06:36:20 PM PDT 24
Peak memory 201860 kb
Host smart-003050d8-9a9e-48c2-ae60-eb0a6c20d01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17542589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_wit
h_pre_cond.17542589
Directory /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3952597948
Short name T47
Test name
Test status
Simulation time 101932186424 ps
CPU time 244.21 seconds
Started Jun 29 06:33:21 PM PDT 24
Finished Jun 29 06:37:25 PM PDT 24
Peak memory 201796 kb
Host smart-582810f5-6280-4061-aaf6-2d9b87ecdd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952597948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.3952597948
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.1548302450
Short name T778
Test name
Test status
Simulation time 45249674247 ps
CPU time 27.9 seconds
Started Jun 29 06:33:18 PM PDT 24
Finished Jun 29 06:33:46 PM PDT 24
Peak memory 201824 kb
Host smart-acbdd890-6d87-4692-8ba3-479f02f3f410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548302450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_w
ith_pre_cond.1548302450
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.4142388348
Short name T505
Test name
Test status
Simulation time 2010217029 ps
CPU time 6.07 seconds
Started Jun 29 06:31:45 PM PDT 24
Finished Jun 29 06:31:52 PM PDT 24
Peak memory 201732 kb
Host smart-14f85b86-f195-4db0-8990-533731f1a685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142388348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_tes
t.4142388348
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1038404872
Short name T569
Test name
Test status
Simulation time 3421772796 ps
CPU time 9.74 seconds
Started Jun 29 06:31:42 PM PDT 24
Finished Jun 29 06:31:52 PM PDT 24
Peak memory 201580 kb
Host smart-4c576993-c5a8-48e0-9d73-ae27ee9fc96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038404872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.1038404872
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.223879453
Short name T409
Test name
Test status
Simulation time 93188322245 ps
CPU time 63.15 seconds
Started Jun 29 06:31:41 PM PDT 24
Finished Jun 29 06:32:45 PM PDT 24
Peak memory 201764 kb
Host smart-61ad7d9f-e84f-4da9-8a12-c25186a48b3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223879453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_combo_detect.223879453
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.2976424486
Short name T51
Test name
Test status
Simulation time 29581673267 ps
CPU time 82.15 seconds
Started Jun 29 06:31:46 PM PDT 24
Finished Jun 29 06:33:08 PM PDT 24
Peak memory 201844 kb
Host smart-68b491eb-246d-4298-93fa-444453956623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976424486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wi
th_pre_cond.2976424486
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2236984329
Short name T584
Test name
Test status
Simulation time 3118761030 ps
CPU time 4.5 seconds
Started Jun 29 06:31:42 PM PDT 24
Finished Jun 29 06:31:47 PM PDT 24
Peak memory 201492 kb
Host smart-5bdaeeed-58d7-42f2-8e8a-d4c715c4a65e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236984329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ec_pwr_on_rst.2236984329
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.2474614118
Short name T742
Test name
Test status
Simulation time 254565995905 ps
CPU time 65.37 seconds
Started Jun 29 06:31:49 PM PDT 24
Finished Jun 29 06:32:56 PM PDT 24
Peak memory 201592 kb
Host smart-e0c8a3e8-4d8b-4ad8-8ae5-481307daa032
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474614118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.2474614118
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.2057011890
Short name T174
Test name
Test status
Simulation time 2609332865 ps
CPU time 7.55 seconds
Started Jun 29 06:31:40 PM PDT 24
Finished Jun 29 06:31:48 PM PDT 24
Peak memory 201520 kb
Host smart-bb8f4eb7-2dca-48ae-bce9-e73e227ad9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057011890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.2057011890
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2435178865
Short name T647
Test name
Test status
Simulation time 2426337433 ps
CPU time 7.61 seconds
Started Jun 29 06:31:46 PM PDT 24
Finished Jun 29 06:31:54 PM PDT 24
Peak memory 201512 kb
Host smart-9b2fc882-cd07-4aad-b907-8535f4669186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435178865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.2435178865
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.756303018
Short name T482
Test name
Test status
Simulation time 2200539070 ps
CPU time 2.11 seconds
Started Jun 29 06:31:47 PM PDT 24
Finished Jun 29 06:31:51 PM PDT 24
Peak memory 201508 kb
Host smart-96b2b411-b28e-43cd-be2a-5eddb81c0045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756303018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.756303018
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.2890789950
Short name T538
Test name
Test status
Simulation time 2512886832 ps
CPU time 7.18 seconds
Started Jun 29 06:31:38 PM PDT 24
Finished Jun 29 06:31:46 PM PDT 24
Peak memory 201508 kb
Host smart-978aec5b-8ac8-44d1-a492-168f492229b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890789950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.2890789950
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.3141770142
Short name T164
Test name
Test status
Simulation time 2128958149 ps
CPU time 1.99 seconds
Started Jun 29 06:31:42 PM PDT 24
Finished Jun 29 06:31:45 PM PDT 24
Peak memory 201452 kb
Host smart-1ce75591-28ef-4f66-a0c9-66f502e2f76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141770142 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.3141770142
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.3217324917
Short name T3
Test name
Test status
Simulation time 164589659614 ps
CPU time 211.04 seconds
Started Jun 29 06:31:41 PM PDT 24
Finished Jun 29 06:35:13 PM PDT 24
Peak memory 201752 kb
Host smart-96ed11cd-54b0-4df5-a37e-7507f4c8e2eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217324917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.3217324917
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.4151283611
Short name T111
Test name
Test status
Simulation time 36500982984 ps
CPU time 41.92 seconds
Started Jun 29 06:31:42 PM PDT 24
Finished Jun 29 06:32:24 PM PDT 24
Peak memory 210224 kb
Host smart-3829eba2-7692-41f7-a7e3-360fd61d25a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151283611 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.4151283611
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1692163817
Short name T572
Test name
Test status
Simulation time 3801914464 ps
CPU time 1.24 seconds
Started Jun 29 06:31:51 PM PDT 24
Finished Jun 29 06:31:52 PM PDT 24
Peak memory 201460 kb
Host smart-69c4153d-e334-48eb-b36e-6fa007bd90b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692163817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ultra_low_pwr.1692163817
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.892608703
Short name T761
Test name
Test status
Simulation time 69941934198 ps
CPU time 46.16 seconds
Started Jun 29 06:33:19 PM PDT 24
Finished Jun 29 06:34:07 PM PDT 24
Peak memory 201836 kb
Host smart-1295b8c0-dc6f-4e65-b564-522ba9e09c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892608703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_wi
th_pre_cond.892608703
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2180253590
Short name T290
Test name
Test status
Simulation time 25862308611 ps
CPU time 16.54 seconds
Started Jun 29 06:33:18 PM PDT 24
Finished Jun 29 06:33:35 PM PDT 24
Peak memory 201880 kb
Host smart-9f559ec0-5f68-48bb-999e-c2d7b3febad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180253590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_w
ith_pre_cond.2180253590
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1968311788
Short name T713
Test name
Test status
Simulation time 27081225224 ps
CPU time 75.18 seconds
Started Jun 29 06:33:25 PM PDT 24
Finished Jun 29 06:34:41 PM PDT 24
Peak memory 201848 kb
Host smart-f4ef0361-6007-4e03-b39a-28a4414c0a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968311788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_w
ith_pre_cond.1968311788
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1097071096
Short name T218
Test name
Test status
Simulation time 25580088479 ps
CPU time 44.86 seconds
Started Jun 29 06:33:25 PM PDT 24
Finished Jun 29 06:34:11 PM PDT 24
Peak memory 201864 kb
Host smart-088f954d-ba96-44ba-8cb3-9b76d1a7e96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097071096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_w
ith_pre_cond.1097071096
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3276014960
Short name T90
Test name
Test status
Simulation time 77904327961 ps
CPU time 56.98 seconds
Started Jun 29 06:33:24 PM PDT 24
Finished Jun 29 06:34:21 PM PDT 24
Peak memory 201784 kb
Host smart-e47167ab-4e80-48f3-bc33-65925b0fe09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276014960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_w
ith_pre_cond.3276014960
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.276877321
Short name T605
Test name
Test status
Simulation time 124524952273 ps
CPU time 77.84 seconds
Started Jun 29 06:33:26 PM PDT 24
Finished Jun 29 06:34:45 PM PDT 24
Peak memory 201856 kb
Host smart-c642e00b-6b24-474d-8377-c96ad0fde319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276877321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_wi
th_pre_cond.276877321
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1128044519
Short name T29
Test name
Test status
Simulation time 25850585187 ps
CPU time 17.89 seconds
Started Jun 29 06:33:27 PM PDT 24
Finished Jun 29 06:33:47 PM PDT 24
Peak memory 201812 kb
Host smart-dee0e1e9-f4dd-4c7a-9ecf-085f70195a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128044519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.1128044519
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.495428352
Short name T112
Test name
Test status
Simulation time 126848275514 ps
CPU time 330.02 seconds
Started Jun 29 06:33:26 PM PDT 24
Finished Jun 29 06:38:57 PM PDT 24
Peak memory 201752 kb
Host smart-7ed02491-e84c-42bc-b3d6-90d2c79a1248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495428352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_wi
th_pre_cond.495428352
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.1039724467
Short name T554
Test name
Test status
Simulation time 2032075814 ps
CPU time 1.9 seconds
Started Jun 29 06:31:39 PM PDT 24
Finished Jun 29 06:31:41 PM PDT 24
Peak memory 201516 kb
Host smart-42cba527-c50d-403f-9cac-0a787a6e239f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039724467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.1039724467
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1354305533
Short name T55
Test name
Test status
Simulation time 3201998239 ps
CPU time 8.76 seconds
Started Jun 29 06:31:43 PM PDT 24
Finished Jun 29 06:31:52 PM PDT 24
Peak memory 201532 kb
Host smart-5f9167ec-7ad8-4a83-98dc-6e54b43f0158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354305533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.1354305533
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1009772465
Short name T589
Test name
Test status
Simulation time 3073072872 ps
CPU time 3.28 seconds
Started Jun 29 06:31:41 PM PDT 24
Finished Jun 29 06:31:45 PM PDT 24
Peak memory 201488 kb
Host smart-e1f9effd-6a49-4437-997b-531429e7cbc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009772465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ec_pwr_on_rst.1009772465
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.799973108
Short name T192
Test name
Test status
Simulation time 2720193088 ps
CPU time 4.42 seconds
Started Jun 29 06:31:47 PM PDT 24
Finished Jun 29 06:31:53 PM PDT 24
Peak memory 201496 kb
Host smart-f280bfe2-6a03-4c81-b026-a6dc055f79ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799973108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl
_edge_detect.799973108
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3146628651
Short name T422
Test name
Test status
Simulation time 2636585161 ps
CPU time 2.22 seconds
Started Jun 29 06:31:47 PM PDT 24
Finished Jun 29 06:31:50 PM PDT 24
Peak memory 201516 kb
Host smart-cc5fb46d-e77d-48df-9085-b34f69294eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146628651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.3146628651
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.3714352451
Short name T687
Test name
Test status
Simulation time 2479222165 ps
CPU time 8.16 seconds
Started Jun 29 06:31:40 PM PDT 24
Finished Jun 29 06:31:48 PM PDT 24
Peak memory 201536 kb
Host smart-2d30def7-f177-4f27-b6cd-f25f86f7135a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714352451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.3714352451
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.2111927894
Short name T129
Test name
Test status
Simulation time 2254115754 ps
CPU time 6.39 seconds
Started Jun 29 06:31:39 PM PDT 24
Finished Jun 29 06:31:46 PM PDT 24
Peak memory 201452 kb
Host smart-0e1812f2-ded7-4e04-a702-e97d7a25ff03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111927894 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.2111927894
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2655925438
Short name T779
Test name
Test status
Simulation time 2510749726 ps
CPU time 7.64 seconds
Started Jun 29 06:31:47 PM PDT 24
Finished Jun 29 06:31:56 PM PDT 24
Peak memory 201528 kb
Host smart-22204798-6a02-4bc8-979c-ebd0d52f2b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655925438 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.2655925438
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.1162072230
Short name T574
Test name
Test status
Simulation time 2119119826 ps
CPU time 3.21 seconds
Started Jun 29 06:31:41 PM PDT 24
Finished Jun 29 06:31:44 PM PDT 24
Peak memory 201440 kb
Host smart-6e89b741-85d3-411e-a434-06f8ed6028ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162072230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.1162072230
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.3200657916
Short name T214
Test name
Test status
Simulation time 9898739949 ps
CPU time 2.62 seconds
Started Jun 29 06:31:43 PM PDT 24
Finished Jun 29 06:31:46 PM PDT 24
Peak memory 201552 kb
Host smart-e8e9124a-8996-4efb-8512-416f73d266f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200657916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_st
ress_all.3200657916
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.2351173489
Short name T220
Test name
Test status
Simulation time 11306840275 ps
CPU time 28.96 seconds
Started Jun 29 06:31:47 PM PDT 24
Finished Jun 29 06:32:17 PM PDT 24
Peak memory 201700 kb
Host smart-641ba726-ec84-42d5-920a-7df09557c7fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351173489 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.2351173489
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1835598032
Short name T734
Test name
Test status
Simulation time 11900495239 ps
CPU time 2.46 seconds
Started Jun 29 06:31:40 PM PDT 24
Finished Jun 29 06:31:43 PM PDT 24
Peak memory 201508 kb
Host smart-21ae9784-23f8-4e08-a181-829943f513f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835598032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ultra_low_pwr.1835598032
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.932735110
Short name T75
Test name
Test status
Simulation time 54217558337 ps
CPU time 139.32 seconds
Started Jun 29 06:33:26 PM PDT 24
Finished Jun 29 06:35:46 PM PDT 24
Peak memory 201800 kb
Host smart-040ae903-fdec-494c-bbff-d395da13362a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932735110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_wi
th_pre_cond.932735110
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1536332750
Short name T665
Test name
Test status
Simulation time 34324883781 ps
CPU time 28.76 seconds
Started Jun 29 06:33:31 PM PDT 24
Finished Jun 29 06:34:00 PM PDT 24
Peak memory 201892 kb
Host smart-43cd1d6d-191d-4d91-ab73-87abc22a6e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536332750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_w
ith_pre_cond.1536332750
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.329180778
Short name T81
Test name
Test status
Simulation time 88033599207 ps
CPU time 58 seconds
Started Jun 29 06:33:24 PM PDT 24
Finished Jun 29 06:34:23 PM PDT 24
Peak memory 201836 kb
Host smart-6713ddb0-aca7-43d8-856c-1560eaeaa5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329180778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_wi
th_pre_cond.329180778
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2123114942
Short name T263
Test name
Test status
Simulation time 26607410931 ps
CPU time 16.77 seconds
Started Jun 29 06:33:25 PM PDT 24
Finished Jun 29 06:33:43 PM PDT 24
Peak memory 201884 kb
Host smart-02e054da-0b85-479f-8788-036b10238eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123114942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_w
ith_pre_cond.2123114942
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.37882177
Short name T709
Test name
Test status
Simulation time 29595909992 ps
CPU time 18.9 seconds
Started Jun 29 06:33:24 PM PDT 24
Finished Jun 29 06:33:44 PM PDT 24
Peak memory 201824 kb
Host smart-cbeea44b-2836-4bc3-bd9c-f78e082410a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37882177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_wit
h_pre_cond.37882177
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.3901354541
Short name T170
Test name
Test status
Simulation time 44947406166 ps
CPU time 17.16 seconds
Started Jun 29 06:33:25 PM PDT 24
Finished Jun 29 06:33:43 PM PDT 24
Peak memory 201864 kb
Host smart-b847dd16-208d-4505-9067-e5fb4f09bbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901354541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_w
ith_pre_cond.3901354541
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2735099108
Short name T212
Test name
Test status
Simulation time 86701788420 ps
CPU time 55.86 seconds
Started Jun 29 06:33:25 PM PDT 24
Finished Jun 29 06:34:21 PM PDT 24
Peak memory 201840 kb
Host smart-f9b8535e-5bfb-4e9e-9a0e-2ca9989dd217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735099108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_w
ith_pre_cond.2735099108
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.4213870444
Short name T621
Test name
Test status
Simulation time 23830671792 ps
CPU time 61.67 seconds
Started Jun 29 06:33:25 PM PDT 24
Finished Jun 29 06:34:27 PM PDT 24
Peak memory 201852 kb
Host smart-f8c47372-9787-4ab3-8fe3-623d1041184c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213870444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_w
ith_pre_cond.4213870444
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2667634488
Short name T655
Test name
Test status
Simulation time 24839090229 ps
CPU time 31.79 seconds
Started Jun 29 06:33:28 PM PDT 24
Finished Jun 29 06:34:01 PM PDT 24
Peak memory 201840 kb
Host smart-3c026cd6-3e0d-4be2-897f-87fb7ec313eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667634488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_w
ith_pre_cond.2667634488
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.26682893
Short name T532
Test name
Test status
Simulation time 27629796406 ps
CPU time 11.44 seconds
Started Jun 29 06:33:25 PM PDT 24
Finished Jun 29 06:33:36 PM PDT 24
Peak memory 201848 kb
Host smart-5405ff08-f634-4e2f-8696-d9e3921863a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26682893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_wit
h_pre_cond.26682893
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.1283212650
Short name T211
Test name
Test status
Simulation time 2052304530 ps
CPU time 1.75 seconds
Started Jun 29 06:31:53 PM PDT 24
Finished Jun 29 06:31:56 PM PDT 24
Peak memory 201520 kb
Host smart-b0b65048-858a-4671-bad8-707077075b0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283212650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_tes
t.1283212650
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2859131943
Short name T278
Test name
Test status
Simulation time 3500923406 ps
CPU time 9.15 seconds
Started Jun 29 06:31:44 PM PDT 24
Finished Jun 29 06:31:53 PM PDT 24
Peak memory 201572 kb
Host smart-b8ebb270-bcf8-4ff9-a161-cab05c930b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859131943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.2859131943
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.1008712563
Short name T651
Test name
Test status
Simulation time 129794892905 ps
CPU time 44.92 seconds
Started Jun 29 06:31:44 PM PDT 24
Finished Jun 29 06:32:29 PM PDT 24
Peak memory 201768 kb
Host smart-8c9fa28c-dd67-4e49-80e2-d282e9d3ed32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008712563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.1008712563
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1272314990
Short name T675
Test name
Test status
Simulation time 5312758591 ps
CPU time 11.65 seconds
Started Jun 29 06:31:39 PM PDT 24
Finished Jun 29 06:31:51 PM PDT 24
Peak memory 201556 kb
Host smart-5a4f6143-6d75-4abe-89dc-1c887957313a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272314990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ec_pwr_on_rst.1272314990
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.3949193228
Short name T252
Test name
Test status
Simulation time 5254533742 ps
CPU time 2.58 seconds
Started Jun 29 06:31:44 PM PDT 24
Finished Jun 29 06:31:47 PM PDT 24
Peak memory 201596 kb
Host smart-9552dc5d-4a2a-49d0-bf9e-5f4f9e9d12dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949193228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.3949193228
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.714827089
Short name T258
Test name
Test status
Simulation time 2619537132 ps
CPU time 2.42 seconds
Started Jun 29 06:31:47 PM PDT 24
Finished Jun 29 06:31:51 PM PDT 24
Peak memory 201512 kb
Host smart-37c1a5da-7ff9-4c6a-86ca-413edb0ba67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714827089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.714827089
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.2778873513
Short name T567
Test name
Test status
Simulation time 2483119985 ps
CPU time 2.12 seconds
Started Jun 29 06:31:44 PM PDT 24
Finished Jun 29 06:31:47 PM PDT 24
Peak memory 201516 kb
Host smart-03b8c97d-2e14-4991-89d5-516ee9c830a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778873513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.2778873513
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.676622495
Short name T451
Test name
Test status
Simulation time 2033844657 ps
CPU time 5.62 seconds
Started Jun 29 06:31:45 PM PDT 24
Finished Jun 29 06:31:51 PM PDT 24
Peak memory 201676 kb
Host smart-fc23e9ae-cb70-45f1-ade0-f24a0a3a2265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676622495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.676622495
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2040703141
Short name T746
Test name
Test status
Simulation time 2508120417 ps
CPU time 7.13 seconds
Started Jun 29 06:31:47 PM PDT 24
Finished Jun 29 06:31:55 PM PDT 24
Peak memory 201744 kb
Host smart-2e7af437-7810-49f8-a162-92e93734d281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040703141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.2040703141
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.2057635640
Short name T200
Test name
Test status
Simulation time 2116952382 ps
CPU time 4.63 seconds
Started Jun 29 06:31:43 PM PDT 24
Finished Jun 29 06:31:48 PM PDT 24
Peak memory 201464 kb
Host smart-b8f4ce0c-2fc3-465c-a591-6832e03e6e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057635640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.2057635640
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.2083975350
Short name T195
Test name
Test status
Simulation time 1285683920019 ps
CPU time 154.47 seconds
Started Jun 29 06:31:48 PM PDT 24
Finished Jun 29 06:34:23 PM PDT 24
Peak memory 201560 kb
Host smart-440838b5-0db8-4c7c-96ba-59fc188aeb07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083975350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st
ress_all.2083975350
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.318670411
Short name T35
Test name
Test status
Simulation time 31594951832 ps
CPU time 76.94 seconds
Started Jun 29 06:31:47 PM PDT 24
Finished Jun 29 06:33:06 PM PDT 24
Peak memory 210248 kb
Host smart-bb336b84-d4d9-4a5b-9a50-ff6fae27b67a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318670411 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.318670411
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1404347076
Short name T760
Test name
Test status
Simulation time 4414837341 ps
CPU time 7.01 seconds
Started Jun 29 06:31:38 PM PDT 24
Finished Jun 29 06:31:45 PM PDT 24
Peak memory 201560 kb
Host smart-35dfaea3-7bc7-491f-a06f-c65e2f6d7575
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404347076 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ultra_low_pwr.1404347076
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.3297858713
Short name T741
Test name
Test status
Simulation time 69946172467 ps
CPU time 48.23 seconds
Started Jun 29 06:33:26 PM PDT 24
Finished Jun 29 06:34:16 PM PDT 24
Peak memory 201864 kb
Host smart-63775016-e898-4a3d-aac3-0ff0405d4aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297858713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_w
ith_pre_cond.3297858713
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3489518083
Short name T403
Test name
Test status
Simulation time 121202082650 ps
CPU time 333.8 seconds
Started Jun 29 06:33:25 PM PDT 24
Finished Jun 29 06:39:00 PM PDT 24
Peak memory 201880 kb
Host smart-3fb5c569-d161-4936-95da-c42c7949da4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489518083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.3489518083
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3533760404
Short name T284
Test name
Test status
Simulation time 18829999667 ps
CPU time 49.97 seconds
Started Jun 29 06:33:26 PM PDT 24
Finished Jun 29 06:34:18 PM PDT 24
Peak memory 201848 kb
Host smart-06e6aad1-b5c6-4d83-8c57-d3742df3a2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533760404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_w
ith_pre_cond.3533760404
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.1238062921
Short name T378
Test name
Test status
Simulation time 81126470185 ps
CPU time 123.65 seconds
Started Jun 29 06:33:26 PM PDT 24
Finished Jun 29 06:35:30 PM PDT 24
Peak memory 201868 kb
Host smart-46f51276-5ab1-4a4e-ab9a-89f2608df1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238062921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_w
ith_pre_cond.1238062921
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.571167936
Short name T185
Test name
Test status
Simulation time 88400895509 ps
CPU time 124.93 seconds
Started Jun 29 06:33:24 PM PDT 24
Finished Jun 29 06:35:29 PM PDT 24
Peak memory 201860 kb
Host smart-b16b5900-a3a4-4d40-84d2-0d922e7c43c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571167936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_wi
th_pre_cond.571167936
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3521232049
Short name T489
Test name
Test status
Simulation time 43180684766 ps
CPU time 51.99 seconds
Started Jun 29 06:33:26 PM PDT 24
Finished Jun 29 06:34:19 PM PDT 24
Peak memory 201816 kb
Host smart-1256da14-5aa2-430a-aab0-7c92a1be6a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521232049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.3521232049
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.383594073
Short name T408
Test name
Test status
Simulation time 116042413390 ps
CPU time 76.95 seconds
Started Jun 29 06:33:26 PM PDT 24
Finished Jun 29 06:34:45 PM PDT 24
Peak memory 201812 kb
Host smart-3bf7a5e5-a9f8-4762-a696-472667c9731b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383594073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_wi
th_pre_cond.383594073
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.257688393
Short name T203
Test name
Test status
Simulation time 78664313339 ps
CPU time 97.64 seconds
Started Jun 29 06:33:25 PM PDT 24
Finished Jun 29 06:35:03 PM PDT 24
Peak memory 201808 kb
Host smart-a76c6ed5-56ec-4d49-a297-f639d1e5d8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257688393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_wi
th_pre_cond.257688393
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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