Unified Coverage Report :: Cond split page

Go back

 LINE       6677
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T3,T6
1	1	0	Covered	T269,T270,T279
1	1	1	Covered	T1,T3,T6

 LINE       6680
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T2,T13
1	1	0	Covered	T281,T275,T280
1	1	1	Covered	T1,T2,T3

 LINE       6682
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T13,T3,T14
1	1	0	Covered	T29,T269,T279
1	1	1	Covered	T3,T14,T20

 LINE       6695
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T13,T3,T14
1	1	0	Covered	T269,T280,T282
1	1	1	Covered	T3,T14,T21

 LINE       6712
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T5,T2,T13
1	1	0	Covered	T269,T275,T278
1	1	1	Covered	T5,T2,T13

 LINE       6721
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T3,T14,T21
1	1	0	Covered	T278,T279,T283
1	1	1	Covered	T3,T21,T22

 LINE       6730
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T3,T14,T7
1	1	0	Covered	T269,T275,T280
1	1	1	Covered	T3,T7,T10

 LINE       6745
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T2,T13,T3
1	1	0	Covered	T269,T270,T273
1	1	1	Covered	T2,T13,T3

 LINE       6747
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T3,T14,T9
1	1	0	Covered	T269,T275,T280
1	1	1	Covered	T23,T24,T25

 LINE       6750
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T3,T14,T52
1	1	0	Covered	T270,T273,T281
1	1	1	Covered	T23,T24,T25

 LINE       6757
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T2,T13,T3
1	1	0	Covered	T270,T275,T280
1	1	1	Covered	T13,T26,T27

 LINE       6763
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T2,T13,T3
1	1	0	Covered	T269,T270,T275
1	1	1	Covered	T26,T27,T11

 LINE       6769
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T2,T3,T14
1	1	0	Covered	T275,T280,T278
1	1	1	Covered	T26,T27,T11

 LINE       6775
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T2,T13,T3
1	1	0	Covered	T269,T280,T283
1	1	1	Covered	T26,T27,T11

 LINE       6781
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T13,T3,T14
1	1	0	Covered	T269,T281,T284
1	1	1	Covered	T13,T26,T27

 LINE       6783
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T3,T14,T26
1	1	0	Covered	T269,T270,T275
1	1	1	Covered	T26,T27,T11

 LINE       6785
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T3,T14,T26
1	1	0	Covered	T269,T275,T280
1	1	1	Covered	T26,T27,T11

 LINE       6787
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T3,T14,T26
1	1	0	Covered	T269,T275,T285
1	1	1	Covered	T26,T27,T11

 LINE       6789
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T2,T13,T3
1	1	0	Covered	T115,T269,T275
1	1	1	Covered	T2,T13,T3

 LINE       6795
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T2,T13,T3
1	1	0	Covered	T269,T270,T275
1	1	1	Covered	T2,T3,T26

 LINE       6801
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T2,T3,T14
1	1	0	Covered	T270,T275,T279
1	1	1	Covered	T2,T3,T26

 LINE       6807
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T2,T3,T14
1	1	0	Covered	T269,T270,T275
1	1	1	Covered	T2,T3,T26

 LINE       6813
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T2,T13,T3
1	1	0	Covered	T270,T275,T278
1	1	1	Covered	T2,T13,T3

 LINE       6815
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T2,T3,T14
1	1	0	Covered	T269,T270,T275
1	1	1	Covered	T2,T3,T26

 LINE       6817
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T2,T3,T14
1	1	0	Covered	T275,T280,T282
1	1	1	Covered	T2,T3,T26

 LINE       6819
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T2,T3,T14
1	1	0	Covered	T269,T270,T281
1	1	1	Covered	T2,T3,T26

 LINE       6821
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T2,T13,T3
1	1	0	Covered	T269,T270,T284
1	1	1	Covered	T2,T13,T3

 LINE       6826
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T2,T3,T14
1	1	0	Covered	T269,T270,T275
1	1	1	Covered	T2,T3,T26

 LINE       6831
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T2,T3,T14
1	1	0	Covered	T270,T275,T280
1	1	1	Covered	T2,T3,T26

 LINE       6836
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T2,T3,T14
1	1	0	Covered	T269,T275,T286
1	1	1	Covered	T2,T3,T26

 LINE       6841
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T2,T13,T3
1	1	0	Covered	T274,T269,T270
1	1	1	Covered	T2,T3,T7

 LINE       6850
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T3,T14,T52
1	1	0	Covered	T269,T270,T275
1	1	1	Covered	T3,T7,T10

 LINE       7105
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T5,T2