Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
767 |
1 |
|
|
T4 |
9 |
|
T14 |
6 |
|
T7 |
13 |
| auto[1] |
733 |
1 |
|
|
T4 |
11 |
|
T14 |
14 |
|
T7 |
7 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
743 |
1 |
|
|
T4 |
11 |
|
T14 |
8 |
|
T7 |
14 |
| auto[1] |
757 |
1 |
|
|
T4 |
9 |
|
T14 |
12 |
|
T7 |
6 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
749 |
1 |
|
|
T4 |
9 |
|
T14 |
15 |
|
T7 |
10 |
| auto[1] |
751 |
1 |
|
|
T4 |
11 |
|
T14 |
5 |
|
T7 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
718 |
1 |
|
|
T4 |
11 |
|
T14 |
9 |
|
T7 |
10 |
| auto[1] |
782 |
1 |
|
|
T4 |
9 |
|
T14 |
11 |
|
T7 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
789 |
1 |
|
|
T4 |
10 |
|
T14 |
9 |
|
T7 |
14 |
| auto[1] |
711 |
1 |
|
|
T4 |
10 |
|
T14 |
11 |
|
T7 |
6 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
740 |
1 |
|
|
T4 |
8 |
|
T14 |
9 |
|
T7 |
11 |
| auto[1] |
760 |
1 |
|
|
T4 |
12 |
|
T14 |
11 |
|
T7 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
747 |
1 |
|
|
T4 |
6 |
|
T14 |
8 |
|
T7 |
11 |
| auto[1] |
753 |
1 |
|
|
T4 |
14 |
|
T14 |
12 |
|
T7 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
763 |
1 |
|
|
T4 |
13 |
|
T14 |
8 |
|
T7 |
10 |
| auto[1] |
737 |
1 |
|
|
T4 |
7 |
|
T14 |
12 |
|
T7 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
774 |
1 |
|
|
T4 |
7 |
|
T14 |
13 |
|
T7 |
12 |
| auto[1] |
726 |
1 |
|
|
T4 |
13 |
|
T14 |
7 |
|
T7 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
756 |
1 |
|
|
T4 |
8 |
|
T14 |
13 |
|
T7 |
7 |
| auto[1] |
744 |
1 |
|
|
T4 |
12 |
|
T14 |
7 |
|
T7 |
13 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
734 |
1 |
|
|
T4 |
11 |
|
T14 |
10 |
|
T7 |
10 |
| auto[1] |
766 |
1 |
|
|
T4 |
9 |
|
T14 |
10 |
|
T7 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
718 |
1 |
|
|
T4 |
6 |
|
T14 |
9 |
|
T7 |
8 |
| auto[1] |
782 |
1 |
|
|
T4 |
14 |
|
T14 |
11 |
|
T7 |
12 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
772 |
1 |
|
|
T4 |
9 |
|
T14 |
11 |
|
T7 |
9 |
| auto[1] |
728 |
1 |
|
|
T4 |
11 |
|
T14 |
9 |
|
T7 |
11 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
743 |
1 |
|
|
T4 |
11 |
|
T14 |
8 |
|
T7 |
14 |
| auto[1] |
757 |
1 |
|
|
T4 |
9 |
|
T14 |
12 |
|
T7 |
6 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
731 |
1 |
|
|
T4 |
8 |
|
T14 |
11 |
|
T7 |
9 |
| auto[1] |
769 |
1 |
|
|
T4 |
12 |
|
T14 |
9 |
|
T7 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
698 |
1 |
|
|
T4 |
10 |
|
T14 |
7 |
|
T7 |
7 |
| auto[1] |
802 |
1 |
|
|
T4 |
10 |
|
T14 |
13 |
|
T7 |
13 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
730 |
1 |
|
|
T4 |
10 |
|
T14 |
8 |
|
T7 |
9 |
| auto[1] |
770 |
1 |
|
|
T4 |
10 |
|
T14 |
12 |
|
T7 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
767 |
1 |
|
|
T4 |
14 |
|
T14 |
10 |
|
T7 |
12 |
| auto[1] |
733 |
1 |
|
|
T4 |
6 |
|
T14 |
10 |
|
T7 |
8 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
751 |
1 |
|
|
T4 |
9 |
|
T14 |
9 |
|
T7 |
12 |
| auto[1] |
749 |
1 |
|
|
T4 |
11 |
|
T14 |
11 |
|
T7 |
8 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
755 |
1 |
|
|
T4 |
10 |
|
T14 |
11 |
|
T7 |
9 |
| auto[1] |
745 |
1 |
|
|
T4 |
10 |
|
T14 |
9 |
|
T7 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
741 |
1 |
|
|
T4 |
6 |
|
T14 |
8 |
|
T7 |
10 |
| auto[1] |
759 |
1 |
|
|
T4 |
14 |
|
T14 |
12 |
|
T7 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
752 |
1 |
|
|
T4 |
13 |
|
T14 |
13 |
|
T7 |
11 |
| auto[1] |
748 |
1 |
|
|
T4 |
7 |
|
T14 |
7 |
|
T7 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
750 |
1 |
|
|
T4 |
8 |
|
T14 |
10 |
|
T7 |
14 |
| auto[1] |
750 |
1 |
|
|
T4 |
12 |
|
T14 |
10 |
|
T7 |
6 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
718 |
1 |
|
|
T4 |
6 |
|
T14 |
9 |
|
T7 |
8 |
| auto[1] |
782 |
1 |
|
|
T4 |
14 |
|
T14 |
11 |
|
T7 |
12 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
376 |
1 |
|
|
T4 |
4 |
|
T14 |
10 |
|
T7 |
3 |
| auto[0] |
auto[1] |
355 |
1 |
|
|
T4 |
4 |
|
T14 |
1 |
|
T7 |
6 |
| auto[1] |
auto[0] |
373 |
1 |
|
|
T4 |
5 |
|
T14 |
5 |
|
T7 |
7 |
| auto[1] |
auto[1] |
396 |
1 |
|
|
T4 |
7 |
|
T14 |
4 |
|
T7 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
344 |
1 |
|
|
T4 |
6 |
|
T14 |
5 |
|
T7 |
2 |
| auto[0] |
auto[1] |
354 |
1 |
|
|
T4 |
4 |
|
T14 |
2 |
|
T7 |
5 |
| auto[1] |
auto[0] |
374 |
1 |
|
|
T4 |
5 |
|
T14 |
4 |
|
T7 |
8 |
| auto[1] |
auto[1] |
428 |
1 |
|
|
T4 |
5 |
|
T14 |
9 |
|
T7 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
382 |
1 |
|
|
T4 |
3 |
|
T14 |
6 |
|
T7 |
5 |
| auto[0] |
auto[1] |
348 |
1 |
|
|
T4 |
7 |
|
T14 |
2 |
|
T7 |
4 |
| auto[1] |
auto[0] |
407 |
1 |
|
|
T4 |
7 |
|
T14 |
3 |
|
T7 |
9 |
| auto[1] |
auto[1] |
363 |
1 |
|
|
T4 |
3 |
|
T14 |
9 |
|
T7 |
2 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
376 |
1 |
|
|
T4 |
4 |
|
T14 |
7 |
|
T7 |
5 |
| auto[0] |
auto[1] |
391 |
1 |
|
|
T4 |
10 |
|
T14 |
3 |
|
T7 |
7 |
| auto[1] |
auto[0] |
364 |
1 |
|
|
T4 |
4 |
|
T14 |
2 |
|
T7 |
6 |
| auto[1] |
auto[1] |
369 |
1 |
|
|
T4 |
2 |
|
T14 |
8 |
|
T7 |
2 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
375 |
1 |
|
|
T4 |
4 |
|
T14 |
4 |
|
T7 |
8 |
| auto[0] |
auto[1] |
376 |
1 |
|
|
T4 |
5 |
|
T14 |
5 |
|
T7 |
4 |
| auto[1] |
auto[0] |
372 |
1 |
|
|
T4 |
2 |
|
T14 |
4 |
|
T7 |
3 |
| auto[1] |
auto[1] |
377 |
1 |
|
|
T4 |
9 |
|
T14 |
7 |
|
T7 |
5 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
385 |
1 |
|
|
T4 |
8 |
|
T14 |
5 |
|
T7 |
6 |
| auto[0] |
auto[1] |
370 |
1 |
|
|
T4 |
2 |
|
T14 |
6 |
|
T7 |
3 |
| auto[1] |
auto[0] |
378 |
1 |
|
|
T4 |
5 |
|
T14 |
3 |
|
T7 |
4 |
| auto[1] |
auto[1] |
367 |
1 |
|
|
T4 |
5 |
|
T14 |
6 |
|
T7 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
368 |
1 |
|
|
T4 |
5 |
|
T14 |
10 |
|
T7 |
4 |
| auto[0] |
auto[1] |
384 |
1 |
|
|
T4 |
8 |
|
T14 |
3 |
|
T7 |
7 |
| auto[1] |
auto[0] |
388 |
1 |
|
|
T4 |
3 |
|
T14 |
3 |
|
T7 |
3 |
| auto[1] |
auto[1] |
360 |
1 |
|
|
T4 |
4 |
|
T14 |
4 |
|
T7 |
6 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
356 |
1 |
|
|
T4 |
4 |
|
T14 |
7 |
|
T7 |
7 |
| auto[0] |
auto[1] |
394 |
1 |
|
|
T4 |
4 |
|
T14 |
3 |
|
T7 |
7 |
| auto[1] |
auto[0] |
378 |
1 |
|
|
T4 |
7 |
|
T14 |
3 |
|
T7 |
3 |
| auto[1] |
auto[1] |
372 |
1 |
|
|
T4 |
5 |
|
T14 |
7 |
|
T7 |
3 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
403 |
1 |
|
|
T4 |
3 |
|
T14 |
3 |
|
T7 |
7 |
| auto[0] |
auto[1] |
369 |
1 |
|
|
T4 |
6 |
|
T14 |
8 |
|
T7 |
2 |
| auto[1] |
auto[0] |
364 |
1 |
|
|
T4 |
6 |
|
T14 |
3 |
|
T7 |
6 |
| auto[1] |
auto[1] |
364 |
1 |
|
|
T4 |
5 |
|
T14 |
6 |
|
T7 |
5 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
743 |
1 |
|
|
T4 |
11 |
|
T14 |
8 |
|
T7 |
14 |
| auto[1] |
auto[1] |
757 |
1 |
|
|
T4 |
9 |
|
T14 |
12 |
|
T7 |
6 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
370 |
1 |
|
|
T4 |
2 |
|
T14 |
4 |
|
T7 |
7 |
| auto[0] |
auto[1] |
371 |
1 |
|
|
T4 |
4 |
|
T14 |
4 |
|
T7 |
3 |
| auto[1] |
auto[0] |
404 |
1 |
|
|
T4 |
5 |
|
T14 |
9 |
|
T7 |
5 |
| auto[1] |
auto[1] |
355 |
1 |
|
|
T4 |
9 |
|
T14 |
3 |
|
T7 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
718 |
1 |
|
|
T4 |
6 |
|
T14 |
9 |
|
T7 |
8 |
| auto[1] |
auto[1] |
782 |
1 |
|
|
T4 |
14 |
|
T14 |
11 |
|
T7 |
12 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
117 |
1 |
|
|
T8 |
11 |
|
T41 |
7 |
|
T35 |
8 |
| auto[1] |
123 |
1 |
|
|
T8 |
9 |
|
T41 |
13 |
|
T35 |
12 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
124 |
1 |
|
|
T8 |
9 |
|
T41 |
12 |
|
T35 |
6 |
| auto[1] |
116 |
1 |
|
|
T8 |
11 |
|
T41 |
8 |
|
T35 |
14 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
116 |
1 |
|
|
T8 |
6 |
|
T41 |
10 |
|
T35 |
8 |
| auto[1] |
124 |
1 |
|
|
T8 |
14 |
|
T41 |
10 |
|
T35 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
121 |
1 |
|
|
T8 |
8 |
|
T41 |
6 |
|
T35 |
10 |
| auto[1] |
119 |
1 |
|
|
T8 |
12 |
|
T41 |
14 |
|
T35 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
116 |
1 |
|
|
T8 |
9 |
|
T41 |
5 |
|
T35 |
11 |
| auto[1] |
124 |
1 |
|
|
T8 |
11 |
|
T41 |
15 |
|
T35 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
137 |
1 |
|
|
T8 |
10 |
|
T41 |
13 |
|
T35 |
15 |
| auto[1] |
103 |
1 |
|
|
T8 |
10 |
|
T41 |
7 |
|
T35 |
5 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
114 |
1 |
|
|
T8 |
11 |
|
T41 |
9 |
|
T35 |
7 |
| auto[1] |
126 |
1 |
|
|
T8 |
9 |
|
T41 |
11 |
|
T35 |
13 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
116 |
1 |
|
|
T8 |
11 |
|
T41 |
10 |
|
T35 |
11 |
| auto[1] |
124 |
1 |
|
|
T8 |
9 |
|
T41 |
10 |
|
T35 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
134 |
1 |
|
|
T8 |
10 |
|
T41 |
16 |
|
T35 |
14 |
| auto[1] |
106 |
1 |
|
|
T8 |
10 |
|
T41 |
4 |
|
T35 |
6 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
109 |
1 |
|
|
T8 |
9 |
|
T41 |
10 |
|
T35 |
8 |
| auto[1] |
131 |
1 |
|
|
T8 |
11 |
|
T41 |
10 |
|
T35 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
111 |
1 |
|
|
T8 |
13 |
|
T41 |
11 |
|
T35 |
10 |
| auto[1] |
129 |
1 |
|
|
T8 |
7 |
|
T41 |
9 |
|
T35 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
134 |
1 |
|
|
T8 |
14 |
|
T41 |
14 |
|
T35 |
10 |
| auto[1] |
106 |
1 |
|
|
T8 |
6 |
|
T41 |
6 |
|
T35 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123 |
1 |
|
|
T8 |
8 |
|
T41 |
14 |
|
T35 |
11 |
| auto[1] |
117 |
1 |
|
|
T8 |
12 |
|
T41 |
6 |
|
T35 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
124 |
1 |
|
|
T8 |
9 |
|
T41 |
12 |
|
T35 |
6 |
| auto[1] |
116 |
1 |
|
|
T8 |
11 |
|
T41 |
8 |
|
T35 |
14 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
121 |
1 |
|
|
T8 |
11 |
|
T41 |
7 |
|
T35 |
8 |
| auto[1] |
119 |
1 |
|
|
T8 |
9 |
|
T41 |
13 |
|
T35 |
12 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
114 |
1 |
|
|
T8 |
9 |
|
T41 |
11 |
|
T35 |
8 |
| auto[1] |
126 |
1 |
|
|
T8 |
11 |
|
T41 |
9 |
|
T35 |
12 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
113 |
1 |
|
|
T8 |
9 |
|
T41 |
10 |
|
T35 |
7 |
| auto[1] |
127 |
1 |
|
|
T8 |
11 |
|
T41 |
10 |
|
T35 |
13 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
114 |
1 |
|
|
T8 |
8 |
|
T41 |
10 |
|
T35 |
9 |
| auto[1] |
126 |
1 |
|
|
T8 |
12 |
|
T41 |
10 |
|
T35 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
110 |
1 |
|
|
T8 |
7 |
|
T41 |
16 |
|
T35 |
12 |
| auto[1] |
130 |
1 |
|
|
T8 |
13 |
|
T41 |
4 |
|
T35 |
8 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
124 |
1 |
|
|
T8 |
13 |
|
T41 |
13 |
|
T35 |
10 |
| auto[1] |
116 |
1 |
|
|
T8 |
7 |
|
T41 |
7 |
|
T35 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
121 |
1 |
|
|
T8 |
13 |
|
T41 |
8 |
|
T35 |
7 |
| auto[1] |
119 |
1 |
|
|
T8 |
7 |
|
T41 |
12 |
|
T35 |
13 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T8 |
7 |
|
T41 |
9 |
|
T35 |
9 |
| auto[1] |
114 |
1 |
|
|
T8 |
13 |
|
T41 |
11 |
|
T35 |
11 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
114 |
1 |
|
|
T8 |
9 |
|
T41 |
8 |
|
T35 |
9 |
| auto[1] |
126 |
1 |
|
|
T8 |
11 |
|
T41 |
12 |
|
T35 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
134 |
1 |
|
|
T8 |
14 |
|
T41 |
14 |
|
T35 |
10 |
| auto[1] |
106 |
1 |
|
|
T8 |
6 |
|
T41 |
6 |
|
T35 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
58 |
1 |
|
|
T8 |
2 |
|
T41 |
4 |
|
T35 |
3 |
| auto[0] |
auto[1] |
63 |
1 |
|
|
T8 |
9 |
|
T41 |
3 |
|
T35 |
5 |
| auto[1] |
auto[0] |
58 |
1 |
|
|
T8 |
4 |
|
T41 |
6 |
|
T35 |
5 |
| auto[1] |
auto[1] |
61 |
1 |
|
|
T8 |
5 |
|
T41 |
7 |
|
T35 |
7 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
57 |
1 |
|
|
T8 |
2 |
|
T41 |
4 |
|
T35 |
4 |
| auto[0] |
auto[1] |
57 |
1 |
|
|
T8 |
7 |
|
T41 |
7 |
|
T35 |
4 |
| auto[1] |
auto[0] |
64 |
1 |
|
|
T8 |
6 |
|
T41 |
2 |
|
T35 |
6 |
| auto[1] |
auto[1] |
62 |
1 |
|
|
T8 |
5 |
|
T41 |
7 |
|
T35 |
6 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
53 |
1 |
|
|
T8 |
5 |
|
T41 |
2 |
|
T35 |
2 |
| auto[0] |
auto[1] |
60 |
1 |
|
|
T8 |
4 |
|
T41 |
8 |
|
T35 |
5 |
| auto[1] |
auto[0] |
63 |
1 |
|
|
T8 |
4 |
|
T41 |
3 |
|
T35 |
9 |
| auto[1] |
auto[1] |
64 |
1 |
|
|
T8 |
7 |
|
T41 |
7 |
|
T35 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
64 |
1 |
|
|
T8 |
5 |
|
T41 |
6 |
|
T35 |
5 |
| auto[0] |
auto[1] |
50 |
1 |
|
|
T8 |
3 |
|
T41 |
4 |
|
T35 |
4 |
| auto[1] |
auto[0] |
73 |
1 |
|
|
T8 |
5 |
|
T41 |
7 |
|
T35 |
10 |
| auto[1] |
auto[1] |
53 |
1 |
|
|
T8 |
7 |
|
T41 |
3 |
|
T35 |
1 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
45 |
1 |
|
|
T8 |
5 |
|
T41 |
7 |
|
T35 |
2 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T8 |
2 |
|
T41 |
9 |
|
T35 |
10 |
| auto[1] |
auto[0] |
69 |
1 |
|
|
T8 |
6 |
|
T41 |
2 |
|
T35 |
5 |
| auto[1] |
auto[1] |
61 |
1 |
|
|
T8 |
7 |
|
T41 |
2 |
|
T35 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
53 |
1 |
|
|
T8 |
8 |
|
T41 |
6 |
|
T35 |
3 |
| auto[0] |
auto[1] |
71 |
1 |
|
|
T8 |
5 |
|
T41 |
7 |
|
T35 |
7 |
| auto[1] |
auto[0] |
63 |
1 |
|
|
T8 |
3 |
|
T41 |
4 |
|
T35 |
8 |
| auto[1] |
auto[1] |
53 |
1 |
|
|
T8 |
4 |
|
T41 |
3 |
|
T35 |
2 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
56 |
1 |
|
|
T8 |
4 |
|
T41 |
3 |
|
T35 |
3 |
| auto[0] |
auto[1] |
70 |
1 |
|
|
T8 |
3 |
|
T41 |
6 |
|
T35 |
6 |
| auto[1] |
auto[0] |
53 |
1 |
|
|
T8 |
5 |
|
T41 |
7 |
|
T35 |
5 |
| auto[1] |
auto[1] |
61 |
1 |
|
|
T8 |
8 |
|
T41 |
4 |
|
T35 |
6 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
51 |
1 |
|
|
T8 |
7 |
|
T41 |
3 |
|
T35 |
4 |
| auto[0] |
auto[1] |
63 |
1 |
|
|
T8 |
2 |
|
T41 |
5 |
|
T35 |
5 |
| auto[1] |
auto[0] |
60 |
1 |
|
|
T8 |
6 |
|
T41 |
8 |
|
T35 |
6 |
| auto[1] |
auto[1] |
66 |
1 |
|
|
T8 |
5 |
|
T41 |
4 |
|
T35 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
58 |
1 |
|
|
T8 |
3 |
|
T41 |
5 |
|
T35 |
4 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T8 |
5 |
|
T41 |
9 |
|
T35 |
7 |
| auto[1] |
auto[0] |
59 |
1 |
|
|
T8 |
8 |
|
T41 |
2 |
|
T35 |
4 |
| auto[1] |
auto[1] |
58 |
1 |
|
|
T8 |
4 |
|
T41 |
4 |
|
T35 |
5 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
124 |
1 |
|
|
T8 |
9 |
|
T41 |
12 |
|
T35 |
6 |
| auto[1] |
auto[1] |
116 |
1 |
|
|
T8 |
11 |
|
T41 |
8 |
|
T35 |
14 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
65 |
1 |
|
|
T8 |
6 |
|
T41 |
6 |
|
T35 |
5 |
| auto[0] |
auto[1] |
56 |
1 |
|
|
T8 |
7 |
|
T41 |
2 |
|
T35 |
2 |
| auto[1] |
auto[0] |
69 |
1 |
|
|
T8 |
4 |
|
T41 |
10 |
|
T35 |
9 |
| auto[1] |
auto[1] |
50 |
1 |
|
|
T8 |
3 |
|
T41 |
2 |
|
T35 |
4 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
134 |
1 |
|
|
T8 |
14 |
|
T41 |
14 |
|
T35 |
10 |
| auto[1] |
auto[1] |
106 |
1 |
|
|
T8 |
6 |
|
T41 |
6 |
|
T35 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
53 |
1 |
|
|
T41 |
10 |
|
T35 |
9 |
|
T71 |
6 |
| auto[1] |
67 |
1 |
|
|
T41 |
10 |
|
T35 |
11 |
|
T71 |
14 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
59 |
1 |
|
|
T41 |
11 |
|
T35 |
8 |
|
T71 |
8 |
| auto[1] |
61 |
1 |
|
|
T41 |
9 |
|
T35 |
12 |
|
T71 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
68 |
1 |
|
|
T41 |
12 |
|
T35 |
12 |
|
T71 |
10 |
| auto[1] |
52 |
1 |
|
|
T41 |
8 |
|
T35 |
8 |
|
T71 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
53 |
1 |
|
|
T41 |
10 |
|
T35 |
9 |
|
T71 |
10 |
| auto[1] |
67 |
1 |
|
|
T41 |
10 |
|
T35 |
11 |
|
T71 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
60 |
1 |
|
|
T41 |
6 |
|
T35 |
17 |
|
T71 |
11 |
| auto[1] |
60 |
1 |
|
|
T41 |
14 |
|
T35 |
3 |
|
T71 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
69 |
1 |
|
|
T41 |
11 |
|
T35 |
12 |
|
T71 |
12 |
| auto[1] |
51 |
1 |
|
|
T41 |
9 |
|
T35 |
8 |
|
T71 |
8 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
60 |
1 |
|
|
T41 |
11 |
|
T35 |
12 |
|
T71 |
12 |
| auto[1] |
60 |
1 |
|
|
T41 |
9 |
|
T35 |
8 |
|
T71 |
8 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
67 |
1 |
|
|
T41 |
9 |
|
T35 |
10 |
|
T71 |
11 |
| auto[1] |
53 |
1 |
|
|
T41 |
11 |
|
T35 |
10 |
|
T71 |
9 |