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Summary for Variable cp_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1303 1 T1 26 T16 8 T4 22
auto[1] 1897 1 T1 55 T16 10 T9 4



Summary for Variable cp_combo0_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_combo0_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2654 1 T1 51 T16 18 T4 22
auto[1] 546 1 T1 30 T9 1 T10 1



Summary for Variable cp_combo1_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_combo1_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3009 1 T1 79 T16 18 T4 21
auto[1] 191 1 T1 2 T4 1 T10 1



Summary for Variable cp_combo2_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_combo2_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3024 1 T1 73 T16 18 T4 18
auto[1] 176 1 T1 8 T4 4 T9 2



Summary for Variable cp_combo3_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_combo3_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3056 1 T1 74 T16 18 T4 21
auto[1] 144 1 T1 7 T4 1 T11 1



Summary for Variable cp_interrupt

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_interrupt

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1913 1 T1 53 T16 18 T4 22
auto[1] 1287 1 T1 28 T25 9 T9 3



Summary for Variable cp_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1467 1 T1 39 T16 14 T4 4
auto[1] 1733 1 T1 42 T16 4 T4 18



Summary for Variable cp_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1329 1 T1 32 T16 5 T4 19
auto[1] 1871 1 T1 49 T16 13 T4 3



Summary for Variable cp_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1352 1 T1 28 T16 9 T4 7
auto[1] 1848 1 T1 53 T16 9 T4 15



Summary for Variable cp_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_in_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1377 1 T1 30 T16 4 T4 10
auto[1] 1823 1 T1 51 T16 14 T4 12



Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 0 96 100.00
Automatically Generated Cross Bins 96 0 96 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo0

Bins
cp_combo0_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 50 1 T1 2 T16 1 T4 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 15 1 T21 1 T344 1 T255 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 53 1 T1 3 T10 1 T43 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 18 1 T1 1 T100 1 T240 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 45 1 T16 1 T38 1 T39 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 28 1 T42 4 T100 1 T59 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 43 1 T10 2 T11 1 T37 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 24 1 T9 1 T33 1 T241 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 60 1 T16 1 T4 1 T39 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 19 1 T100 1 T240 1 T270 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 44 1 T1 2 T11 1 T113 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 17 1 T270 1 T89 1 T345 3
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 54 1 T4 2 T37 1 T42 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 19 1 T100 1 T240 1 T241 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 61 1 T1 1 T33 2 T68 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 32 1 T1 1 T240 1 T241 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 55 1 T1 1 T25 1 T11 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 15 1 T270 1 T255 1 T243 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 38 1 T16 2 T10 1 T39 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 27 1 T59 1 T271 1 T255 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 54 1 T1 2 T16 1 T10 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 18 1 T1 2 T240 1 T346 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 32 1 T1 1 T10 1 T42 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 28 1 T1 1 T33 1 T347 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 52 1 T37 1 T68 1 T236 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 20 1 T240 2 T347 3 T270 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 69 1 T10 1 T43 10 T74 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 44 1 T1 2 T74 8 T347 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 28 1 T1 1 T16 2 T10 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 29 1 T1 1 T100 2 T247 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 90 1 T1 3 T16 6 T12 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 68 1 T12 8 T21 1 T74 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 43 1 T1 1 T4 3 T38 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 20 1 T1 1 T59 1 T270 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 57 1 T1 1 T10 1 T37 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 18 1 T241 1 T344 1 T243 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 44 1 T16 2 T10 2 T38 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 16 1 T89 1 T255 1 T348 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 36 1 T1 2 T37 1 T113 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 21 1 T113 1 T89 1 T241 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 35 1 T1 2 T4 2 T10 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 23 1 T100 2 T240 1 T347 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 39 1 T33 3 T349 1 T267 13
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 29 1 T240 1 T270 1 T350 2
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 29 1 T4 10 T10 2 T269 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 18 1 T1 1 T100 1 T270 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 43 1 T1 1 T10 2 T11 6
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 62 1 T42 2 T113 4 T235 8
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 46 1 T1 1 T4 3 T9 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 23 1 T39 2 T59 1 T270 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 46 1 T1 1 T10 2 T85 9
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 33 1 T9 1 T39 2 T240 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 41 1 T25 1 T39 2 T33 3
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 26 1 T39 1 T100 1 T240 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 54 1 T16 2 T37 1 T42 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 64 1 T42 3 T240 1 T347 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 78 1 T1 2 T33 1 T235 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 17 1 T270 1 T351 5 T89 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 38 1 T68 1 T269 1 T144 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 29 1 T100 1 T240 1 T347 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 66 1 T1 1 T33 5 T68 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 33 1 T25 9 T240 1 T347 3
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 264 1 T1 13 T9 2 T10 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 14 1 T100 1 T344 1 T255 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 6 1 T59 2 T352 2 T353 2
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 10 1 T1 1 T59 1 T270 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 5 1 T59 1 T352 1 T244 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 5 1 T347 1 T354 1 T348 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 8 1 T1 1 T33 1 T59 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 8 1 T1 1 T59 1 T89 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 16 1 T33 1 T100 2 T59 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 8 1 T1 3 T100 1 T344 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 8 1 T39 1 T352 1 T355 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 14 1 T1 1 T39 3 T59 2
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 6 1 T100 1 T352 2 T354 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 12 1 T100 1 T270 1 T345 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 7 1 T1 1 T240 1 T271 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 19 1 T74 10 T356 2 T357 2
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 9 1 T59 1 T247 1 T356 2
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 12 1 T100 1 T74 3 T347 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 6 1 T59 1 T271 2 T348 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 19 1 T113 6 T358 1 T352 2
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 9 1 T59 1 T89 1 T356 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 15 1 T21 1 T33 1 T113 5
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 11 1 T240 1 T347 1 T270 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 7 1 T59 1 T350 3 T352 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 10 1 T1 1 T9 1 T33 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 10 1 T42 1 T33 1 T59 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 7 1 T39 2 T352 1 T354 2
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 10 1 T39 1 T100 1 T241 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 3 1 T354 1 T273 1 T359 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 7 1 T240 1 T346 1 T255 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 4 1 T350 1 T352 1 T243 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 8 1 T356 1 T243 2 T131 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 7 1 T255 1 T243 1 T348 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 134 1 T1 9 T21 1 T33 1


User Defined Cross Bins for cross_combo0

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded



Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 25 71 73.96 25
Automatically Generated Cross Bins 96 25 71 73.96 25
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo1

Element holes
cp_combo1_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[1]] * [auto[1]] -- -- 2
[auto[1]] [auto[0]] [auto[1]] [auto[1]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[0]] [auto[0]] * [auto[1]] [auto[1]] -- -- 2
[auto[1]] [auto[1]] [auto[0]] [auto[1]] [auto[1]] * [auto[1]] -- -- 2
[auto[1]] [auto[1]] [auto[1]] [auto[0]] * * [auto[1]] -- -- 4


Uncovered bins
cp_combo1_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[1]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo1_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 52 1 T1 2 T16 1 T4 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 21 1 T21 1 T59 2 T352 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 57 1 T1 4 T10 1 T43 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 28 1 T1 2 T100 1 T59 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 54 1 T16 1 T37 1 T38 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 33 1 T42 4 T100 1 T59 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 44 1 T10 2 T11 1 T37 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 29 1 T9 1 T33 1 T347 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 63 1 T16 1 T4 1 T39 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 27 1 T1 1 T33 1 T100 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 47 1 T1 3 T11 1 T113 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 25 1 T1 1 T59 1 T270 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 55 1 T1 1 T4 2 T37 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 35 1 T33 1 T100 3 T59 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 55 1 T1 2 T33 2 T68 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 40 1 T1 4 T100 1 T240 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 58 1 T1 1 T25 1 T11 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 22 1 T270 1 T352 1 T355 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 45 1 T1 1 T16 2 T10 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 40 1 T1 1 T39 2 T59 3
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 56 1 T1 3 T16 1 T10 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 24 1 T1 2 T100 1 T240 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 41 1 T1 1 T10 1 T37 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 40 1 T1 1 T33 1 T100 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 46 1 T1 1 T37 1 T68 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 27 1 T1 1 T240 3 T347 3
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 70 1 T10 1 T43 11 T74 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 63 1 T1 2 T74 18 T347 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 31 1 T1 1 T16 2 T10 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 38 1 T1 1 T100 2 T59 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 88 1 T1 3 T16 6 T12 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 80 1 T12 8 T21 1 T100 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 47 1 T1 1 T4 2 T37 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 25 1 T1 1 T59 2 T270 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 58 1 T1 1 T10 1 T37 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 37 1 T113 6 T241 1 T358 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 48 1 T16 2 T10 3 T38 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 24 1 T59 1 T89 2 T356 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 42 1 T1 3 T37 1 T113 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 36 1 T21 1 T33 1 T113 6
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 38 1 T1 2 T4 2 T10 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 32 1 T100 2 T240 2 T347 3
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 37 1 T33 4 T68 1 T349 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 36 1 T59 1 T240 1 T270 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 32 1 T4 10 T10 2 T33 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 28 1 T1 2 T9 1 T33 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 45 1 T1 2 T10 2 T11 6
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 72 1 T42 3 T33 1 T113 4
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 50 1 T1 2 T4 3 T9 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 30 1 T39 4 T59 1 T270 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 47 1 T1 1 T10 2 T33 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 43 1 T9 1 T39 3 T100 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 44 1 T25 1 T39 2 T33 3
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 29 1 T39 1 T100 1 T240 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 54 1 T1 1 T16 2 T37 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 71 1 T42 3 T240 2 T347 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 80 1 T1 2 T33 1 T235 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 20 1 T270 1 T351 5 T89 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 38 1 T37 1 T68 1 T269 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 37 1 T100 1 T240 1 T347 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 71 1 T1 2 T37 1 T33 5
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 40 1 T25 9 T240 1 T347 3
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 154 1 T1 11 T9 2 T37 5
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 130 1 T1 9 T33 1 T100 2
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 1 1 T39 1 - - - -
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 1 1 T39 1 - - - -
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 1 1 T360 1 - - - -
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 1 1 T109 1 - - - -
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 2 1 T350 2 - - - -
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 1 1 T350 1 - - - -
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 18 1 T21 1 T59 4 T347 2


User Defined Cross Bins for cross_combo1

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded



Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 27 69 71.88 27
Automatically Generated Cross Bins 96 27 69 71.88 27
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo2

Element holes
cp_combo2_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[1]] * [auto[1]] -- -- 2
[auto[1]] [auto[0]] [auto[1]] [auto[1]] [auto[1]] * [auto[1]] -- -- 2
[auto[1]] [auto[1]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] * [auto[1]] -- -- 2
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[1]] -- -- 2


Uncovered bins
cp_combo2_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[0]] [auto[1]] [auto[1]] 0 1 1
[auto[1]] [auto[0]] [auto[1]] [auto[1]] [auto[0]] [auto[0]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo2_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 52 1 T1 2 T16 1 T4 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 21 1 T21 1 T59 2 T352 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 55 1 T1 4 T10 1 T43 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 28 1 T1 2 T100 1 T59 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 53 1 T16 1 T37 1 T38 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 33 1 T42 4 T100 1 T59 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 45 1 T10 2 T11 1 T37 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 29 1 T9 1 T33 1 T347 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 60 1 T16 1 T4 1 T39 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 27 1 T1 1 T33 1 T100 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 45 1 T1 3 T11 1 T113 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 25 1 T1 1 T59 1 T270 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 56 1 T1 1 T4 1 T37 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 35 1 T33 1 T100 3 T59 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 63 1 T1 2 T33 2 T68 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 40 1 T1 4 T100 1 T240 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 58 1 T1 1 T25 1 T11 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 22 1 T39 1 T270 1 T352 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 45 1 T1 1 T16 2 T10 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 41 1 T1 1 T39 3 T59 3
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 56 1 T1 3 T16 1 T10 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 24 1 T1 2 T100 1 T240 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 39 1 T1 1 T10 1 T37 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 40 1 T1 1 T33 1 T100 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 53 1 T1 1 T37 1 T68 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 27 1 T1 1 T240 3 T347 3
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 66 1 T10 1 T43 10 T74 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 58 1 T1 2 T74 13 T347 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 31 1 T1 1 T16 2 T10 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 38 1 T1 1 T100 2 T59 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 82 1 T1 3 T16 6 T12 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 80 1 T12 8 T21 1 T100 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 47 1 T1 1 T4 2 T37 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 26 1 T1 1 T59 2 T270 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 61 1 T1 1 T10 1 T37 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 37 1 T113 6 T241 1 T358 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 48 1 T16 2 T10 3 T38 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 25 1 T59 1 T89 2 T356 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 43 1 T1 3 T37 1 T113 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 36 1 T21 1 T33 1 T113 6
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 38 1 T1 2 T4 2 T10 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 34 1 T100 2 T240 2 T347 3
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 36 1 T33 4 T68 1 T349 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 36 1 T59 1 T240 1 T270 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 30 1 T4 8 T10 2 T33 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 28 1 T1 2 T9 1 T33 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 43 1 T1 2 T10 2 T11 6
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 72 1 T42 3 T33 1 T113 4
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 49 1 T1 2 T4 3 T9 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 29 1 T39 4 T59 1 T270 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 51 1 T1 1 T10 2 T33 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 42 1 T9 1 T39 3 T100 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 41 1 T25 1 T39 2 T33 3
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 29 1 T39 1 T100 1 T240 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 55 1 T1 1 T16 2 T37 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 71 1 T42 3 T240 2 T347 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 73 1 T1 2 T33 1 T235 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 21 1 T270 1 T350 1 T351 5
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 40 1 T37 1 T68 1 T269 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 37 1 T100 1 T240 1 T347 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 71 1 T1 2 T37 1 T33 5
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 40 1 T25 9 T240 1 T347 3
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 178 1 T1 5 T10 1 T37 3
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 130 1 T1 9 T21 1 T100 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 1 1 T355 1 - - - -
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 5 1 T74 5 - - - -
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 1 1 T109 1 - - - -
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 1 1 T361 1 - - - -
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 18 1 T33 1 T100 1 T59 4


User Defined Cross Bins for cross_combo2

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded



Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 24 72 75.00 24
Automatically Generated Cross Bins 96 24 72 75.00 24
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo3

Element holes
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[0]] [auto[0]] * * [auto[1]] -- -- 4
[auto[1]] [auto[0]] [auto[0]] [auto[1]] [auto[0]] * [auto[1]] -- -- 2
[auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[1]] * [auto[1]] -- -- 2
[auto[1]] [auto[0]] [auto[1]] [auto[1]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[0]] [auto[1]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] * [auto[1]] -- -- 2
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[1]] -- -- 2


Uncovered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[0]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] 0 1 1
[auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[0]] [auto[1]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[0]] [auto[0]] [auto[0]] [auto[1]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 52 1 T1 2 T16 1 T4 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 21 1 T21 1 T59 2 T352 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 56 1 T1 4 T10 1 T43 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 28 1 T1 2 T100 1 T59 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 54 1 T16 1 T37 1 T38 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 33 1 T42 4 T100 1 T59 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 43 1 T10 2 T11 1 T37 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 29 1 T9 1 T33 1 T347 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 63 1 T16 1 T4 1 T39 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 27 1 T1 1 T33 1 T100 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 47 1 T1 3 T11 1 T113 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 25 1 T1 1 T59 1 T270 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 57 1 T1 1 T4 2 T37 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 33 1 T33 1 T100 3 T59 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 61 1 T1 2 T33 2 T68 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 40 1 T1 4 T100 1 T240 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 58 1 T1 1 T25 1 T11 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 22 1 T270 1 T352 1 T355 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 44 1 T1 1 T16 2 T10 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 41 1 T1 1 T39 3 T59 3
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 54 1 T1 3 T16 1 T10 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 24 1 T1 2 T100 1 T240 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 41 1 T1 1 T10 1 T37 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 40 1 T1 1 T33 1 T100 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 53 1 T1 1 T37 1 T68 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 27 1 T1 1 T240 3 T347 3
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 69 1 T10 1 T43 11 T74 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 63 1 T1 2 T74 18 T347 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 31 1 T1 1 T16 2 T10 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 38 1 T1 1 T100 2 T59 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 90 1 T1 3 T16 6 T12 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 80 1 T12 8 T21 1 T100 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 47 1 T1 1 T4 2 T37 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 25 1 T1 1 T59 2 T270 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 60 1 T1 1 T10 1 T37 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 37 1 T113 6 T241 1 T358 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 50 1 T16 2 T10 3 T38 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 24 1 T59 1 T89 2 T356 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 42 1 T1 3 T37 1 T113 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 35 1 T21 1 T33 1 T113 6
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 38 1 T1 2 T4 2 T10 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 34 1 T100 2 T240 2 T347 3
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 41 1 T33 4 T68 1 T349 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 36 1 T59 1 T240 1 T270 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 31 1 T4 10 T10 2 T33 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 28 1 T1 2 T9 1 T33 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 41 1 T1 2 T10 2 T11 5
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 72 1 T42 3 T33 1 T113 4
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 49 1 T1 2 T4 3 T9 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 29 1 T39 3 T59 1 T270 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 50 1 T1 1 T10 2 T33 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 42 1 T9 1 T39 3 T100 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 41 1 T25 1 T39 1 T33 3
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 29 1 T39 1 T100 1 T240 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 57 1 T1 1 T16 2 T37 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 71 1 T42 3 T240 2 T347 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 81 1 T1 2 T33 1 T235 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 21 1 T270 1 T350 1 T351 5
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 39 1 T37 1 T68 1 T269 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 37 1 T100 1 T240 1 T347 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 67 1 T1 2 T37 1 T33 5
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 40 1 T25 9 T240 1 T347 3
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 194 1 T1 6 T9 2 T10 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 124 1 T1 9 T33 1 T100 2
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 2 1 T362 1 T153 1 - -
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 1 1 T39 1 - - - -
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 1 1 T360 1 - - - -
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 1 1 T109 1 - - - -
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 1 1 T109 1 - - - -
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 1 1 T39 1 - - - -
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 1 1 T363 1 - - - -
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 24 1 T21 1 T347 1 T210 1


User Defined Cross Bins for cross_combo3

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%