Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.ac_present
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key0_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key0_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key1_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key1_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key2_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key2_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.lid_open
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_ac_present
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_bat_disable
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key0_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key0_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key1_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key1_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key2_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key2_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_lid_open
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_pwrb_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_pwrb_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_z3_wakeup
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key0_inXval
Uncovered bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key0_outXval
Uncovered bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key1_inXval
Uncovered bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key1_outXval
Uncovered bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key2_inXval
Uncovered bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key2_outXval
Uncovered bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for pwrb_inXval
Uncovered bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for pwrb_outXval
Uncovered bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for ac_presentXval
Uncovered bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
2 |
0 |
0.00 |
2 |
| Automatically Generated Cross Bins |
2 |
2 |
0 |
0.00 |
2 |
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Uncovered bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0]] |
[auto[0]] |
0 |
1 |
1 |
|
| [auto[1]] |
[auto[1]] |
0 |
1 |
1 |
|
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for lid_openXval
Uncovered bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
2 |
0 |
0.00 |
2 |
| Automatically Generated Cross Bins |
2 |
2 |
0 |
0.00 |
2 |
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Uncovered bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0]] |
[auto[0]] |
0 |
1 |
1 |
|
| [auto[1]] |
[auto[1]] |
0 |
1 |
1 |
|
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
857 |
1 |
|
|
T24 |
11 |
|
T9 |
11 |
|
T25 |
6 |
| auto[1] |
903 |
1 |
|
|
T24 |
9 |
|
T9 |
9 |
|
T25 |
14 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
895 |
1 |
|
|
T24 |
12 |
|
T9 |
14 |
|
T25 |
10 |
| auto[1] |
865 |
1 |
|
|
T24 |
8 |
|
T9 |
6 |
|
T25 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
909 |
1 |
|
|
T24 |
11 |
|
T9 |
9 |
|
T25 |
8 |
| auto[1] |
851 |
1 |
|
|
T24 |
9 |
|
T9 |
11 |
|
T25 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
833 |
1 |
|
|
T24 |
12 |
|
T9 |
10 |
|
T25 |
10 |
| auto[1] |
927 |
1 |
|
|
T24 |
8 |
|
T9 |
10 |
|
T25 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
865 |
1 |
|
|
T24 |
9 |
|
T9 |
13 |
|
T25 |
12 |
| auto[1] |
895 |
1 |
|
|
T24 |
11 |
|
T9 |
7 |
|
T25 |
8 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
893 |
1 |
|
|
T24 |
7 |
|
T9 |
8 |
|
T25 |
12 |
| auto[1] |
867 |
1 |
|
|
T24 |
13 |
|
T9 |
12 |
|
T25 |
8 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
882 |
1 |
|
|
T24 |
11 |
|
T9 |
11 |
|
T25 |
8 |
| auto[1] |
878 |
1 |
|
|
T24 |
9 |
|
T9 |
9 |
|
T25 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
922 |
1 |
|
|
T24 |
11 |
|
T9 |
8 |
|
T25 |
11 |
| auto[1] |
838 |
1 |
|
|
T24 |
9 |
|
T9 |
12 |
|
T25 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
860 |
1 |
|
|
T24 |
10 |
|
T9 |
8 |
|
T25 |
7 |
| auto[1] |
900 |
1 |
|
|
T24 |
10 |
|
T9 |
12 |
|
T25 |
13 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
848 |
1 |
|
|
T24 |
10 |
|
T9 |
8 |
|
T25 |
9 |
| auto[1] |
912 |
1 |
|
|
T24 |
10 |
|
T9 |
12 |
|
T25 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
904 |
1 |
|
|
T24 |
10 |
|
T9 |
11 |
|
T25 |
13 |
| auto[1] |
856 |
1 |
|
|
T24 |
10 |
|
T9 |
9 |
|
T25 |
7 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
885 |
1 |
|
|
T24 |
11 |
|
T9 |
6 |
|
T25 |
13 |
| auto[1] |
875 |
1 |
|
|
T24 |
9 |
|
T9 |
14 |
|
T25 |
7 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
876 |
1 |
|
|
T24 |
16 |
|
T9 |
10 |
|
T25 |
13 |
| auto[1] |
884 |
1 |
|
|
T24 |
4 |
|
T9 |
10 |
|
T25 |
7 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
895 |
1 |
|
|
T24 |
12 |
|
T9 |
14 |
|
T25 |
10 |
| auto[1] |
865 |
1 |
|
|
T24 |
8 |
|
T9 |
6 |
|
T25 |
10 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
879 |
1 |
|
|
T24 |
11 |
|
T9 |
7 |
|
T25 |
7 |
| auto[1] |
881 |
1 |
|
|
T24 |
9 |
|
T9 |
13 |
|
T25 |
13 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
865 |
1 |
|
|
T24 |
8 |
|
T9 |
12 |
|
T25 |
11 |
| auto[1] |
895 |
1 |
|
|
T24 |
12 |
|
T9 |
8 |
|
T25 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
863 |
1 |
|
|
T24 |
13 |
|
T9 |
7 |
|
T25 |
12 |
| auto[1] |
897 |
1 |
|
|
T24 |
7 |
|
T9 |
13 |
|
T25 |
8 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
861 |
1 |
|
|
T24 |
5 |
|
T9 |
10 |
|
T25 |
8 |
| auto[1] |
899 |
1 |
|
|
T24 |
15 |
|
T9 |
10 |
|
T25 |
12 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
898 |
1 |
|
|
T24 |
6 |
|
T9 |
15 |
|
T25 |
16 |
| auto[1] |
862 |
1 |
|
|
T24 |
14 |
|
T9 |
5 |
|
T25 |
4 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
904 |
1 |
|
|
T24 |
8 |
|
T9 |
12 |
|
T25 |
11 |
| auto[1] |
856 |
1 |
|
|
T24 |
12 |
|
T9 |
8 |
|
T25 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
896 |
1 |
|
|
T24 |
10 |
|
T9 |
14 |
|
T25 |
7 |
| auto[1] |
864 |
1 |
|
|
T24 |
10 |
|
T9 |
6 |
|
T25 |
13 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
893 |
1 |
|
|
T24 |
8 |
|
T9 |
9 |
|
T25 |
9 |
| auto[1] |
867 |
1 |
|
|
T24 |
12 |
|
T9 |
11 |
|
T25 |
11 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
897 |
1 |
|
|
T24 |
10 |
|
T9 |
12 |
|
T25 |
7 |
| auto[1] |
863 |
1 |
|
|
T24 |
10 |
|
T9 |
8 |
|
T25 |
13 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
885 |
1 |
|
|
T24 |
11 |
|
T9 |
6 |
|
T25 |
13 |
| auto[1] |
875 |
1 |
|
|
T24 |
9 |
|
T9 |
14 |
|
T25 |
7 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
452 |
1 |
|
|
T24 |
4 |
|
T9 |
2 |
|
T25 |
5 |
| auto[0] |
auto[1] |
427 |
1 |
|
|
T24 |
7 |
|
T9 |
5 |
|
T25 |
2 |
| auto[1] |
auto[0] |
457 |
1 |
|
|
T24 |
7 |
|
T9 |
7 |
|
T25 |
3 |
| auto[1] |
auto[1] |
424 |
1 |
|
|
T24 |
2 |
|
T9 |
6 |
|
T25 |
10 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
407 |
1 |
|
|
T24 |
3 |
|
T9 |
5 |
|
T25 |
8 |
| auto[0] |
auto[1] |
458 |
1 |
|
|
T24 |
5 |
|
T9 |
7 |
|
T25 |
3 |
| auto[1] |
auto[0] |
426 |
1 |
|
|
T24 |
9 |
|
T9 |
5 |
|
T25 |
2 |
| auto[1] |
auto[1] |
469 |
1 |
|
|
T24 |
3 |
|
T9 |
3 |
|
T25 |
7 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
413 |
1 |
|
|
T24 |
6 |
|
T9 |
5 |
|
T25 |
7 |
| auto[0] |
auto[1] |
450 |
1 |
|
|
T24 |
7 |
|
T9 |
2 |
|
T25 |
5 |
| auto[1] |
auto[0] |
452 |
1 |
|
|
T24 |
3 |
|
T9 |
8 |
|
T25 |
5 |
| auto[1] |
auto[1] |
445 |
1 |
|
|
T24 |
4 |
|
T9 |
5 |
|
T25 |
3 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
426 |
1 |
|
|
T24 |
1 |
|
T9 |
4 |
|
T25 |
5 |
| auto[0] |
auto[1] |
435 |
1 |
|
|
T24 |
4 |
|
T9 |
6 |
|
T25 |
3 |
| auto[1] |
auto[0] |
467 |
1 |
|
|
T24 |
6 |
|
T9 |
4 |
|
T25 |
7 |
| auto[1] |
auto[1] |
432 |
1 |
|
|
T24 |
9 |
|
T9 |
6 |
|
T25 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
449 |
1 |
|
|
T24 |
2 |
|
T9 |
8 |
|
T25 |
4 |
| auto[0] |
auto[1] |
449 |
1 |
|
|
T24 |
4 |
|
T9 |
7 |
|
T25 |
12 |
| auto[1] |
auto[0] |
433 |
1 |
|
|
T24 |
9 |
|
T9 |
3 |
|
T25 |
4 |
| auto[1] |
auto[1] |
429 |
1 |
|
|
T24 |
5 |
|
T9 |
2 |
|
T40 |
11 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
472 |
1 |
|
|
T24 |
3 |
|
T9 |
5 |
|
T25 |
3 |
| auto[0] |
auto[1] |
432 |
1 |
|
|
T24 |
5 |
|
T9 |
7 |
|
T25 |
8 |
| auto[1] |
auto[0] |
450 |
1 |
|
|
T24 |
8 |
|
T9 |
3 |
|
T25 |
8 |
| auto[1] |
auto[1] |
406 |
1 |
|
|
T24 |
4 |
|
T9 |
5 |
|
T25 |
1 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
437 |
1 |
|
|
T24 |
5 |
|
T9 |
5 |
|
T25 |
4 |
| auto[0] |
auto[1] |
456 |
1 |
|
|
T24 |
3 |
|
T9 |
4 |
|
T25 |
5 |
| auto[1] |
auto[0] |
411 |
1 |
|
|
T24 |
5 |
|
T9 |
3 |
|
T25 |
5 |
| auto[1] |
auto[1] |
456 |
1 |
|
|
T24 |
7 |
|
T9 |
8 |
|
T25 |
6 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
467 |
1 |
|
|
T24 |
6 |
|
T9 |
8 |
|
T25 |
5 |
| auto[0] |
auto[1] |
430 |
1 |
|
|
T24 |
4 |
|
T9 |
4 |
|
T25 |
2 |
| auto[1] |
auto[0] |
437 |
1 |
|
|
T24 |
4 |
|
T9 |
3 |
|
T25 |
8 |
| auto[1] |
auto[1] |
426 |
1 |
|
|
T24 |
6 |
|
T9 |
5 |
|
T25 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
425 |
1 |
|
|
T24 |
9 |
|
T9 |
6 |
|
T25 |
4 |
| auto[0] |
auto[1] |
451 |
1 |
|
|
T24 |
7 |
|
T9 |
4 |
|
T25 |
9 |
| auto[1] |
auto[0] |
432 |
1 |
|
|
T24 |
2 |
|
T9 |
5 |
|
T25 |
2 |
| auto[1] |
auto[1] |
452 |
1 |
|
|
T24 |
2 |
|
T9 |
5 |
|
T25 |
5 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
895 |
1 |
|
|
T24 |
12 |
|
T9 |
14 |
|
T25 |
10 |
| auto[1] |
auto[1] |
865 |
1 |
|
|
T24 |
8 |
|
T9 |
6 |
|
T25 |
10 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
430 |
1 |
|
|
T24 |
4 |
|
T9 |
6 |
|
T25 |
3 |
| auto[0] |
auto[1] |
466 |
1 |
|
|
T24 |
6 |
|
T9 |
8 |
|
T25 |
4 |
| auto[1] |
auto[0] |
430 |
1 |
|
|
T24 |
6 |
|
T9 |
2 |
|
T25 |
4 |
| auto[1] |
auto[1] |
434 |
1 |
|
|
T24 |
4 |
|
T9 |
4 |
|
T25 |
9 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
885 |
1 |
|
|
T24 |
11 |
|
T9 |
6 |
|
T25 |
13 |
| auto[1] |
auto[1] |
875 |
1 |
|
|
T24 |
9 |
|
T9 |
14 |
|
T25 |
7 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
216 |
1 |
|
|
T40 |
11 |
|
T10 |
11 |
|
T44 |
9 |
| auto[1] |
204 |
1 |
|
|
T40 |
9 |
|
T10 |
9 |
|
T44 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
199 |
1 |
|
|
T40 |
11 |
|
T10 |
12 |
|
T44 |
13 |
| auto[1] |
221 |
1 |
|
|
T40 |
9 |
|
T10 |
8 |
|
T44 |
7 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
220 |
1 |
|
|
T40 |
9 |
|
T10 |
7 |
|
T44 |
9 |
| auto[1] |
200 |
1 |
|
|
T40 |
11 |
|
T10 |
13 |
|
T44 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
219 |
1 |
|
|
T40 |
8 |
|
T10 |
10 |
|
T44 |
15 |
| auto[1] |
201 |
1 |
|
|
T40 |
12 |
|
T10 |
10 |
|
T44 |
5 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
190 |
1 |
|
|
T40 |
9 |
|
T10 |
10 |
|
T44 |
11 |
| auto[1] |
230 |
1 |
|
|
T40 |
11 |
|
T10 |
10 |
|
T44 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
223 |
1 |
|
|
T40 |
10 |
|
T10 |
15 |
|
T44 |
11 |
| auto[1] |
197 |
1 |
|
|
T40 |
10 |
|
T10 |
5 |
|
T44 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
219 |
1 |
|
|
T40 |
11 |
|
T10 |
3 |
|
T44 |
14 |
| auto[1] |
201 |
1 |
|
|
T40 |
9 |
|
T10 |
17 |
|
T44 |
6 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
222 |
1 |
|
|
T40 |
11 |
|
T10 |
10 |
|
T44 |
14 |
| auto[1] |
198 |
1 |
|
|
T40 |
9 |
|
T10 |
10 |
|
T44 |
6 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
217 |
1 |
|
|
T40 |
7 |
|
T10 |
11 |
|
T44 |
10 |
| auto[1] |
203 |
1 |
|
|
T40 |
13 |
|
T10 |
9 |
|
T44 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
222 |
1 |
|
|
T40 |
12 |
|
T10 |
10 |
|
T44 |
10 |
| auto[1] |
198 |
1 |
|
|
T40 |
8 |
|
T10 |
10 |
|
T44 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
219 |
1 |
|
|
T40 |
8 |
|
T10 |
8 |
|
T44 |
12 |
| auto[1] |
201 |
1 |
|
|
T40 |
12 |
|
T10 |
12 |
|
T44 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
210 |
1 |
|
|
T40 |
10 |
|
T10 |
8 |
|
T44 |
14 |
| auto[1] |
210 |
1 |
|
|
T40 |
10 |
|
T10 |
12 |
|
T44 |
6 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
216 |
1 |
|
|
T40 |
8 |
|
T10 |
9 |
|
T44 |
12 |
| auto[1] |
204 |
1 |
|
|
T40 |
12 |
|
T10 |
11 |
|
T44 |
8 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
199 |
1 |
|
|
T40 |
11 |
|
T10 |
12 |
|
T44 |
13 |
| auto[1] |
221 |
1 |
|
|
T40 |
9 |
|
T10 |
8 |
|
T44 |
7 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
195 |
1 |
|
|
T40 |
10 |
|
T10 |
11 |
|
T44 |
8 |
| auto[1] |
225 |
1 |
|
|
T40 |
10 |
|
T10 |
9 |
|
T44 |
12 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
210 |
1 |
|
|
T40 |
11 |
|
T10 |
8 |
|
T44 |
10 |
| auto[1] |
210 |
1 |
|
|
T40 |
9 |
|
T10 |
12 |
|
T44 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
220 |
1 |
|
|
T40 |
10 |
|
T10 |
15 |
|
T44 |
8 |
| auto[1] |
200 |
1 |
|
|
T40 |
10 |
|
T10 |
5 |
|
T44 |
12 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
211 |
1 |
|
|
T40 |
9 |
|
T10 |
10 |
|
T44 |
10 |
| auto[1] |
209 |
1 |
|
|
T40 |
11 |
|
T10 |
10 |
|
T44 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
215 |
1 |
|
|
T40 |
8 |
|
T10 |
5 |
|
T44 |
12 |
| auto[1] |
205 |
1 |
|
|
T40 |
12 |
|
T10 |
15 |
|
T44 |
8 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
230 |
1 |
|
|
T40 |
12 |
|
T10 |
14 |
|
T44 |
12 |
| auto[1] |
190 |
1 |
|
|
T40 |
8 |
|
T10 |
6 |
|
T44 |
8 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
204 |
1 |
|
|
T40 |
12 |
|
T10 |
12 |
|
T44 |
14 |
| auto[1] |
216 |
1 |
|
|
T40 |
8 |
|
T10 |
8 |
|
T44 |
6 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
212 |
1 |
|
|
T40 |
11 |
|
T10 |
8 |
|
T44 |
5 |
| auto[1] |
208 |
1 |
|
|
T40 |
9 |
|
T10 |
12 |
|
T44 |
15 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
191 |
1 |
|
|
T40 |
11 |
|
T10 |
4 |
|
T44 |
7 |
| auto[1] |
229 |
1 |
|
|
T40 |
9 |
|
T10 |
16 |
|
T44 |
13 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
210 |
1 |
|
|
T40 |
10 |
|
T10 |
8 |
|
T44 |
14 |
| auto[1] |
210 |
1 |
|
|
T40 |
10 |
|
T10 |
12 |
|
T44 |
6 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
116 |
1 |
|
|
T40 |
5 |
|
T10 |
4 |
|
T44 |
4 |
| auto[0] |
auto[1] |
79 |
1 |
|
|
T40 |
5 |
|
T10 |
7 |
|
T44 |
4 |
| auto[1] |
auto[0] |
104 |
1 |
|
|
T40 |
4 |
|
T10 |
3 |
|
T44 |
5 |
| auto[1] |
auto[1] |
121 |
1 |
|
|
T40 |
6 |
|
T10 |
6 |
|
T44 |
7 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
123 |
1 |
|
|
T40 |
5 |
|
T10 |
4 |
|
T44 |
8 |
| auto[0] |
auto[1] |
87 |
1 |
|
|
T40 |
6 |
|
T10 |
4 |
|
T44 |
2 |
| auto[1] |
auto[0] |
96 |
1 |
|
|
T40 |
3 |
|
T10 |
6 |
|
T44 |
7 |
| auto[1] |
auto[1] |
114 |
1 |
|
|
T40 |
6 |
|
T10 |
6 |
|
T44 |
3 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
104 |
1 |
|
|
T40 |
3 |
|
T10 |
8 |
|
T44 |
4 |
| auto[0] |
auto[1] |
116 |
1 |
|
|
T40 |
7 |
|
T10 |
7 |
|
T44 |
4 |
| auto[1] |
auto[0] |
86 |
1 |
|
|
T40 |
6 |
|
T10 |
2 |
|
T44 |
7 |
| auto[1] |
auto[1] |
114 |
1 |
|
|
T40 |
4 |
|
T10 |
3 |
|
T44 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
116 |
1 |
|
|
T40 |
3 |
|
T10 |
8 |
|
T44 |
5 |
| auto[0] |
auto[1] |
95 |
1 |
|
|
T40 |
6 |
|
T10 |
2 |
|
T44 |
5 |
| auto[1] |
auto[0] |
107 |
1 |
|
|
T40 |
7 |
|
T10 |
7 |
|
T44 |
6 |
| auto[1] |
auto[1] |
102 |
1 |
|
|
T40 |
4 |
|
T10 |
3 |
|
T44 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
121 |
1 |
|
|
T40 |
4 |
|
T10 |
2 |
|
T44 |
9 |
| auto[0] |
auto[1] |
94 |
1 |
|
|
T40 |
4 |
|
T10 |
3 |
|
T44 |
3 |
| auto[1] |
auto[0] |
98 |
1 |
|
|
T40 |
7 |
|
T10 |
1 |
|
T44 |
5 |
| auto[1] |
auto[1] |
107 |
1 |
|
|
T40 |
5 |
|
T10 |
14 |
|
T44 |
3 |