Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1929

1

T18

8

T27

12

T8

19

auto[1]

623

1

T8

5

T10

6

T49

15

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1960

1

T18

6

T27

12

T8

19

auto[1]

592

1

T18

2

T8

5

T10

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1936

1

T18

8

T27

12

T8

15

auto[1]

616

1

T8

9

T10

12

T12

6

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1916

1

T18

6

T27

12

T8

24

auto[1]

636

1

T18

2

T10

16

T12

6

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2289

1

T18

8

T27

12

T8

24

auto[1]

263

1

T31

46

T241

2

T273

1

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2377

1

T18

8

T27

12

T8

15

auto[1]

175

1

T8

9

T79

4

T48

1

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2343

1

T18

6

T27

12

T8

24

auto[1]

209

1

T18

2

T31

10

T48

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2298

1

T18

8

T27

9

T8

15

auto[1]

254

1

T27

3

T8

9

T31

28

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2346

1

T18

6

T27

12

T8

24

auto[1]

206

1

T18

2

T47

1

T48

1

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2018

1

T18

8

T27

9

T8

20

auto[1]

534

1

T27

3

T8

4

T10

9

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	920	1			T10	21		T12	12		T49	15
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	71	1			T31	18		T148	3		T274	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	51	1			T186	5		T104	2		T276	5
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	23	1			T334	1		T336	10		T103	6
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	98	1			T27	3		T8	2		T48	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	37	1			T31	18		T241	2		T273	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	11	1			T274	2		T345	2		T346	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	11	1			T347	5		T348	3		T349	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	53	1			T81	3		T350	2		T275	4
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	22	1			T335	4		T351	6		T103	4
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	28	1			T18	2		T48	1		T186	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	8	1			T328	7		T352	1		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	17	1			T273	1		T353	2		T334	4
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	12	1			T31	10		T340	2		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	25	1			T8	3		T241	3		T273	3
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	29	1			T347	9		T348	6		T354	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	20	1			T355	6		T351	9		T250	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	14	1			T239	4		T351	6		T329	4
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	15	1			T8	2		T48	1		T81	3
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	3	1			T232	2		T356	1		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	4	1			T347	4		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	10	1			T275	1		T267	1		T103	2
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	10	1			T186	1		T274	2		T221	5
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	20	1			T328	20		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T357	2		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T329	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

141

1

T8

3

T49

11

T241

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

78

1

T27

3

T274

4

T353

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

53

1

T113

5

T287

3

T218

14

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

151

1

T247

12

T186

6

T276

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

84

1

T48

1

T81

3

T118

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

59

1

T10

8

T12

6

T278

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

42

1

T49

1

T63

4

T66

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

144

1

T31

18

T48

1

T117

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

47

1

T10

5

T241

3

T185

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

71

1

T8

2

T241

2

T247

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T81

3

T358

2

T359

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

63

1

T10

7

T276

5

T353

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T49

3

T123

1

T37

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

17

1

T276

3

T354

2

T360

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

12

1

T281

2

T326

3

T124

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

136

1

T101

11

T31

10

T118

9

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

73

1

T33

10

T279

2

T274

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

37

1

T273

1

T42

1

T104

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T32

1

T361

3

T353

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

39

1

T18

2

T186

1

T272

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T104

2

T73

1

T350

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

24

1

T66

1

T117

5

T113

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T10

1

T247

2

T287

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T8

2

T12

6

T63

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T117

2

T81

3

T167

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

35

1

T278

2

T362

3

T206

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T66

3

T48

1

T206

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

36

1

T101

1

T31

18

T334

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T118

1

T281

1

T110

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

12

1

T330

2

T128

1

T338

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T363

1

T263

1

T129

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded