Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

962

1

T57

10

T59

10

T23

32

auto[1]

1020

1

T57

10

T59

10

T23

30

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

466

1

T57

5

T59

5

T23

12

from_0to1

471

1

T57

5

T59

5

T23

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1005

1

T57

12

T59

8

T23

37

auto[1]

977

1

T57

8

T59

12

T23

25

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T57

9

T59

12

T23

28

auto[1]

982

1

T57

11

T59

8

T23

34

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T59

1

T375

1

T376

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T57

1

T23

1

T375

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T57

1

T376

1

T377

2

auto[0]

from_1to0

auto[1]

auto[1]

52

1

T59

1

T23

1

T376

2

auto[0]

from_0to1

auto[0]

auto[0]

48

1

T57

1

T23

4

T66

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T59

1

T23

1

T66

1

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T59

2

T23

1

T66

2

auto[0]

from_0to1

auto[1]

auto[1]

40

1

T57

1

T375

1

T377

1

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T57

1

T59

1

T23

1

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T57

1

T23

3

T66

1

auto[1]

from_1to0

auto[1]

auto[0]

51

1

T57

1

T59

1

T23

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T59

1

T23

5

T66

1

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T57

1

T59

1

T377

1

auto[1]

from_0to1

auto[0]

auto[1]

53

1

T23

1

T377

2

T191

2

auto[1]

from_0to1

auto[1]

auto[0]

82

1

T57

1

T59

1

T23

3

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T57

1

T23

1

T66

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

981

1

T57

12

T59

9

T23

25

auto[1]

1001

1

T57

8

T59

11

T23

37

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

501

1

T57

7

T59

6

T23

15

from_0to1

498

1

T57

6

T59

5

T23

16

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

952

1

T57

12

T59

11

T23

30

auto[1]

1030

1

T57

8

T59

9

T23

32

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1016

1

T57

12

T59

11

T23

30

auto[1]

966

1

T57

8

T59

9

T23

32

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T59

1

T23

2

T66

2

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T57

1

T59

1

T23

4

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T57

1

T23

1

T66

2

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T57

1

T23

1

T376

1

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T59

1

T23

1

T375

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T57

1

T59

1

T23

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T57

2

T23

2

T66

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T57

1

T23

2

T66

2

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T57

3

T59

1

T23

4

auto[1]

from_1to0

auto[0]

auto[1]

51

1

T57

1

T23

1

T66

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T59

2

T23

2

T66

1

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T59

1

T376

1

T377

3

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T57

1

T59

1

T23

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T23

1

T53

2

T191

1

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T59

1

T23

4

T66

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T57

1

T59

1

T23

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

995

1

T57

2

T59

11

T23

34

auto[1]

987

1

T57

18

T59

9

T23

28

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

484

1

T57

5

T59

3

T23

14

from_0to1

480

1

T57

4

T59

4

T23

14

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

997

1

T57

11

T59

8

T23

27

auto[1]

985

1

T57

9

T59

12

T23

35

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

956

1

T57

9

T59

10

T23

40

auto[1]

1026

1

T57

11

T59

10

T23

22

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

54

1

T59

1

T23

2

T53

1

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T57

1

T59

2

T375

1

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T23

2

T66

2

T375

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T23

2

T375

2

T376

1

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T59

1

T23

3

T66

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T375

1

T376

1

T191

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T57

1

T23

2

T66

2

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T23

1

T375

1

T53

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T57

1

T23

4

T376

1

auto[1]

from_1to0

auto[0]

auto[1]

76

1

T57

2

T66

2

T375

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T23

2

T66

1

T376

2

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T57

1

T23

2

T375

1

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T23

3

T377

2

T42

2

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T57

1

T23

1

T375

2

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T57

1

T59

2

T23

3

auto[1]

from_0to1

auto[1]

auto[1]

51

1

T57

1

T59

1

T23

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

960

1

T57

11

T59

9

T23

36

auto[1]

1022

1

T57

9

T59

11

T23

26

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

467

1

T57

5

T59

4

T23

19

from_0to1

466

1

T57

5

T59

5

T23

20

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

990

1

T57

11

T59

11

T23

31

auto[1]

992

1

T57

9

T59

9

T23

31

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1001

1

T57

11

T59

10

T23

29

auto[1]

981

1

T57

9

T59

10

T23

33

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T59

1

T23

3

T375

1

auto[0]

from_1to0

auto[0]

auto[1]

45

1

T23

2

T375

1

T376

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T57

1

T59

1

T23

4

auto[0]

from_1to0

auto[1]

auto[1]

49

1

T23

2

T375

1

T53

2

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T57

2

T59

1

T23

2

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T57

1

T23

5

T377

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T57

1

T23

3

T377

3

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T59

1

T23

3

T66

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T57

1

T23

3

T66

2

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T57

1

T59

2

T23

2

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T57

2

T23

2

T66

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T23

1

T375

1

T376

1

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T59

2

T23

2

T42

2

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T66

1

T375

2

T376

1

auto[1]

from_0to1

auto[1]

auto[0]

49

1

T23

2

T375

2

T376

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T57

1

T59

1

T23

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

994

1

T57

3

T59

7

T23

29

auto[1]

988

1

T57

17

T59

13

T23

33

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

447

1

T57

5

T59

6

T23

10

from_0to1

447

1

T57

5

T59

6

T23

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1007

1

T57

11

T59

8

T23

32

auto[1]

975

1

T57

9

T59

12

T23

30

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

950

1

T57

12

T59

8

T23

36

auto[1]

1032

1

T57

8

T59

12

T23

26

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

47

1

T59

1

T23

1

T66

2

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T57

1

T23

1

T66

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T23

3

T66

1

T376

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T66

1

T375

1

T376

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T23

1

T375

1

T377

2

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T59

1

T66

1

T376

1

auto[0]

from_0to1

auto[1]

auto[0]

39

1

T66

1

T375

1

T377

2

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T59

3

T23

3

T66

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T57

2

T23

2

T375

2

auto[1]

from_1to0

auto[0]

auto[1]

52

1

T59

3

T23

1

T377

1

auto[1]

from_1to0

auto[1]

auto[0]

47

1

T57

1

T59

1

T23

1

auto[1]

from_1to0

auto[1]

auto[1]

53

1

T57

1

T59

1

T23

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T57

2

T23

2

T376

1

auto[1]

from_0to1

auto[0]

auto[1]

53

1

T66

1

T375

1

T191

2

auto[1]

from_0to1

auto[1]

auto[0]

48

1

T57

2

T59

1

T23

3

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T57

1

T59

1

T23

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

991

1

T57

6

T59

9

T23

27

auto[1]

991

1

T57

14

T59

11

T23

35

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

469

1

T57

5

T59

5

T23

17

from_0to1

466

1

T57

4

T59

5

T23

17

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1009

1

T57

11

T59

12

T23

29

auto[1]

973

1

T57

9

T59

8

T23

33

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

989

1

T57

11

T59

9

T23

31

auto[1]

993

1

T57

9

T59

11

T23

31

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

54

1

T59

1

T23

2

T66

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T59

1

T23

1

T375

1

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T57

1

T23

2

T375

1

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T23

2

T66

1

T375

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T23

3

T66

1

T375

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T23

2

T375

1

T376

1

auto[0]

from_0to1

auto[1]

auto[0]

50

1

T57

1

T23

2

T375

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T57

1

T59

1

T23

3

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T57

1

T59

3

T23

4

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T57

2

T23

2

T191

1

auto[1]

from_1to0

auto[1]

auto[0]

50

1

T23

2

T375

1

T376

1

auto[1]

from_1to0

auto[1]

auto[1]

49

1

T57

1

T23

2

T375

1

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T57

2

T23

3

T375

1

auto[1]

from_0to1

auto[0]

auto[1]

54

1

T59

4

T23

2

T376

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T23

2

T66

1

T376

1

auto[1]

from_0to1

auto[1]

auto[1]

47

1

T66

2

T191

1

T42

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

959

1

T57

9

T59

11

T23

36

auto[1]

1023

1

T57

11

T59

9

T23

26

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

462

1

T57

4

T59

6

T23

11

from_0to1

469

1

T57

4

T59

5

T23

12

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

991

1

T57

8

T59

10

T23

37

auto[1]

991

1

T57

12

T59

10

T23

25

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

948

1

T57

12

T59

9

T23

35

auto[1]

1034

1

T57

8

T59

11

T23

27

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T23

3

T42

2

T378

2

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T59

1

T23

2

T53

1

auto[0]

from_1to0

auto[1]

auto[0]

57

1

T376

2

T191

2

T42

1

auto[0]

from_1to0

auto[1]

auto[1]

50

1

T57

1

T59

2

T23

1

auto[0]

from_0to1

auto[0]

auto[0]

54

1

T57

1

T59

1

T23

3

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T59

1

T23

1

T377

2

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T59

1

T23

3

T375

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T57

1

T23

2

T377

2

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T23

2

T377

2

T42

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T59

2

T23

1

T66

2

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T57

2

T59

1

T376

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T57

1

T23

2

T375

2

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T23

2

T66

1

T375

1

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T57

1

T59

1

T23

1

auto[1]

from_0to1

auto[1]

auto[0]

45

1

T59

1

T376

1

T53

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T57

1

T66

1

T375

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

988

1

T57

10

T59

10

T23

29

auto[1]

994

1

T57

10

T59

10

T23

33

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

496

1

T57

4

T59

5

T23

16

from_0to1

492

1

T57

4

T59

5

T23

16

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1018

1

T57

11

T59

14

T23

29

auto[1]

964

1

T57

9

T59

6

T23

33

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

944

1

T57

10

T59

8

T23

29

auto[1]

1038

1

T57

10

T59

12

T23

33

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

78

1

T57

2

T59

1

T23

1

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T57

2

T23

3

T66

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T23

2

T375

1

T53

1

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T59

1

T23

1

T66

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T23

1

T375

2

T42

2

auto[0]

from_0to1

auto[0]

auto[1]

76

1

T57

1

T59

3

T23

1

auto[0]

from_0to1

auto[1]

auto[0]

52

1

T23

2

T66

1

T377

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T57

1

T23

4

T191

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T59

1

T23

3

T377

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T23

2

T376

1

T42

2

auto[1]

from_1to0

auto[1]

auto[0]

53

1

T59

2

T23

3

T42

2

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T23

1

T66

2

T375

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T59

2

T23

1

T377

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T57

1

T23

2

T66

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T57

1

T23

2

T375

1

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T23

3

T66

1

T191

1