Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	150021	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

117049

1

T4

12

T1

7

T5

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	138526	1			T4	2		T1	11		T5	3
values[0x0]	63846	1			T4	32		T1	4		T5	1
values[0x1]	64698	1			T4	28		T1	3		T5	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	121474	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145596

1

T4

16

T1

10

T5

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	885	1			T4	1		T14	5		T15	1
valid_sources[0x01]	838	1			T15	1		T18	1		T57	1
valid_sources[0x02]	825	1			T18	8		T22	1		T27	3
valid_sources[0x03]	1066	1			T18	6		T26	1		T27	3
valid_sources[0x04]	1120	1			T3	5		T18	1		T59	3
valid_sources[0x05]	749	1			T4	2		T17	1		T18	4
valid_sources[0x06]	941	1			T4	1		T18	4		T57	1
valid_sources[0x07]	923	1			T18	5		T26	1		T6	2
valid_sources[0x08]	1777	1			T4	1		T18	2		T57	1
valid_sources[0x09]	882	1			T4	1		T17	1		T18	3
valid_sources[0x0a]	1005	1			T18	5		T57	1		T26	1
valid_sources[0x0b]	1123	1			T17	1		T57	1		T59	1
valid_sources[0x0c]	1004	1			T18	3		T22	1		T26	4
valid_sources[0x0d]	783	1			T3	5		T18	1		T59	1
valid_sources[0x0e]	993	1			T17	1		T18	4		T22	2
valid_sources[0x0f]	724	1			T17	2		T18	1		T57	3
valid_sources[0x10]	2268	1			T18	5		T59	1		T27	10
valid_sources[0x11]	1402	1			T1	2		T17	1		T18	9
valid_sources[0x12]	889	1			T3	20		T18	1		T59	1
valid_sources[0x13]	998	1			T17	2		T18	1		T57	1
valid_sources[0x14]	847	1			T18	3		T26	1		T27	3
valid_sources[0x15]	998	1			T4	1		T18	4		T26	2
valid_sources[0x16]	677	1			T18	1		T56	1		T57	1
valid_sources[0x17]	928	1			T18	6		T26	1		T23	1
valid_sources[0x18]	830	1			T17	1		T18	3		T26	3
valid_sources[0x19]	940	1			T18	4		T22	1		T26	6
valid_sources[0x1a]	797	1			T18	5		T57	1		T26	2
valid_sources[0x1b]	983	1			T57	1		T27	2		T23	2
valid_sources[0x1c]	780	1			T17	1		T18	2		T56	1
valid_sources[0x1d]	1181	1			T18	3		T59	1		T26	2
valid_sources[0x1e]	840	1			T18	3		T57	1		T26	2
valid_sources[0x1f]	855	1			T18	3		T27	3		T23	3
valid_sources[0x20]	1297	1			T18	1		T26	1		T23	6
valid_sources[0x21]	1014	1			T18	8		T59	1		T26	2
valid_sources[0x22]	827	1			T17	1		T18	5		T59	1
valid_sources[0x23]	947	1			T18	2		T26	1		T27	4
valid_sources[0x24]	859	1			T15	1		T18	11		T57	1
valid_sources[0x25]	910	1			T26	1		T27	1		T23	6
valid_sources[0x26]	800	1			T18	7		T6	1		T27	4
valid_sources[0x27]	1204	1			T18	2		T22	1		T26	3
valid_sources[0x28]	801	1			T22	1		T59	1		T26	2
valid_sources[0x29]	869	1			T18	7		T57	2		T26	4
valid_sources[0x2a]	948	1			T18	5		T22	1		T59	3
valid_sources[0x2b]	734	1			T18	11		T28	2		T22	1
valid_sources[0x2c]	919	1			T18	2		T57	1		T26	2
valid_sources[0x2d]	1275	1			T18	3		T56	1		T27	1
valid_sources[0x2e]	1717	1			T18	2		T22	1		T57	2
valid_sources[0x2f]	1109	1			T18	8		T56	1		T26	3
valid_sources[0x30]	803	1			T4	2		T17	1		T18	6
valid_sources[0x31]	1052	1			T26	2		T27	6		T23	7
valid_sources[0x32]	844	1			T56	1		T26	1		T23	5
valid_sources[0x33]	920	1			T18	1		T57	1		T27	1
valid_sources[0x34]	957	1			T13	4		T18	3		T22	2
valid_sources[0x35]	933	1			T2	9		T18	2		T27	2
valid_sources[0x36]	1047	1			T18	4		T57	2		T59	1
valid_sources[0x37]	755	1			T18	2		T57	1		T59	1
valid_sources[0x38]	845	1			T18	5		T26	1		T6	1
valid_sources[0x39]	809	1			T18	3		T22	1		T57	1
valid_sources[0x3a]	825	1			T18	4		T57	1		T59	2
valid_sources[0x3b]	955	1			T18	4		T56	2		T59	1
valid_sources[0x3c]	1068	1			T17	1		T18	1		T57	1
valid_sources[0x3d]	1080	1			T18	4		T26	3		T27	3
valid_sources[0x3e]	739	1			T18	3		T22	1		T57	1
valid_sources[0x3f]	917	1			T17	2		T18	5		T27	1
valid_sources[0x40]	872	1			T15	1		T18	4		T22	1
valid_sources[0x41]	1593	1			T18	8		T59	2		T26	1
valid_sources[0x42]	740	1			T3	8		T26	1		T27	8
valid_sources[0x43]	869	1			T18	10		T26	1		T27	2
valid_sources[0x44]	874	1			T4	1		T17	1		T18	5
valid_sources[0x45]	1124	1			T18	6		T57	1		T59	2
valid_sources[0x46]	774	1			T17	1		T18	4		T57	1
valid_sources[0x47]	2055	1			T4	1		T18	8		T57	1
valid_sources[0x48]	795	1			T15	1		T17	1		T18	2
valid_sources[0x49]	958	1			T4	1		T1	1		T18	2
valid_sources[0x4a]	1166	1			T18	7		T57	1		T26	3
valid_sources[0x4b]	730	1			T18	7		T26	3		T27	3
valid_sources[0x4c]	1184	1			T18	7		T27	7		T23	9
valid_sources[0x4d]	850	1			T17	1		T3	20		T18	1
valid_sources[0x4e]	915	1			T18	3		T59	1		T26	2
valid_sources[0x4f]	917	1			T57	1		T26	2		T27	3
valid_sources[0x50]	851	1			T26	1		T27	2		T23	1
valid_sources[0x51]	999	1			T4	2		T3	20		T18	1
valid_sources[0x52]	796	1			T18	3		T59	1		T26	6
valid_sources[0x53]	825	1			T18	2		T57	1		T26	1
valid_sources[0x54]	1560	1			T17	1		T3	11		T18	1
valid_sources[0x55]	807	1			T18	7		T57	1		T26	1
valid_sources[0x56]	840	1			T18	10		T22	2		T26	1
valid_sources[0x57]	930	1			T59	1		T26	2		T27	2
valid_sources[0x58]	1548	1			T18	6		T57	1		T26	4
valid_sources[0x59]	1110	1			T18	10		T26	1		T6	1
valid_sources[0x5a]	866	1			T18	3		T26	3		T23	5
valid_sources[0x5b]	887	1			T18	5		T56	3		T23	7
valid_sources[0x5c]	848	1			T18	4		T26	2		T6	1
valid_sources[0x5d]	979	1			T26	5		T6	1		T23	6
valid_sources[0x5e]	1017	1			T18	3		T57	2		T59	2
valid_sources[0x5f]	838	1			T18	4		T27	5		T23	5
valid_sources[0x60]	910	1			T17	1		T18	8		T26	1
valid_sources[0x61]	731	1			T15	1		T22	2		T27	5
valid_sources[0x62]	1069	1			T4	2		T18	1		T59	1
valid_sources[0x63]	1041	1			T4	1		T27	2		T10	2
valid_sources[0x64]	1253	1			T4	6		T1	2		T18	3
valid_sources[0x65]	1323	1			T4	2		T18	1		T26	1
valid_sources[0x66]	994	1			T17	3		T18	6		T57	1
valid_sources[0x67]	1083	1			T18	7		T56	2		T26	1
valid_sources[0x68]	1593	1			T26	4		T27	4		T23	3
valid_sources[0x69]	984	1			T4	1		T18	2		T57	1
valid_sources[0x6a]	734	1			T17	2		T18	4		T22	1
valid_sources[0x6b]	981	1			T18	4		T26	3		T27	3
valid_sources[0x6c]	937	1			T59	1		T26	1		T27	8
valid_sources[0x6d]	1468	1			T18	2		T57	2		T26	1
valid_sources[0x6e]	1089	1			T15	1		T18	2		T56	1
valid_sources[0x6f]	866	1			T18	6		T59	1		T26	1
valid_sources[0x70]	1031	1			T17	2		T3	1		T18	6
valid_sources[0x71]	1165	1			T18	3		T57	1		T59	1
valid_sources[0x72]	1168	1			T4	2		T18	6		T57	1
valid_sources[0x73]	859	1			T18	8		T26	1		T6	1
valid_sources[0x74]	899	1			T4	2		T59	1		T26	3
valid_sources[0x75]	918	1			T15	1		T17	1		T18	3
valid_sources[0x76]	1928	1			T5	1		T18	4		T26	4
valid_sources[0x77]	2469	1			T4	1		T3	20		T18	5
valid_sources[0x78]	1593	1			T3	69		T18	3		T57	1
valid_sources[0x79]	870	1			T17	1		T18	2		T26	3
valid_sources[0x7a]	1046	1			T18	3		T57	1		T26	3
valid_sources[0x7b]	1633	1			T5	1		T3	7		T18	6
valid_sources[0x7c]	1142	1			T4	1		T3	235		T18	3
valid_sources[0x7d]	777	1			T13	1		T18	1		T26	2
valid_sources[0x7e]	958	1			T18	4		T26	5		T27	8
valid_sources[0x7f]	1450	1			T18	8		T57	1		T59	5
valid_sources[0x80]	855	1			T18	3		T57	1		T59	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63426

1

T1

4

T5

2

T14

2

values[0x0]

all_enables

biggest_size

31333

1

T4

8

T1

2

T13

2

values[0x1]

all_enables

biggest_size

22290

1

T4

4

T1

1

T5

1