Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	90.48		100.00	100.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	90.48		100.00	100.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T15
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T15
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T23,T25,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T23,T25,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T23,T25,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T23,T25,T39
1	0	Covered	T4,T15,T17
1	1	Covered	T23,T25,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T23,T25,T39
0	1	Covered	T51,T53
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T25,T39
0	1	Covered	T23,T25,T39
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T23,T25,T39
1	-	Covered	T23,T25,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T23,T25,T39
DetectSt	168	Covered	T23,T25,T39
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T23,T25,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T23,T25,T39
DebounceSt->IdleSt	163	Covered	T51,T112,T113
DetectSt->IdleSt	186	Covered	T51,T53
DetectSt->StableSt	191	Covered	T23,T25,T39
IdleSt->DebounceSt	148	Covered	T23,T25,T39
StableSt->IdleSt	206	Covered	T23,T25,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T23,T25,T39
0	1	Covered	T23,T25,T39
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T23,T25,T39
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T23,T25,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T23,T25,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T51,T112,T113
DebounceSt	-	0	0	-	-	-	-	Covered	T23,T25,T39
DetectSt	-	-	-	-	1	-	-	Covered	T51,T53
DetectSt	-	-	-	-	0	1	-	Covered	T23,T25,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T25,T39
StableSt	-	-	-	-	-	-	0	Covered	T23,T25,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	251	0	0
CntIncr_A	6481552	282576	0	0
CntNoWrap_A	6481552	5865483	0	0
DetectStDropOut_A	6481552	2	0	0
DetectedOut_A	6481552	811	0	0
DetectedPulseOut_A	6481552	116	0	0
DisabledIdleSt_A	6481552	5577411	0	0
DisabledNoDetection_A	6481552	5579648	0	0
EnterDebounceSt_A	6481552	135	0	0
EnterDetectSt_A	6481552	118	0	0
EnterStableSt_A	6481552	116	0	0
PulseIsPulse_A	6481552	116	0	0
StayInStableSt	6481552	695	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6481552	6459	0	0
gen_low_level_sva.LowLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	115	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	251	0	0
T8	12632	0	0	0
T9	953	0	0	0
T10	30263	0	0	0
T23	9472	4	0	0
T25	0	2	0	0
T39	0	4	0	0
T50	0	4	0	0
T51	0	5	0	0
T52	0	2	0	0
T53	0	4	0	0
T54	0	6	0	0
T55	0	2	0	0
T64	495	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T114	0	4	0	0
T115	432	0	0	0
T116	450	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	282576	0	0
T8	12632	0	0	0
T9	953	0	0	0
T10	30263	0	0	0
T23	9472	99	0	0
T25	0	30	0	0
T39	0	112	0	0
T50	0	152	0	0
T51	0	158	0	0
T52	0	53903	0	0
T53	0	109	0	0
T54	0	134	0	0
T55	0	100	0	0
T64	495	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T114	0	133	0	0
T115	432	0	0	0
T116	450	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5865483	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	2	0	0
T24	492	0	0	0
T33	32904	0	0	0
T41	1149	0	0	0
T51	661	1	0	0
T53	0	1	0	0
T65	551	0	0	0
T68	498	0	0	0
T101	28438	0	0	0
T131	402	0	0	0
T132	422	0	0	0
T133	442	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	811	0	0
T8	12632	0	0	0
T9	953	0	0	0
T10	30263	0	0	0
T23	9472	18	0	0
T25	0	5	0	0
T39	0	12	0	0
T50	0	16	0	0
T51	0	4	0	0
T52	0	11	0	0
T53	0	4	0	0
T54	0	33	0	0
T55	0	12	0	0
T64	495	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T114	0	6	0	0
T115	432	0	0	0
T116	450	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	116	0	0
T8	12632	0	0	0
T9	953	0	0	0
T10	30263	0	0	0
T23	9472	2	0	0
T25	0	1	0	0
T39	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	0	1	0	0
T64	495	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T114	0	2	0	0
T115	432	0	0	0
T116	450	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5577411	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5579648	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	135	0	0
T8	12632	0	0	0
T9	953	0	0	0
T10	30263	0	0	0
T23	9472	2	0	0
T25	0	1	0	0
T39	0	2	0	0
T50	0	2	0	0
T51	0	3	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	3	0	0
T55	0	1	0	0
T64	495	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T114	0	2	0	0
T115	432	0	0	0
T116	450	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	118	0	0
T8	12632	0	0	0
T9	953	0	0	0
T10	30263	0	0	0
T23	9472	2	0	0
T25	0	1	0	0
T39	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	3	0	0
T55	0	1	0	0
T64	495	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T114	0	2	0	0
T115	432	0	0	0
T116	450	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	116	0	0
T8	12632	0	0	0
T9	953	0	0	0
T10	30263	0	0	0
T23	9472	2	0	0
T25	0	1	0	0
T39	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	0	1	0	0
T64	495	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T114	0	2	0	0
T115	432	0	0	0
T116	450	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	116	0	0
T8	12632	0	0	0
T9	953	0	0	0
T10	30263	0	0	0
T23	9472	2	0	0
T25	0	1	0	0
T39	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	0	1	0	0
T64	495	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T114	0	2	0	0
T115	432	0	0	0
T116	450	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	695	0	0
T8	12632	0	0	0
T9	953	0	0	0
T10	30263	0	0	0
T23	9472	16	0	0
T25	0	4	0	0
T39	0	10	0	0
T50	0	14	0	0
T51	0	3	0	0
T52	0	10	0	0
T53	0	3	0	0
T54	0	30	0	0
T55	0	11	0	0
T64	495	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T114	0	4	0	0
T115	432	0	0	0
T116	450	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	6459	0	0
T1	189379	0	0	0
T2	551	0	0	0
T3	298636	22	0	0
T4	525	4	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	3	0	0
T16	4402	0	0	0
T17	521	4	0	0
T18	0	26	0	0
T22	0	10	0	0
T26	0	23	0	0
T56	0	2	0	0
T57	0	6	0	0
T59	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	115	0	0
T8	12632	0	0	0
T9	953	0	0	0
T10	30263	0	0	0
T23	9472	2	0	0
T25	0	1	0	0
T39	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	0	1	0	0
T64	495	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T114	0	2	0	0
T115	432	0	0	0
T116	450	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T15
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T15
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T3,T6,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T9
1	0	Covered	T4,T15,T17
1	1	Covered	T3,T6,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T11,T62
0	1	Covered	T9,T83,T111
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T11,T62
0	1	Unreachable
1	0	Covered	T6,T11,T62

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T9
DetectSt	168	Covered	T6,T9,T11
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T6,T11,T62

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T9,T11
DebounceSt->IdleSt	163	Covered	T3,T6,T9
DetectSt->IdleSt	186	Covered	T9,T83,T111
DetectSt->StableSt	191	Covered	T6,T11,T62
IdleSt->DebounceSt	148	Covered	T3,T6,T9
StableSt->IdleSt	206	Covered	T6,T11,T62

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T9
0	1	Covered	T3,T6,T9
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T11
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T102
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T6,T9
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T9
DetectSt	-	-	-	-	1	-	-	Covered	T9,T83,T111
DetectSt	-	-	-	-	0	1	-	Covered	T6,T11,T62
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T11,T62
StableSt	-	-	-	-	-	-	0	Covered	T6,T11,T62
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	227	0	0
CntIncr_A	6481552	94283	0	0
CntNoWrap_A	6481552	5865507	0	0
DetectStDropOut_A	6481552	30	0	0
DetectedOut_A	6481552	100236	0	0
DetectedPulseOut_A	6481552	42	0	0
DisabledIdleSt_A	6481552	4416669	0	0
DisabledNoDetection_A	6481552	4418947	0	0
EnterDebounceSt_A	6481552	155	0	0
EnterDetectSt_A	6481552	72	0	0
EnterStableSt_A	6481552	42	0	0
PulseIsPulse_A	6481552	42	0	0
StayInStableSt	6481552	100194	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6481552	6459	0	0
gen_low_level_sva.LowLevelEvent_A	6481552	5868014	0	0
gen_sticky_sva.StableStDropOut_A	6481552	695261	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	227	0	0
T3	298636	5	0	0
T6	3381	7	0	0
T9	0	7	0	0
T11	0	2	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	2	0	0
T66	0	2	0	0
T67	0	2	0	0
T82	0	4	0	0
T83	0	5	0	0
T84	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	94283	0	0
T3	298636	210	0	0
T6	3381	526	0	0
T9	0	212	0	0
T11	0	42	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	98	0	0
T66	0	45	0	0
T67	0	60	0	0
T82	0	172	0	0
T83	0	42	0	0
T84	0	35	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5865507	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292107	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	30	0	0
T9	953	3	0	0
T10	30263	0	0	0
T11	1939	0	0	0
T12	23039	0	0	0
T25	661	0	0	0
T45	518	0	0	0
T49	27298	0	0	0
T64	495	0	0	0
T83	0	1	0	0
T98	402	0	0	0
T106	0	1	0	0
T111	0	5	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0
T142	0	8	0	0
T143	0	1	0	0
T144	404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	100236	0	0
T6	3381	366	0	0
T7	767	0	0	0
T11	0	258	0	0
T23	9472	0	0	0
T27	12374	0	0	0
T60	424	0	0	0
T62	0	676	0	0
T66	0	125	0	0
T67	0	162	0	0
T75	530	0	0	0
T76	526	0	0	0
T82	0	740	0	0
T83	0	1	0	0
T84	0	174	0	0
T97	411	0	0	0
T105	0	602	0	0
T111	0	1	0	0
T115	432	0	0	0
T116	450	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	42	0	0
T6	3381	1	0	0
T7	767	0	0	0
T11	0	1	0	0
T23	9472	0	0	0
T27	12374	0	0	0
T60	424	0	0	0
T62	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T75	530	0	0	0
T76	526	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T97	411	0	0	0
T105	0	1	0	0
T111	0	1	0	0
T115	432	0	0	0
T116	450	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	4416669	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	2416	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	4418947	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	2431	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	155	0	0
T3	298636	5	0	0
T6	3381	6	0	0
T9	0	4	0	0
T11	0	1	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T82	0	2	0	0
T83	0	3	0	0
T84	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	72	0	0
T6	3381	1	0	0
T7	767	0	0	0
T9	0	3	0	0
T11	0	1	0	0
T23	9472	0	0	0
T27	12374	0	0	0
T60	424	0	0	0
T62	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T75	530	0	0	0
T76	526	0	0	0
T82	0	2	0	0
T83	0	2	0	0
T84	0	1	0	0
T97	411	0	0	0
T105	0	1	0	0
T115	432	0	0	0
T116	450	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	42	0	0
T6	3381	1	0	0
T7	767	0	0	0
T11	0	1	0	0
T23	9472	0	0	0
T27	12374	0	0	0
T60	424	0	0	0
T62	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T75	530	0	0	0
T76	526	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T97	411	0	0	0
T105	0	1	0	0
T111	0	1	0	0
T115	432	0	0	0
T116	450	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	42	0	0
T6	3381	1	0	0
T7	767	0	0	0
T11	0	1	0	0
T23	9472	0	0	0
T27	12374	0	0	0
T60	424	0	0	0
T62	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T75	530	0	0	0
T76	526	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T97	411	0	0	0
T105	0	1	0	0
T111	0	1	0	0
T115	432	0	0	0
T116	450	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	100194	0	0
T6	3381	365	0	0
T7	767	0	0	0
T11	0	257	0	0
T23	9472	0	0	0
T27	12374	0	0	0
T44	0	12	0	0
T60	424	0	0	0
T62	0	675	0	0
T66	0	124	0	0
T67	0	161	0	0
T75	530	0	0	0
T76	526	0	0	0
T82	0	738	0	0
T84	0	173	0	0
T97	411	0	0	0
T105	0	601	0	0
T110	0	2	0	0
T115	432	0	0	0
T116	450	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	6459	0	0
T1	189379	0	0	0
T2	551	0	0	0
T3	298636	22	0	0
T4	525	4	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	3	0	0
T16	4402	0	0	0
T17	521	4	0	0
T18	0	26	0	0
T22	0	10	0	0
T26	0	23	0	0
T56	0	2	0	0
T57	0	6	0	0
T59	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	695261	0	0
T6	3381	110	0	0
T7	767	0	0	0
T11	0	453	0	0
T23	9472	0	0	0
T27	12374	0	0	0
T60	424	0	0	0
T62	0	105	0	0
T66	0	51656	0	0
T67	0	254	0	0
T75	530	0	0	0
T76	526	0	0	0
T82	0	388	0	0
T83	0	125	0	0
T84	0	124	0	0
T97	411	0	0	0
T105	0	68	0	0
T111	0	85	0	0
T115	432	0	0	0
T116	450	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T3,T6,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T9
1	0	Covered	T4,T1,T2
1	1	Covered	T3,T6,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T9
0	1	Covered	T105,T109,T110
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T9
0	1	Unreachable
1	0	Covered	T3,T6,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T9
DetectSt	168	Covered	T3,T6,T9
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T3,T6,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T9
DebounceSt->IdleSt	163	Covered	T11,T66,T82
DetectSt->IdleSt	186	Covered	T105,T109,T110
DetectSt->StableSt	191	Covered	T3,T6,T9
IdleSt->DebounceSt	148	Covered	T3,T6,T9
StableSt->IdleSt	206	Covered	T3,T6,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T9
0	1	Covered	T3,T6,T9
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T9
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T102
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T66,T82
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T9
DetectSt	-	-	-	-	1	-	-	Covered	T105,T109,T110
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T9
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	171	0	0
CntIncr_A	6481552	209645	0	0
CntNoWrap_A	6481552	5865563	0	0
DetectStDropOut_A	6481552	11	0	0
DetectedOut_A	6481552	591018	0	0
DetectedPulseOut_A	6481552	52	0	0
DisabledIdleSt_A	6481552	4416669	0	0
DisabledNoDetection_A	6481552	4418947	0	0
EnterDebounceSt_A	6481552	108	0	0
EnterDetectSt_A	6481552	63	0	0
EnterStableSt_A	6481552	52	0	0
PulseIsPulse_A	6481552	52	0	0
StayInStableSt	6481552	590966	0	0
gen_high_level_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_sticky_sva.StableStDropOut_A	6481552	461198	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	171	0	0
T3	298636	2	0	0
T6	3381	4	0	0
T9	0	2	0	0
T11	0	4	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	2	0	0
T66	0	2	0	0
T67	0	2	0	0
T82	0	6	0	0
T83	0	2	0	0
T84	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	209645	0	0
T3	298636	56570	0	0
T6	3381	87	0	0
T9	0	48	0	0
T11	0	184	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	46	0	0
T66	0	51784	0	0
T67	0	91	0	0
T82	0	468	0	0
T83	0	61	0	0
T84	0	44	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5865563	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292110	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	11	0	0
T44	17909	0	0	0
T72	494	0	0	0
T104	15917	0	0	0
T105	63210	1	0	0
T106	1429	0	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	1428	0	0	0
T138	0	1	0	0
T141	0	2	0	0
T143	0	1	0	0
T145	0	3	0	0
T146	0	1	0	0
T147	422	0	0	0
T148	16228	0	0	0
T149	436	0	0	0
T150	607	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	591018	0	0
T3	298636	232847	0	0
T6	3381	417	0	0
T9	0	191	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T44	0	43	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	202	0	0
T67	0	319	0	0
T83	0	283	0	0
T84	0	194	0	0
T105	0	125	0	0
T111	0	487	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	52	0	0
T3	298636	1	0	0
T6	3381	2	0	0
T9	0	1	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T44	0	1	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	1	0	0
T67	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0
T105	0	1	0	0
T111	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	4416669	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	2416	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	4418947	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	2431	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	108	0	0
T3	298636	1	0	0
T6	3381	2	0	0
T9	0	1	0	0
T11	0	4	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0
T82	0	6	0	0
T83	0	1	0	0
T84	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	63	0	0
T3	298636	1	0	0
T6	3381	2	0	0
T9	0	1	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T44	0	1	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	1	0	0
T67	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0
T105	0	2	0	0
T111	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	52	0	0
T3	298636	1	0	0
T6	3381	2	0	0
T9	0	1	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T44	0	1	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	1	0	0
T67	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0
T105	0	1	0	0
T111	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	52	0	0
T3	298636	1	0	0
T6	3381	2	0	0
T9	0	1	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T44	0	1	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	1	0	0
T67	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0
T105	0	1	0	0
T111	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	590966	0	0
T3	298636	232846	0	0
T6	3381	415	0	0
T9	0	190	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T44	0	42	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	201	0	0
T67	0	318	0	0
T83	0	282	0	0
T84	0	192	0	0
T105	0	124	0	0
T111	0	484	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	461198	0	0
T3	298636	261	0	0
T6	3381	1109	0	0
T9	0	265	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T44	0	31	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	631	0	0
T67	0	57	0	0
T83	0	61	0	0
T84	0	181	0	0
T105	0	271	0	0
T111	0	266	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T3,T6,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T9
1	0	Covered	T4,T1,T2
1	1	Covered	T3,T6,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T11
0	1	Covered	T83,T105,T106
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T11
0	1	Unreachable
1	0	Covered	T3,T6,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T9
DetectSt	168	Covered	T3,T6,T11
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T3,T6,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T11
DebounceSt->IdleSt	163	Covered	T6,T9,T105
DetectSt->IdleSt	186	Covered	T83,T105,T106
DetectSt->StableSt	191	Covered	T3,T6,T11
IdleSt->DebounceSt	148	Covered	T3,T6,T9
StableSt->IdleSt	206	Covered	T3,T6,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T9
0	1	Covered	T3,T6,T9
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T11
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T102
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T9,T105
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T9
DetectSt	-	-	-	-	1	-	-	Covered	T83,T105,T106
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	199	0	0
CntIncr_A	6481552	321482	0	0
CntNoWrap_A	6481552	5865535	0	0
DetectStDropOut_A	6481552	20	0	0
DetectedOut_A	6481552	150861	0	0
DetectedPulseOut_A	6481552	51	0	0
DisabledIdleSt_A	6481552	4416669	0	0
DisabledNoDetection_A	6481552	4418947	0	0
EnterDebounceSt_A	6481552	128	0	0
EnterDetectSt_A	6481552	71	0	0
EnterStableSt_A	6481552	51	0	0
PulseIsPulse_A	6481552	51	0	0
StayInStableSt	6481552	150810	0	0
gen_high_event_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_high_level_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_sticky_sva.StableStDropOut_A	6481552	917267	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	199	0	0
T3	298636	2	0	0
T6	3381	7	0	0
T9	0	4	0	0
T11	0	2	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	2	0	0
T66	0	2	0	0
T67	0	2	0	0
T82	0	4	0	0
T83	0	6	0	0
T84	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	321482	0	0
T3	298636	36	0	0
T6	3381	149	0	0
T9	0	288	0	0
T11	0	68	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	56	0	0
T66	0	66	0	0
T67	0	100	0	0
T82	0	140	0	0
T83	0	120	0	0
T84	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5865535	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292110	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	20	0	0
T36	1126	0	0	0
T42	16126	0	0	0
T71	4937	0	0	0
T83	1254	2	0	0
T84	13652	0	0	0
T105	0	1	0	0
T106	0	1	0	0
T140	0	3	0	0
T141	0	2	0	0
T151	0	1	0	0
T152	0	3	0	0
T153	0	1	0	0
T154	0	2	0	0
T155	0	1	0	0
T156	406	0	0	0
T157	1081	0	0	0
T158	403	0	0	0
T159	13775	0	0	0
T160	501	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	150861	0	0
T3	298636	179	0	0
T6	3381	508	0	0
T11	0	465	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	397	0	0
T66	0	139	0	0
T67	0	306	0	0
T82	0	603	0	0
T83	0	1	0	0
T84	0	122	0	0
T105	0	90	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	51	0	0
T3	298636	1	0	0
T6	3381	1	0	0
T11	0	1	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	2	0	0
T105	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	4416669	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	2416	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	4418947	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	2431	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	128	0	0
T3	298636	1	0	0
T6	3381	6	0	0
T9	0	4	0	0
T11	0	1	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T82	0	2	0	0
T83	0	3	0	0
T84	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	71	0	0
T3	298636	1	0	0
T6	3381	1	0	0
T11	0	1	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T82	0	2	0	0
T83	0	3	0	0
T84	0	2	0	0
T105	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	51	0	0
T3	298636	1	0	0
T6	3381	1	0	0
T11	0	1	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	2	0	0
T105	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	51	0	0
T3	298636	1	0	0
T6	3381	1	0	0
T11	0	1	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	2	0	0
T105	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	150810	0	0
T3	298636	178	0	0
T6	3381	507	0	0
T11	0	464	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T44	0	18	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	396	0	0
T66	0	138	0	0
T67	0	305	0	0
T82	0	601	0	0
T84	0	120	0	0
T105	0	89	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	917267	0	0
T3	298636	289474	0	0
T6	3381	497	0	0
T11	0	225	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T62	0	440	0	0
T66	0	51636	0	0
T67	0	76	0	0
T82	0	582	0	0
T83	0	118	0	0
T84	0	270	0	0
T105	0	330	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T39,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T39,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T39,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T39,T41
1	0	Covered	T4,T1,T5
1	1	Covered	T1,T39,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T39,T41
0	1	Not Covered
1	0	Covered	T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T39,T41
0	1	Covered	T1,T39,T41
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T39,T41
1	-	Covered	T1,T39,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T39,T41
DetectSt	168	Covered	T1,T39,T41
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T39,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T39,T41
DebounceSt->IdleSt	163	Covered	T161,T162,T102
DetectSt->IdleSt	186	Covered	T61
DetectSt->StableSt	191	Covered	T1,T39,T41
IdleSt->DebounceSt	148	Covered	T1,T39,T41
StableSt->IdleSt	206	Covered	T1,T39,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T39,T41
0	1	Covered	T1,T39,T41
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T39,T41
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T39,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T39,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T161,T162
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T39,T41
DetectSt	-	-	-	-	1	-	-	Covered	T61
DetectSt	-	-	-	-	0	1	-	Covered	T1,T39,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T39,T41
StableSt	-	-	-	-	-	-	0	Covered	T1,T39,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	85	0	0
CntIncr_A	6481552	73891	0	0
CntNoWrap_A	6481552	5865649	0	0
DetectStDropOut_A	6481552	0	0	0
DetectedOut_A	6481552	27796	0	0
DetectedPulseOut_A	6481552	40	0	0
DisabledIdleSt_A	6481552	5403527	0	0
DisabledNoDetection_A	6481552	5405756	0	0
EnterDebounceSt_A	6481552	44	0	0
EnterDetectSt_A	6481552	41	0	0
EnterStableSt_A	6481552	40	0	0
PulseIsPulse_A	6481552	40	0	0
StayInStableSt	6481552	27739	0	0
gen_high_level_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	85	0	0
T1	189379	2	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T38	0	4	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	4	0	0
T44	0	8	0	0
T145	0	2	0	0
T161	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	73891	0	0
T1	189379	40506	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	31059	0	0
T35	0	90	0	0
T38	0	120	0	0
T39	0	62	0	0
T41	0	85	0	0
T42	0	136	0	0
T44	0	212	0	0
T145	0	30	0	0
T161	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5865649	0	0
T1	189379	188976	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	27796	0	0
T1	189379	42	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	24712	0	0
T35	0	42	0	0
T38	0	82	0	0
T39	0	137	0	0
T41	0	42	0	0
T42	0	178	0	0
T44	0	176	0	0
T145	0	45	0	0
T161	0	72	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	40	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	4	0	0
T145	0	1	0	0
T161	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5403527	0	0
T1	189379	3	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5405756	0	0
T1	189379	3	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	44	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	4	0	0
T145	0	1	0	0
T161	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	41	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	4	0	0
T145	0	1	0	0
T161	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	40	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	4	0	0
T145	0	1	0	0
T161	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	40	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	4	0	0
T145	0	1	0	0
T161	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	27739	0	0
T1	189379	41	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	24711	0	0
T35	0	41	0	0
T38	0	79	0	0
T39	0	136	0	0
T41	0	41	0	0
T42	0	174	0	0
T44	0	171	0	0
T145	0	44	0	0
T161	0	70	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	23	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	3	0	0
T145	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T35,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T35,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T35,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T35,T42
1	0	Covered	T4,T2,T17
1	1	Covered	T1,T35,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T35,T42
0	1	Covered	T165,T166,T154
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T35,T42
0	1	Covered	T1,T35,T42
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T35,T42
1	-	Covered	T1,T35,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T35,T42
DetectSt	168	Covered	T1,T35,T42
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T35,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T35,T42
DebounceSt->IdleSt	163	Covered	T164,T167,T166
DetectSt->IdleSt	186	Covered	T165,T166,T154
DetectSt->StableSt	191	Covered	T1,T35,T42
IdleSt->DebounceSt	148	Covered	T1,T35,T42
StableSt->IdleSt	206	Covered	T1,T35,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T35,T42
0	1	Covered	T1,T35,T42
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T35,T42
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T35,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T35,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T164,T167,T166
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T35,T42
DetectSt	-	-	-	-	1	-	-	Covered	T165,T166,T154
DetectSt	-	-	-	-	0	1	-	Covered	T1,T35,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T35,T42
StableSt	-	-	-	-	-	-	0	Covered	T1,T35,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	130	0	0
CntIncr_A	6481552	133458	0	0
CntNoWrap_A	6481552	5865604	0	0
DetectStDropOut_A	6481552	3	0	0
DetectedOut_A	6481552	71398	0	0
DetectedPulseOut_A	6481552	58	0	0
DisabledIdleSt_A	6481552	5553864	0	0
DisabledNoDetection_A	6481552	5556091	0	0
EnterDebounceSt_A	6481552	70	0	0
EnterDetectSt_A	6481552	61	0	0
EnterStableSt_A	6481552	58	0	0
PulseIsPulse_A	6481552	58	0	0
StayInStableSt	6481552	71316	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6481552	2311	0	0
gen_low_level_sva.LowLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	130	0	0
T1	189379	4	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T35	0	4	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T42	0	4	0	0
T107	0	4	0	0
T168	0	2	0	0
T169	0	2	0	0
T170	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	133458	0	0
T1	189379	81012	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T35	0	180	0	0
T36	0	91	0	0
T37	0	73	0	0
T38	0	79	0	0
T42	0	136	0	0
T107	0	184	0	0
T168	0	68	0	0
T169	0	29	0	0
T170	0	92	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5865604	0	0
T1	189379	188974	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	3	0	0
T154	0	1	0	0
T165	574	1	0	0
T166	0	1	0	0
T171	521	0	0	0
T172	708	0	0	0
T173	552	0	0	0
T174	506	0	0	0
T175	21457	0	0	0
T176	425	0	0	0
T177	868	0	0	0
T178	404	0	0	0
T179	10925	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	71398	0	0
T1	189379	67408	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T35	0	141	0	0
T36	0	162	0	0
T37	0	53	0	0
T38	0	38	0	0
T42	0	189	0	0
T107	0	262	0	0
T168	0	56	0	0
T169	0	43	0	0
T170	0	238	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	58	0	0
T1	189379	2	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T42	0	2	0	0
T107	0	2	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5553864	0	0
T1	189379	3	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5556091	0	0
T1	189379	3	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	70	0	0
T1	189379	2	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T42	0	2	0	0
T107	0	2	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	61	0	0
T1	189379	2	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T42	0	2	0	0
T107	0	2	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	58	0	0
T1	189379	2	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T42	0	2	0	0
T107	0	2	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	58	0	0
T1	189379	2	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T42	0	2	0	0
T107	0	2	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	71316	0	0
T1	189379	67405	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T35	0	138	0	0
T36	0	161	0	0
T37	0	51	0	0
T38	0	36	0	0
T42	0	187	0	0
T107	0	259	0	0
T168	0	55	0	0
T169	0	41	0	0
T170	0	237	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	2311	0	0
T1	189379	2	0	0
T2	551	1	0	0
T3	298636	20	0	0
T4	525	6	0	0
T5	681	0	0	0
T7	0	1	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	4	0	0
T22	0	5	0	0
T56	0	5	0	0
T57	0	4	0	0
T59	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	33	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T42	0	2	0	0
T107	0	1	0	0
T163	0	2	0	0
T164	0	1	0	0
T168	0	1	0	0
T170	0	1	0	0
T180	0	2	0	0