Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T39,T42,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T39,T42,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T42,T36,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T39,T34
1	0	Covered	T4,T1,T5
1	1	Covered	T39,T42,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T42,T36,T44
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T42,T36,T44
0	1	Covered	T42,T36,T44
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T42,T36,T44
1	-	Covered	T42,T36,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T39,T42,T36
DetectSt	168	Covered	T42,T36,T44
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T42,T36,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T42,T36,T44
DebounceSt->IdleSt	163	Covered	T39,T44,T102
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T42,T36,T44
IdleSt->DebounceSt	148	Covered	T39,T42,T36
StableSt->IdleSt	206	Covered	T42,T36,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T39,T42,T36
0	1	Covered	T39,T42,T36
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T36,T44
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T39,T42,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T42,T36,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T44,T181
DebounceSt	-	0	0	-	-	-	-	Covered	T39,T42,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T42,T36,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T42,T36,T44
StableSt	-	-	-	-	-	-	0	Covered	T42,T36,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	90	0	0
CntIncr_A	6481552	25355	0	0
CntNoWrap_A	6481552	5865644	0	0
DetectStDropOut_A	6481552	0	0	0
DetectedOut_A	6481552	9061	0	0
DetectedPulseOut_A	6481552	43	0	0
DisabledIdleSt_A	6481552	5602877	0	0
DisabledNoDetection_A	6481552	5605099	0	0
EnterDebounceSt_A	6481552	47	0	0
EnterDetectSt_A	6481552	43	0	0
EnterStableSt_A	6481552	43	0	0
PulseIsPulse_A	6481552	43	0	0
StayInStableSt	6481552	8997	0	0
gen_high_level_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	90	0	0
T36	0	2	0	0
T38	0	2	0	0
T39	2881	1	0	0
T42	0	4	0	0
T43	545	0	0	0
T44	0	3	0	0
T47	6802	0	0	0
T50	2645	0	0	0
T51	661	0	0	0
T62	2876	0	0	0
T63	18154	0	0	0
T77	531	0	0	0
T88	8403	0	0	0
T108	0	2	0	0
T145	0	2	0	0
T161	0	2	0	0
T169	0	2	0	0
T182	0	2	0	0
T183	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	25355	0	0
T36	0	91	0	0
T38	0	60	0	0
T39	2881	62	0	0
T42	0	102	0	0
T43	545	0	0	0
T44	0	184	0	0
T47	6802	0	0	0
T50	2645	0	0	0
T51	661	0	0	0
T62	2876	0	0	0
T63	18154	0	0	0
T77	531	0	0	0
T88	8403	0	0	0
T108	0	14	0	0
T145	0	30	0	0
T161	0	26	0	0
T169	0	27	0	0
T182	0	41	0	0
T183	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5865644	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	9061	0	0
T36	1126	366	0	0
T38	0	101	0	0
T42	16126	172	0	0
T44	0	46	0	0
T71	4937	0	0	0
T84	13652	0	0	0
T105	63210	0	0	0
T108	0	43	0	0
T145	0	141	0	0
T158	403	0	0	0
T159	13775	0	0	0
T160	501	0	0	0
T161	0	218	0	0
T169	0	76	0	0
T182	0	145	0	0
T184	0	231	0	0
T185	16777	0	0	0
T186	22602	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	43	0	0
T36	1126	1	0	0
T38	0	1	0	0
T42	16126	2	0	0
T44	0	1	0	0
T71	4937	0	0	0
T84	13652	0	0	0
T105	63210	0	0	0
T108	0	1	0	0
T145	0	1	0	0
T158	403	0	0	0
T159	13775	0	0	0
T160	501	0	0	0
T161	0	1	0	0
T169	0	1	0	0
T182	0	1	0	0
T184	0	2	0	0
T185	16777	0	0	0
T186	22602	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5602877	0	0
T1	189379	188978	0	0
T2	551	4	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5605099	0	0
T1	189379	188979	0	0
T2	551	4	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	47	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	2881	1	0	0
T42	0	2	0	0
T43	545	0	0	0
T44	0	2	0	0
T47	6802	0	0	0
T50	2645	0	0	0
T51	661	0	0	0
T62	2876	0	0	0
T63	18154	0	0	0
T77	531	0	0	0
T88	8403	0	0	0
T108	0	1	0	0
T145	0	1	0	0
T161	0	1	0	0
T169	0	1	0	0
T182	0	1	0	0
T183	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	43	0	0
T36	1126	1	0	0
T38	0	1	0	0
T42	16126	2	0	0
T44	0	1	0	0
T71	4937	0	0	0
T84	13652	0	0	0
T105	63210	0	0	0
T108	0	1	0	0
T145	0	1	0	0
T158	403	0	0	0
T159	13775	0	0	0
T160	501	0	0	0
T161	0	1	0	0
T169	0	1	0	0
T182	0	1	0	0
T184	0	2	0	0
T185	16777	0	0	0
T186	22602	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	43	0	0
T36	1126	1	0	0
T38	0	1	0	0
T42	16126	2	0	0
T44	0	1	0	0
T71	4937	0	0	0
T84	13652	0	0	0
T105	63210	0	0	0
T108	0	1	0	0
T145	0	1	0	0
T158	403	0	0	0
T159	13775	0	0	0
T160	501	0	0	0
T161	0	1	0	0
T169	0	1	0	0
T182	0	1	0	0
T184	0	2	0	0
T185	16777	0	0	0
T186	22602	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	43	0	0
T36	1126	1	0	0
T38	0	1	0	0
T42	16126	2	0	0
T44	0	1	0	0
T71	4937	0	0	0
T84	13652	0	0	0
T105	63210	0	0	0
T108	0	1	0	0
T145	0	1	0	0
T158	403	0	0	0
T159	13775	0	0	0
T160	501	0	0	0
T161	0	1	0	0
T169	0	1	0	0
T182	0	1	0	0
T184	0	2	0	0
T185	16777	0	0	0
T186	22602	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	8997	0	0
T36	1126	365	0	0
T38	0	100	0	0
T42	16126	170	0	0
T44	0	45	0	0
T71	4937	0	0	0
T84	13652	0	0	0
T105	63210	0	0	0
T108	0	42	0	0
T145	0	139	0	0
T158	403	0	0	0
T159	13775	0	0	0
T160	501	0	0	0
T161	0	216	0	0
T169	0	74	0	0
T182	0	143	0	0
T184	0	227	0	0
T185	16777	0	0	0
T186	22602	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	21	0	0
T36	1126	1	0	0
T38	0	1	0	0
T42	16126	2	0	0
T44	0	1	0	0
T71	4937	0	0	0
T84	13652	0	0	0
T105	63210	0	0	0
T108	0	1	0	0
T158	403	0	0	0
T159	13775	0	0	0
T160	501	0	0	0
T167	0	1	0	0
T180	0	1	0	0
T185	16777	0	0	0
T186	22602	0	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T2,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T4,T5,T13
1	1	Covered	T1,T2,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T35,T107,T108
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T7,T39
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T7
1	-	Covered	T1,T7,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T7
DetectSt	168	Covered	T1,T2,T7
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T2,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T7
DebounceSt->IdleSt	163	Covered	T161,T167,T187
DetectSt->IdleSt	186	Covered	T35,T107,T108
DetectSt->StableSt	191	Covered	T1,T2,T7
IdleSt->DebounceSt	148	Covered	T1,T2,T7
StableSt->IdleSt	206	Covered	T1,T7,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T161,T167,T187
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	1	-	-	Covered	T35,T107,T108
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T39
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	160	0	0
CntIncr_A	6481552	124885	0	0
CntNoWrap_A	6481552	5865574	0	0
DetectStDropOut_A	6481552	8	0	0
DetectedOut_A	6481552	45978	0	0
DetectedPulseOut_A	6481552	69	0	0
DisabledIdleSt_A	6481552	5578338	0	0
DisabledNoDetection_A	6481552	5580560	0	0
EnterDebounceSt_A	6481552	84	0	0
EnterDetectSt_A	6481552	77	0	0
EnterStableSt_A	6481552	69	0	0
PulseIsPulse_A	6481552	69	0	0
StayInStableSt	6481552	45875	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6481552	2682	0	0
gen_low_level_sva.LowLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	160	0	0
T1	189379	4	0	0
T2	551	2	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	4	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T35	0	4	0	0
T36	0	4	0	0
T39	0	4	0	0
T44	0	6	0	0
T78	0	2	0	0
T107	0	4	0	0
T150	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	124885	0	0
T1	189379	81012	0	0
T2	551	32	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	118	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T35	0	180	0	0
T36	0	182	0	0
T39	0	124	0	0
T44	0	276	0	0
T78	0	39	0	0
T107	0	184	0	0
T150	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5865574	0	0
T1	189379	188974	0	0
T2	551	148	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	8	0	0
T35	865	1	0	0
T38	0	1	0	0
T42	16126	0	0	0
T70	493	0	0	0
T83	1254	0	0	0
T84	13652	0	0	0
T107	0	1	0	0
T108	0	1	0	0
T113	49822	0	0	0
T156	406	0	0	0
T157	1081	0	0	0
T167	0	1	0	0
T184	0	1	0	0
T188	0	1	0	0
T190	0	1	0	0
T191	505	0	0	0
T192	426	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	45978	0	0
T1	189379	86	0	0
T2	551	110	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	84	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T35	0	4	0	0
T36	0	76	0	0
T39	0	398	0	0
T44	0	121	0	0
T78	0	49	0	0
T107	0	220	0	0
T150	0	81	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	69	0	0
T1	189379	2	0	0
T2	551	1	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T39	0	2	0	0
T44	0	3	0	0
T78	0	1	0	0
T107	0	1	0	0
T150	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5578338	0	0
T1	189379	3	0	0
T2	551	4	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5580560	0	0
T1	189379	3	0	0
T2	551	4	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	84	0	0
T1	189379	2	0	0
T2	551	1	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	2	0	0
T44	0	3	0	0
T78	0	1	0	0
T107	0	2	0	0
T150	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	77	0	0
T1	189379	2	0	0
T2	551	1	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	2	0	0
T44	0	3	0	0
T78	0	1	0	0
T107	0	2	0	0
T150	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	69	0	0
T1	189379	2	0	0
T2	551	1	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T39	0	2	0	0
T44	0	3	0	0
T78	0	1	0	0
T107	0	1	0	0
T150	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	69	0	0
T1	189379	2	0	0
T2	551	1	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T39	0	2	0	0
T44	0	3	0	0
T78	0	1	0	0
T107	0	1	0	0
T150	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	45875	0	0
T1	189379	83	0	0
T2	551	108	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	81	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T35	0	3	0	0
T36	0	73	0	0
T39	0	395	0	0
T44	0	117	0	0
T78	0	47	0	0
T107	0	219	0	0
T150	0	78	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	2682	0	0
T1	189379	2	0	0
T2	551	1	0	0
T3	298636	23	0	0
T4	525	6	0	0
T5	681	3	0	0
T13	526	3	0	0
T14	745	6	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	3	0	0
T22	0	5	0	0
T56	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	34	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	1	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T44	0	2	0	0
T107	0	1	0	0
T150	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T7,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T7,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T7,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T39
1	0	Covered	T4,T2,T17
1	1	Covered	T1,T7,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T39
0	1	Covered	T107,T169,T195
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T39
0	1	Covered	T1,T7,T39
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T39
1	-	Covered	T1,T7,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T39
DetectSt	168	Covered	T1,T7,T39
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T7,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T39
DebounceSt->IdleSt	163	Covered	T164,T196,T102
DetectSt->IdleSt	186	Covered	T107,T169,T195
DetectSt->StableSt	191	Covered	T1,T7,T39
IdleSt->DebounceSt	148	Covered	T1,T7,T39
StableSt->IdleSt	206	Covered	T1,T7,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T39
0	1	Covered	T1,T7,T39
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T39
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T164,T196
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T39
DetectSt	-	-	-	-	1	-	-	Covered	T107,T169,T195
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T39
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	112	0	0
CntIncr_A	6481552	113762	0	0
CntNoWrap_A	6481552	5865622	0	0
DetectStDropOut_A	6481552	4	0	0
DetectedOut_A	6481552	39033	0	0
DetectedPulseOut_A	6481552	50	0	0
DisabledIdleSt_A	6481552	5405488	0	0
DisabledNoDetection_A	6481552	5407720	0	0
EnterDebounceSt_A	6481552	58	0	0
EnterDetectSt_A	6481552	54	0	0
EnterStableSt_A	6481552	50	0	0
PulseIsPulse_A	6481552	50	0	0
StayInStableSt	6481552	38960	0	0
gen_high_level_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	112	0	0
T1	189379	2	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	4	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T39	0	4	0	0
T40	0	4	0	0
T42	0	4	0	0
T44	0	6	0	0
T78	0	2	0	0
T107	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	113762	0	0
T1	189379	40506	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	118	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	31059	0	0
T35	0	90	0	0
T39	0	124	0	0
T40	0	32	0	0
T42	0	102	0	0
T44	0	198	0	0
T78	0	39	0	0
T107	0	92	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5865622	0	0
T1	189379	188976	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	4	0	0
T107	1176	1	0	0
T108	554	0	0	0
T167	0	1	0	0
T169	0	1	0	0
T195	0	1	0	0
T197	505	0	0	0
T198	18990	0	0	0
T199	1608	0	0	0
T200	421	0	0	0
T201	2186	0	0	0
T202	407	0	0	0
T203	410	0	0	0
T204	695	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	39033	0	0
T1	189379	6763	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	36	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	27820	0	0
T35	0	134	0	0
T39	0	213	0	0
T40	0	95	0	0
T42	0	405	0	0
T44	0	396	0	0
T78	0	50	0	0
T108	0	74	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	50	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	0	2	0	0
T44	0	3	0	0
T78	0	1	0	0
T108	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5405488	0	0
T1	189379	3	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5407720	0	0
T1	189379	3	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	58	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	0	2	0	0
T44	0	3	0	0
T78	0	1	0	0
T107	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	54	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	0	2	0	0
T44	0	3	0	0
T78	0	1	0	0
T107	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	50	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	0	2	0	0
T44	0	3	0	0
T78	0	1	0	0
T108	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	50	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	0	2	0	0
T44	0	3	0	0
T78	0	1	0	0
T108	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	38960	0	0
T1	189379	6762	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	34	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	27819	0	0
T35	0	133	0	0
T39	0	210	0	0
T40	0	92	0	0
T42	0	401	0	0
T44	0	392	0	0
T78	0	48	0	0
T108	0	73	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	26	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	0	2	0	0
T108	0	1	0	0
T169	0	1	0	0
T205	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T7,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T7,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T7,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T4,T17,T3
1	1	Covered	T1,T7,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T41
0	1	Covered	T206
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T41
0	1	Covered	T7,T41,T36
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T41
1	-	Covered	T7,T41,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T41
DetectSt	168	Covered	T1,T7,T41
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T7,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T41
DebounceSt->IdleSt	163	Covered	T102
DetectSt->IdleSt	186	Covered	T206
DetectSt->StableSt	191	Covered	T1,T7,T41
IdleSt->DebounceSt	148	Covered	T1,T7,T41
StableSt->IdleSt	206	Covered	T7,T41,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T41
0	1	Covered	T1,T7,T41
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T41
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T41
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T41
DetectSt	-	-	-	-	1	-	-	Covered	T206
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T41,T36
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	105	0	0
CntIncr_A	6481552	113805	0	0
CntNoWrap_A	6481552	5865629	0	0
DetectStDropOut_A	6481552	1	0	0
DetectedOut_A	6481552	90942	0	0
DetectedPulseOut_A	6481552	51	0	0
DisabledIdleSt_A	6481552	5401890	0	0
DisabledNoDetection_A	6481552	5404111	0	0
EnterDebounceSt_A	6481552	53	0	0
EnterDetectSt_A	6481552	52	0	0
EnterStableSt_A	6481552	51	0	0
PulseIsPulse_A	6481552	51	0	0
StayInStableSt	6481552	90863	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6481552	6275	0	0
gen_low_level_sva.LowLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	105	0	0
T1	189379	2	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	4	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	2	0	0
T36	0	4	0	0
T38	0	2	0	0
T41	0	6	0	0
T44	0	2	0	0
T107	0	2	0	0
T150	0	2	0	0
T161	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	113805	0	0
T1	189379	40506	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	118	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	31059	0	0
T36	0	182	0	0
T38	0	79	0	0
T41	0	255	0	0
T44	0	92	0	0
T107	0	92	0	0
T150	0	10	0	0
T161	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5865629	0	0
T1	189379	188976	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	1	0	0
T206	54788	1	0	0
T207	493	0	0	0
T208	492	0	0	0
T209	8795	0	0	0
T210	412	0	0	0
T211	628	0	0	0
T212	502	0	0	0
T213	526	0	0	0
T214	422	0	0	0
T215	595	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	90942	0	0
T1	189379	42	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	83	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	86917	0	0
T36	0	188	0	0
T38	0	37	0	0
T41	0	124	0	0
T44	0	122	0	0
T107	0	582	0	0
T150	0	62	0	0
T161	0	183	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	51	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T41	0	3	0	0
T44	0	1	0	0
T107	0	1	0	0
T150	0	1	0	0
T161	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5401890	0	0
T1	189379	3	0	0
T2	551	4	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5404111	0	0
T1	189379	3	0	0
T2	551	4	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	53	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T41	0	3	0	0
T44	0	1	0	0
T107	0	1	0	0
T150	0	1	0	0
T161	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	52	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T41	0	3	0	0
T44	0	1	0	0
T107	0	1	0	0
T150	0	1	0	0
T161	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	51	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T41	0	3	0	0
T44	0	1	0	0
T107	0	1	0	0
T150	0	1	0	0
T161	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	51	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T41	0	3	0	0
T44	0	1	0	0
T107	0	1	0	0
T150	0	1	0	0
T161	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	90863	0	0
T1	189379	40	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	80	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	86915	0	0
T36	0	185	0	0
T38	0	35	0	0
T41	0	120	0	0
T44	0	121	0	0
T107	0	580	0	0
T150	0	60	0	0
T161	0	180	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	6275	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	23	0	0
T4	525	3	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	4	0	0
T18	0	28	0	0
T22	0	7	0	0
T26	0	28	0	0
T56	0	3	0	0
T57	0	2	0	0
T59	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	22	0	0
T7	767	1	0	0
T8	12632	0	0	0
T23	9472	0	0	0
T27	12374	0	0	0
T36	0	1	0	0
T41	0	2	0	0
T44	0	1	0	0
T60	424	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T115	432	0	0	0
T116	450	0	0	0
T161	0	1	0	0
T163	0	1	0	0
T164	0	2	0	0
T167	0	1	0	0
T180	0	1	0	0
T206	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T2,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T4,T17,T3
1	1	Covered	T1,T2,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T108,T216,T217
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T7
1	-	Covered	T1,T2,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T7
DetectSt	168	Covered	T1,T2,T7
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T2,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T7
DebounceSt->IdleSt	163	Covered	T42,T44,T38
DetectSt->IdleSt	186	Covered	T108,T216,T217
DetectSt->StableSt	191	Covered	T1,T2,T7
IdleSt->DebounceSt	148	Covered	T1,T2,T7
StableSt->IdleSt	206	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T44,T38
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	1	-	-	Covered	T108,T216,T217
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	148	0	0
CntIncr_A	6481552	107834	0	0
CntNoWrap_A	6481552	5865586	0	0
DetectStDropOut_A	6481552	4	0	0
DetectedOut_A	6481552	22065	0	0
DetectedPulseOut_A	6481552	67	0	0
DisabledIdleSt_A	6481552	5309352	0	0
DisabledNoDetection_A	6481552	5311573	0	0
EnterDebounceSt_A	6481552	78	0	0
EnterDetectSt_A	6481552	71	0	0
EnterStableSt_A	6481552	67	0	0
PulseIsPulse_A	6481552	67	0	0
StayInStableSt	6481552	21970	0	0
gen_high_level_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	148	0	0
T1	189379	2	0	0
T2	551	2	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	4	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	2	0	0
T39	0	4	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	5	0	0
T43	0	2	0	0
T44	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	107834	0	0
T1	189379	40506	0	0
T2	551	32	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	118	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	31059	0	0
T39	0	124	0	0
T40	0	16	0	0
T41	0	85	0	0
T42	0	181	0	0
T43	0	44	0	0
T44	0	184	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5865586	0	0
T1	189379	188976	0	0
T2	551	148	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	4	0	0
T37	10951	0	0	0
T108	554	1	0	0
T203	410	0	0	0
T204	695	0	0	0
T216	0	2	0	0
T217	0	1	0	0
T218	18736	0	0	0
T219	1000	0	0	0
T220	743	0	0	0
T221	17883	0	0	0
T222	422	0	0	0
T223	568	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	22065	0	0
T1	189379	43	0	0
T2	551	26	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	84	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	42	0	0
T39	0	112	0	0
T40	0	40	0	0
T41	0	395	0	0
T42	0	191	0	0
T43	0	91	0	0
T44	0	47	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	67	0	0
T1	189379	1	0	0
T2	551	1	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5309352	0	0
T1	189379	3	0	0
T2	551	4	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5311573	0	0
T1	189379	3	0	0
T2	551	4	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	78	0	0
T1	189379	1	0	0
T2	551	1	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	1	0	0
T44	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	71	0	0
T1	189379	1	0	0
T2	551	1	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	67	0	0
T1	189379	1	0	0
T2	551	1	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	67	0	0
T1	189379	1	0	0
T2	551	1	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	21970	0	0
T1	189379	42	0	0
T2	551	25	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	81	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	40	0	0
T39	0	110	0	0
T40	0	38	0	0
T41	0	394	0	0
T42	0	188	0	0
T43	0	89	0	0
T44	0	46	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	38	0	0
T1	189379	1	0	0
T2	551	1	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	1	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T161	0	2	0	0
T182	0	1	0	0
T194	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T41,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T41,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T41,T40
1	0	Covered	T4,T2,T17
1	1	Covered	T1,T41,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T41,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T41,T42
0	1	Covered	T42,T150,T107
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T41,T42
1	-	Covered	T42,T150,T107

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T41,T42
DetectSt	168	Covered	T1,T41,T42
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T41,T42
DebounceSt->IdleSt	163	Covered	T102
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T41,T42
IdleSt->DebounceSt	148	Covered	T1,T41,T42
StableSt->IdleSt	206	Covered	T42,T150,T107

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T41,T42
0	1	Covered	T1,T41,T42
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T41,T42
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T41,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T41,T42
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T41,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T42,T150,T107
StableSt	-	-	-	-	-	-	0	Covered	T1,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	61	0	0
CntIncr_A	6481552	53459	0	0
CntNoWrap_A	6481552	5865673	0	0
DetectStDropOut_A	6481552	0	0	0
DetectedOut_A	6481552	49647	0	0
DetectedPulseOut_A	6481552	30	0	0
DisabledIdleSt_A	6481552	5518328	0	0
DisabledNoDetection_A	6481552	5520571	0	0
EnterDebounceSt_A	6481552	31	0	0
EnterDetectSt_A	6481552	30	0	0
EnterStableSt_A	6481552	30	0	0
PulseIsPulse_A	6481552	30	0	0
StayInStableSt	6481552	49604	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6481552	5939	0	0
gen_low_level_sva.LowLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	61	0	0
T1	189379	2	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T41	0	2	0	0
T42	0	4	0	0
T107	0	2	0	0
T150	0	4	0	0
T169	0	2	0	0
T170	0	2	0	0
T180	0	2	0	0
T182	0	2	0	0
T193	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	53459	0	0
T1	189379	40506	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T41	0	85	0	0
T42	0	136	0	0
T107	0	92	0	0
T150	0	20	0	0
T169	0	27	0	0
T170	0	92	0	0
T180	0	39	0	0
T182	0	41	0	0
T193	0	55	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5865673	0	0
T1	189379	188976	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	49647	0	0
T1	189379	47312	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T41	0	43	0	0
T42	0	177	0	0
T107	0	221	0	0
T150	0	82	0	0
T169	0	70	0	0
T170	0	130	0	0
T180	0	8	0	0
T182	0	146	0	0
T193	0	150	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	30	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T107	0	1	0	0
T150	0	2	0	0
T169	0	1	0	0
T170	0	1	0	0
T180	0	1	0	0
T182	0	1	0	0
T193	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5518328	0	0
T1	189379	3	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5520571	0	0
T1	189379	3	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	31	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T107	0	1	0	0
T150	0	2	0	0
T169	0	1	0	0
T170	0	1	0	0
T180	0	1	0	0
T182	0	1	0	0
T193	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	30	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T107	0	1	0	0
T150	0	2	0	0
T169	0	1	0	0
T170	0	1	0	0
T180	0	1	0	0
T182	0	1	0	0
T193	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	30	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T107	0	1	0	0
T150	0	2	0	0
T169	0	1	0	0
T170	0	1	0	0
T180	0	1	0	0
T182	0	1	0	0
T193	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	30	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T107	0	1	0	0
T150	0	2	0	0
T169	0	1	0	0
T170	0	1	0	0
T180	0	1	0	0
T182	0	1	0	0
T193	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	49604	0	0
T1	189379	47310	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T41	0	41	0	0
T42	0	174	0	0
T107	0	220	0	0
T150	0	79	0	0
T169	0	69	0	0
T170	0	128	0	0
T180	0	7	0	0
T182	0	144	0	0
T193	0	148	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5939	0	0
T1	189379	1	0	0
T2	551	1	0	0
T3	298636	23	0	0
T4	525	4	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	7	0	0
T18	0	28	0	0
T22	0	7	0	0
T28	0	1	0	0
T56	0	1	0	0
T57	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	16	0	0
T36	1126	0	0	0
T42	16126	1	0	0
T71	4937	0	0	0
T84	13652	0	0	0
T105	63210	0	0	0
T107	0	1	0	0
T150	0	1	0	0
T158	403	0	0	0
T159	13775	0	0	0
T160	501	0	0	0
T169	0	1	0	0
T180	0	1	0	0
T185	16777	0	0	0
T186	22602	0	0	0
T189	0	1	0	0
T224	0	1	0	0
T225	0	1	0	0
T226	0	2	0	0
T227	0	1	0	0