Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T43,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T43,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T43,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T43,T34
1	0	Covered	T4,T1,T17
1	1	Covered	T2,T43,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T43,T34
0	1	Covered	T107,T108,T206
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T43,T34
0	1	Covered	T43,T34,T42
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T43,T34
1	-	Covered	T43,T34,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T43,T34
DetectSt	168	Covered	T2,T43,T34
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T43,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T43,T34
DebounceSt->IdleSt	163	Covered	T228,T102,T229
DetectSt->IdleSt	186	Covered	T107,T108,T206
DetectSt->StableSt	191	Covered	T2,T43,T34
IdleSt->DebounceSt	148	Covered	T2,T43,T34
StableSt->IdleSt	206	Covered	T43,T34,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T43,T34
0	1	Covered	T2,T43,T34
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T43,T34
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T43,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T43,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T228,T229
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T43,T34
DetectSt	-	-	-	-	1	-	-	Covered	T107,T108,T206
DetectSt	-	-	-	-	0	1	-	Covered	T2,T43,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T34,T42
StableSt	-	-	-	-	-	-	0	Covered	T2,T43,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	137	0	0
CntIncr_A	6481552	67843	0	0
CntNoWrap_A	6481552	5865597	0	0
DetectStDropOut_A	6481552	7	0	0
DetectedOut_A	6481552	58187	0	0
DetectedPulseOut_A	6481552	60	0	0
DisabledIdleSt_A	6481552	5498202	0	0
DisabledNoDetection_A	6481552	5500426	0	0
EnterDebounceSt_A	6481552	71	0	0
EnterDetectSt_A	6481552	67	0	0
EnterStableSt_A	6481552	60	0	0
PulseIsPulse_A	6481552	60	0	0
StayInStableSt	6481552	58101	0	0
gen_high_level_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	137	0	0
T2	551	2	0	0
T3	298636	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T22	495	0	0	0
T28	453	0	0	0
T34	0	2	0	0
T37	0	2	0	0
T42	0	4	0	0
T43	0	2	0	0
T44	0	4	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T107	0	6	0	0
T108	0	4	0	0
T150	0	6	0	0
T230	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	67843	0	0
T2	551	32	0	0
T3	298636	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T22	495	0	0	0
T28	453	0	0	0
T34	0	31059	0	0
T37	0	73	0	0
T42	0	90	0	0
T43	0	44	0	0
T44	0	28	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T107	0	276	0	0
T108	0	28	0	0
T150	0	30	0	0
T230	0	19	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5865597	0	0
T1	189379	188978	0	0
T2	551	148	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	7	0	0
T107	1176	1	0	0
T108	554	1	0	0
T167	0	1	0	0
T197	505	0	0	0
T198	18990	0	0	0
T199	1608	0	0	0
T200	421	0	0	0
T201	2186	0	0	0
T202	407	0	0	0
T203	410	0	0	0
T204	695	0	0	0
T206	0	1	0	0
T227	0	1	0	0
T229	0	1	0	0
T231	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	58187	0	0
T2	551	50	0	0
T3	298636	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T22	495	0	0	0
T28	453	0	0	0
T34	0	24713	0	0
T37	0	52	0	0
T42	0	142	0	0
T43	0	9	0	0
T44	0	86	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T107	0	262	0	0
T108	0	40	0	0
T150	0	135	0	0
T230	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	60	0	0
T2	551	1	0	0
T3	298636	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T22	495	0	0	0
T28	453	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T107	0	2	0	0
T108	0	1	0	0
T150	0	3	0	0
T230	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5498202	0	0
T1	189379	188978	0	0
T2	551	4	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5500426	0	0
T1	189379	188979	0	0
T2	551	4	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	71	0	0
T2	551	1	0	0
T3	298636	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T22	495	0	0	0
T28	453	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T107	0	3	0	0
T108	0	2	0	0
T150	0	3	0	0
T230	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	67	0	0
T2	551	1	0	0
T3	298636	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T22	495	0	0	0
T28	453	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T107	0	3	0	0
T108	0	2	0	0
T150	0	3	0	0
T230	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	60	0	0
T2	551	1	0	0
T3	298636	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T22	495	0	0	0
T28	453	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T107	0	2	0	0
T108	0	1	0	0
T150	0	3	0	0
T230	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	60	0	0
T2	551	1	0	0
T3	298636	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T22	495	0	0	0
T28	453	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T107	0	2	0	0
T108	0	1	0	0
T150	0	3	0	0
T230	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	58101	0	0
T2	551	48	0	0
T3	298636	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T22	495	0	0	0
T28	453	0	0	0
T34	0	24712	0	0
T37	0	50	0	0
T42	0	140	0	0
T43	0	8	0	0
T44	0	83	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T107	0	259	0	0
T108	0	38	0	0
T150	0	131	0	0
T230	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	33	0	0
T24	492	0	0	0
T33	32904	0	0	0
T34	0	1	0	0
T41	1149	0	0	0
T42	0	2	0	0
T43	545	1	0	0
T44	0	1	0	0
T51	661	0	0	0
T65	551	0	0	0
T101	28438	0	0	0
T107	0	1	0	0
T131	402	0	0	0
T132	422	0	0	0
T133	442	0	0	0
T150	0	2	0	0
T164	0	2	0	0
T169	0	1	0	0
T182	0	1	0	0
T206	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T7,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T7,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T39
1	0	Covered	T4,T1,T17
1	1	Covered	T7,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T39,T40
0	1	Not Covered
1	0	Covered	T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T39,T40
0	1	Covered	T7,T39,T40
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T39,T40
1	-	Covered	T7,T39,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T39,T40
DetectSt	168	Covered	T7,T39,T40
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T7,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T39,T40
DebounceSt->IdleSt	163	Covered	T44,T150,T102
DetectSt->IdleSt	186	Covered	T61
DetectSt->StableSt	191	Covered	T7,T39,T40
IdleSt->DebounceSt	148	Covered	T7,T39,T40
StableSt->IdleSt	206	Covered	T7,T39,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T39,T40
0	1	Covered	T7,T39,T40
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T39,T40
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T44,T150
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T39,T40
DetectSt	-	-	-	-	1	-	-	Covered	T61
DetectSt	-	-	-	-	0	1	-	Covered	T7,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T39,T40
StableSt	-	-	-	-	-	-	0	Covered	T7,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	97	0	0
CntIncr_A	6481552	25464	0	0
CntNoWrap_A	6481552	5865637	0	0
DetectStDropOut_A	6481552	0	0	0
DetectedOut_A	6481552	2968	0	0
DetectedPulseOut_A	6481552	46	0	0
DisabledIdleSt_A	6481552	5750927	0	0
DisabledNoDetection_A	6481552	5753149	0	0
EnterDebounceSt_A	6481552	50	0	0
EnterDetectSt_A	6481552	47	0	0
EnterStableSt_A	6481552	46	0	0
PulseIsPulse_A	6481552	46	0	0
StayInStableSt	6481552	2900	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6481552	5923	0	0
gen_low_level_sva.LowLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	97	0	0
T7	767	2	0	0
T8	12632	0	0	0
T23	9472	0	0	0
T27	12374	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	4	0	0
T40	0	4	0	0
T44	0	5	0	0
T60	424	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T108	0	2	0	0
T115	432	0	0	0
T116	450	0	0	0
T150	0	3	0	0
T182	0	2	0	0
T194	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	25464	0	0
T7	767	59	0	0
T8	12632	0	0	0
T23	9472	0	0	0
T27	12374	0	0	0
T35	0	90	0	0
T36	0	91	0	0
T39	0	124	0	0
T40	0	32	0	0
T44	0	198	0	0
T60	424	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T108	0	14	0	0
T115	432	0	0	0
T116	450	0	0	0
T150	0	20	0	0
T182	0	41	0	0
T194	0	92	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5865637	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	2968	0	0
T7	767	112	0	0
T8	12632	0	0	0
T23	9472	0	0	0
T27	12374	0	0	0
T35	0	47	0	0
T36	0	132	0	0
T39	0	73	0	0
T40	0	81	0	0
T44	0	95	0	0
T60	424	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T108	0	60	0	0
T115	432	0	0	0
T116	450	0	0	0
T150	0	9	0	0
T182	0	70	0	0
T194	0	131	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	46	0	0
T7	767	1	0	0
T8	12632	0	0	0
T23	9472	0	0	0
T27	12374	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T44	0	2	0	0
T60	424	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T108	0	1	0	0
T115	432	0	0	0
T116	450	0	0	0
T150	0	1	0	0
T182	0	1	0	0
T194	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5750927	0	0
T1	189379	188978	0	0
T2	551	4	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5753149	0	0
T1	189379	188979	0	0
T2	551	4	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	50	0	0
T7	767	1	0	0
T8	12632	0	0	0
T23	9472	0	0	0
T27	12374	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T44	0	3	0	0
T60	424	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T108	0	1	0	0
T115	432	0	0	0
T116	450	0	0	0
T150	0	2	0	0
T182	0	1	0	0
T194	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	47	0	0
T7	767	1	0	0
T8	12632	0	0	0
T23	9472	0	0	0
T27	12374	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T44	0	2	0	0
T60	424	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T108	0	1	0	0
T115	432	0	0	0
T116	450	0	0	0
T150	0	1	0	0
T182	0	1	0	0
T194	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	46	0	0
T7	767	1	0	0
T8	12632	0	0	0
T23	9472	0	0	0
T27	12374	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T44	0	2	0	0
T60	424	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T108	0	1	0	0
T115	432	0	0	0
T116	450	0	0	0
T150	0	1	0	0
T182	0	1	0	0
T194	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	46	0	0
T7	767	1	0	0
T8	12632	0	0	0
T23	9472	0	0	0
T27	12374	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T44	0	2	0	0
T60	424	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T108	0	1	0	0
T115	432	0	0	0
T116	450	0	0	0
T150	0	1	0	0
T182	0	1	0	0
T194	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	2900	0	0
T7	767	111	0	0
T8	12632	0	0	0
T23	9472	0	0	0
T27	12374	0	0	0
T35	0	45	0	0
T36	0	131	0	0
T39	0	70	0	0
T40	0	78	0	0
T44	0	92	0	0
T60	424	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T108	0	59	0	0
T115	432	0	0	0
T116	450	0	0	0
T150	0	8	0	0
T182	0	68	0	0
T194	0	128	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5923	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	26	0	0
T4	525	5	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	5	0	0
T18	0	24	0	0
T22	0	8	0	0
T28	0	1	0	0
T56	0	4	0	0
T57	0	5	0	0
T59	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	24	0	0
T7	767	1	0	0
T8	12632	0	0	0
T23	9472	0	0	0
T27	12374	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T60	424	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T97	411	0	0	0
T108	0	1	0	0
T115	432	0	0	0
T116	450	0	0	0
T150	0	1	0	0
T164	0	1	0	0
T170	0	1	0	0
T194	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T2,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T39
1	0	Covered	T4,T17,T3
1	1	Covered	T1,T2,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T39
0	1	Covered	T38,T194,T165
1	0	Covered	T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T39
0	1	Covered	T39,T34,T150
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T39
1	-	Covered	T39,T34,T150

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T39
DetectSt	168	Covered	T1,T2,T39
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T2,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T39
DebounceSt->IdleSt	163	Covered	T37,T102
DetectSt->IdleSt	186	Covered	T38,T194,T165
DetectSt->StableSt	191	Covered	T1,T2,T39
IdleSt->DebounceSt	148	Covered	T1,T2,T39
StableSt->IdleSt	206	Covered	T39,T34,T150

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T39
0	1	Covered	T1,T2,T39
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T39
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T37
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T39
DetectSt	-	-	-	-	1	-	-	Covered	T38,T194,T165
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T34,T150
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	114	0	0
CntIncr_A	6481552	74402	0	0
CntNoWrap_A	6481552	5865620	0	0
DetectStDropOut_A	6481552	3	0	0
DetectedOut_A	6481552	60701	0	0
DetectedPulseOut_A	6481552	52	0	0
DisabledIdleSt_A	6481552	5484523	0	0
DisabledNoDetection_A	6481552	5486756	0	0
EnterDebounceSt_A	6481552	58	0	0
EnterDetectSt_A	6481552	56	0	0
EnterStableSt_A	6481552	52	0	0
PulseIsPulse_A	6481552	52	0	0
StayInStableSt	6481552	60625	0	0
gen_high_level_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	114	0	0
T1	189379	2	0	0
T2	551	2	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T78	0	2	0	0
T150	0	6	0	0
T182	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	74402	0	0
T1	189379	40506	0	0
T2	551	32	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	31059	0	0
T35	0	90	0	0
T37	0	73	0	0
T38	0	34	0	0
T39	0	62	0	0
T78	0	39	0	0
T150	0	30	0	0
T182	0	82	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5865620	0	0
T1	189379	188976	0	0
T2	551	148	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	3	0	0
T38	6400	1	0	0
T165	0	1	0	0
T194	0	1	0	0
T232	9881	0	0	0
T233	1631	0	0	0
T234	423	0	0	0
T235	493	0	0	0
T236	496	0	0	0
T237	7505	0	0	0
T238	416	0	0	0
T239	15218	0	0	0
T240	979	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	60701	0	0
T1	189379	41	0	0
T2	551	109	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	55817	0	0
T35	0	46	0	0
T39	0	372	0	0
T78	0	50	0	0
T150	0	94	0	0
T168	0	279	0	0
T182	0	110	0	0
T194	0	89	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	52	0	0
T1	189379	1	0	0
T2	551	1	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T39	0	1	0	0
T78	0	1	0	0
T150	0	3	0	0
T168	0	1	0	0
T182	0	2	0	0
T194	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5484523	0	0
T1	189379	3	0	0
T2	551	4	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5486756	0	0
T1	189379	3	0	0
T2	551	4	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	58	0	0
T1	189379	1	0	0
T2	551	1	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T78	0	1	0	0
T150	0	3	0	0
T182	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	56	0	0
T1	189379	1	0	0
T2	551	1	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T78	0	1	0	0
T150	0	3	0	0
T182	0	2	0	0
T194	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	52	0	0
T1	189379	1	0	0
T2	551	1	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T39	0	1	0	0
T78	0	1	0	0
T150	0	3	0	0
T168	0	1	0	0
T182	0	2	0	0
T194	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	52	0	0
T1	189379	1	0	0
T2	551	1	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T39	0	1	0	0
T78	0	1	0	0
T150	0	3	0	0
T168	0	1	0	0
T182	0	2	0	0
T194	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	60625	0	0
T1	189379	39	0	0
T2	551	107	0	0
T3	298636	0	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	55816	0	0
T35	0	44	0	0
T39	0	371	0	0
T78	0	48	0	0
T150	0	90	0	0
T168	0	277	0	0
T182	0	107	0	0
T194	0	88	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	28	0	0
T34	0	1	0	0
T39	2881	1	0	0
T43	545	0	0	0
T47	6802	0	0	0
T50	2645	0	0	0
T51	661	0	0	0
T62	2876	0	0	0
T63	18154	0	0	0
T77	531	0	0	0
T88	8403	0	0	0
T150	0	2	0	0
T167	0	1	0	0
T177	0	1	0	0
T180	0	1	0	0
T182	0	1	0	0
T183	402	0	0	0
T184	0	2	0	0
T194	0	1	0	0
T228	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T34,T37,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T34,T37,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T34,T37,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T43,T40
1	0	Covered	T4,T17,T3
1	1	Covered	T34,T37,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T37,T38
0	1	Covered	T229
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T37,T38
0	1	Covered	T184,T167,T180
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T37,T38
1	-	Covered	T184,T167,T180

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T37,T38
DetectSt	168	Covered	T34,T37,T38
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T34,T37,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T37,T38
DebounceSt->IdleSt	163	Covered	T228,T102,T229
DetectSt->IdleSt	186	Covered	T229
DetectSt->StableSt	191	Covered	T34,T37,T38
IdleSt->DebounceSt	148	Covered	T34,T37,T38
StableSt->IdleSt	206	Covered	T37,T38,T145

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T34,T37,T38
0	1	Covered	T34,T37,T38
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T37,T38
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T37,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T37,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T228,T229
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T37,T38
DetectSt	-	-	-	-	1	-	-	Covered	T229
DetectSt	-	-	-	-	0	1	-	Covered	T34,T37,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T184,T167,T180
StableSt	-	-	-	-	-	-	0	Covered	T34,T37,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	75	0	0
CntIncr_A	6481552	44481	0	0
CntNoWrap_A	6481552	5865659	0	0
DetectStDropOut_A	6481552	1	0	0
DetectedOut_A	6481552	2276	0	0
DetectedPulseOut_A	6481552	35	0	0
DisabledIdleSt_A	6481552	5338285	0	0
DisabledNoDetection_A	6481552	5340510	0	0
EnterDebounceSt_A	6481552	39	0	0
EnterDetectSt_A	6481552	36	0	0
EnterStableSt_A	6481552	35	0	0
PulseIsPulse_A	6481552	35	0	0
StayInStableSt	6481552	2222	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6481552	5856	0	0
gen_low_level_sva.LowLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	75	0	0
T34	177265	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T119	4672	0	0	0
T120	10516	0	0	0
T145	0	2	0	0
T165	0	2	0	0
T167	0	4	0	0
T170	0	2	0	0
T180	0	4	0	0
T184	0	6	0	0
T228	0	1	0	0
T241	15029	0	0	0
T242	751	0	0	0
T243	441	0	0	0
T244	430	0	0	0
T245	415	0	0	0
T246	402	0	0	0
T247	35835	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	44481	0	0
T34	177265	31059	0	0
T37	0	73	0	0
T38	0	34	0	0
T119	4672	0	0	0
T120	10516	0	0	0
T145	0	30	0	0
T165	0	61	0	0
T167	0	162	0	0
T170	0	92	0	0
T180	0	49	0	0
T184	0	189	0	0
T228	0	88	0	0
T241	15029	0	0	0
T242	751	0	0	0
T243	441	0	0	0
T244	430	0	0	0
T245	415	0	0	0
T246	402	0	0	0
T247	35835	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5865659	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	1	0	0
T229	70147	1	0	0
T248	503	0	0	0
T249	416	0	0	0
T250	7658	0	0	0
T251	490	0	0	0
T252	7860	0	0	0
T253	426	0	0	0
T254	402	0	0	0
T255	1672	0	0	0
T256	594	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	2276	0	0
T34	177265	41	0	0
T37	0	52	0	0
T38	0	41	0	0
T119	4672	0	0	0
T120	10516	0	0	0
T145	0	70	0	0
T162	0	80	0	0
T165	0	42	0	0
T167	0	171	0	0
T170	0	38	0	0
T180	0	92	0	0
T184	0	130	0	0
T241	15029	0	0	0
T242	751	0	0	0
T243	441	0	0	0
T244	430	0	0	0
T245	415	0	0	0
T246	402	0	0	0
T247	35835	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	35	0	0
T34	177265	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T119	4672	0	0	0
T120	10516	0	0	0
T145	0	1	0	0
T162	0	2	0	0
T165	0	1	0	0
T167	0	2	0	0
T170	0	1	0	0
T180	0	2	0	0
T184	0	3	0	0
T241	15029	0	0	0
T242	751	0	0	0
T243	441	0	0	0
T244	430	0	0	0
T245	415	0	0	0
T246	402	0	0	0
T247	35835	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5338285	0	0
T1	189379	3	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5340510	0	0
T1	189379	3	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	39	0	0
T34	177265	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T119	4672	0	0	0
T120	10516	0	0	0
T145	0	1	0	0
T165	0	1	0	0
T167	0	2	0	0
T170	0	1	0	0
T180	0	2	0	0
T184	0	3	0	0
T228	0	1	0	0
T241	15029	0	0	0
T242	751	0	0	0
T243	441	0	0	0
T244	430	0	0	0
T245	415	0	0	0
T246	402	0	0	0
T247	35835	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	36	0	0
T34	177265	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T119	4672	0	0	0
T120	10516	0	0	0
T145	0	1	0	0
T162	0	2	0	0
T165	0	1	0	0
T167	0	2	0	0
T170	0	1	0	0
T180	0	2	0	0
T184	0	3	0	0
T241	15029	0	0	0
T242	751	0	0	0
T243	441	0	0	0
T244	430	0	0	0
T245	415	0	0	0
T246	402	0	0	0
T247	35835	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	35	0	0
T34	177265	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T119	4672	0	0	0
T120	10516	0	0	0
T145	0	1	0	0
T162	0	2	0	0
T165	0	1	0	0
T167	0	2	0	0
T170	0	1	0	0
T180	0	2	0	0
T184	0	3	0	0
T241	15029	0	0	0
T242	751	0	0	0
T243	441	0	0	0
T244	430	0	0	0
T245	415	0	0	0
T246	402	0	0	0
T247	35835	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	35	0	0
T34	177265	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T119	4672	0	0	0
T120	10516	0	0	0
T145	0	1	0	0
T162	0	2	0	0
T165	0	1	0	0
T167	0	2	0	0
T170	0	1	0	0
T180	0	2	0	0
T184	0	3	0	0
T241	15029	0	0	0
T242	751	0	0	0
T243	441	0	0	0
T244	430	0	0	0
T245	415	0	0	0
T246	402	0	0	0
T247	35835	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	2222	0	0
T34	177265	39	0	0
T37	0	50	0	0
T38	0	39	0	0
T119	4672	0	0	0
T120	10516	0	0	0
T145	0	68	0	0
T162	0	78	0	0
T165	0	40	0	0
T167	0	168	0	0
T170	0	36	0	0
T180	0	90	0	0
T184	0	125	0	0
T241	15029	0	0	0
T242	751	0	0	0
T243	441	0	0	0
T244	430	0	0	0
T245	415	0	0	0
T246	402	0	0	0
T247	35835	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5856	0	0
T1	189379	0	0	0
T2	551	0	0	0
T3	298636	20	0	0
T4	525	3	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	3	0	0
T18	0	33	0	0
T22	0	8	0	0
T26	0	21	0	0
T28	0	1	0	0
T56	0	3	0	0
T57	0	4	0	0
T59	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	15	0	0
T143	0	2	0	0
T162	0	2	0	0
T167	0	1	0	0
T180	0	2	0	0
T184	49330	1	0	0
T224	0	1	0	0
T257	0	1	0	0
T258	0	1	0	0
T259	0	1	0	0
T260	0	1	0	0
T261	10614	0	0	0
T262	523	0	0	0
T263	25702	0	0	0
T264	724	0	0	0
T265	501	0	0	0
T266	438	0	0	0
T267	12424	0	0	0
T268	525	0	0	0
T269	638	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T15
1	1	Covered	T4,T1,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T7,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T7,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T7,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T39
1	0	Covered	T4,T15,T2
1	1	Covered	T1,T7,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T39
0	1	Covered	T184,T260,T231
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T39
0	1	Covered	T39,T43,T41
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T39
1	-	Covered	T39,T43,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T39
DetectSt	168	Covered	T1,T7,T39
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T7,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T39
DebounceSt->IdleSt	163	Covered	T42,T37,T165
DetectSt->IdleSt	186	Covered	T184,T260,T231
DetectSt->StableSt	191	Covered	T1,T7,T39
IdleSt->DebounceSt	148	Covered	T1,T7,T39
StableSt->IdleSt	206	Covered	T39,T43,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T39
0	1	Covered	T1,T7,T39
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T39
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T37,T165
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T39
DetectSt	-	-	-	-	1	-	-	Covered	T184,T260,T231
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T43,T41
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	123	0	0
CntIncr_A	6481552	154774	0	0
CntNoWrap_A	6481552	5865611	0	0
DetectStDropOut_A	6481552	3	0	0
DetectedOut_A	6481552	243851	0	0
DetectedPulseOut_A	6481552	56	0	0
DisabledIdleSt_A	6481552	5379639	0	0
DisabledNoDetection_A	6481552	5381872	0	0
EnterDebounceSt_A	6481552	65	0	0
EnterDetectSt_A	6481552	59	0	0
EnterStableSt_A	6481552	56	0	0
PulseIsPulse_A	6481552	56	0	0
StayInStableSt	6481552	243768	0	0
gen_high_level_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	123	0	0
T1	189379	2	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	2	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	4	0	0
T35	0	4	0	0
T36	0	4	0	0
T39	0	4	0	0
T41	0	4	0	0
T42	0	3	0	0
T43	0	2	0	0
T78	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	154774	0	0
T1	189379	40506	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	59	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	62118	0	0
T35	0	180	0	0
T36	0	182	0	0
T39	0	124	0	0
T41	0	170	0	0
T42	0	102	0	0
T43	0	44	0	0
T78	0	39	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5865611	0	0
T1	189379	188976	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	3	0	0
T184	49330	1	0	0
T231	0	1	0	0
T260	0	1	0	0
T261	10614	0	0	0
T262	523	0	0	0
T263	25702	0	0	0
T264	724	0	0	0
T265	501	0	0	0
T266	438	0	0	0
T267	12424	0	0	0
T268	525	0	0	0
T269	638	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	243851	0	0
T1	189379	148463	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	44	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	83635	0	0
T35	0	141	0	0
T36	0	39	0	0
T39	0	100	0	0
T41	0	227	0	0
T42	0	194	0	0
T43	0	7	0	0
T78	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	56	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	1	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T78	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5379639	0	0
T1	189379	3	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5381872	0	0
T1	189379	3	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	65	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	1	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T78	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	59	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	1	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T78	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	56	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	1	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T78	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	56	0	0
T1	189379	1	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	1	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T78	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	243768	0	0
T1	189379	148461	0	0
T2	551	0	0	0
T3	298636	0	0	0
T5	681	0	0	0
T7	0	42	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	0	0	0
T16	4402	0	0	0
T17	521	0	0	0
T18	11652	0	0	0
T34	0	83632	0	0
T35	0	138	0	0
T36	0	37	0	0
T39	0	97	0	0
T41	0	224	0	0
T42	0	193	0	0
T43	0	6	0	0
T78	0	36	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	28	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T39	2881	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	545	1	0	0
T44	0	1	0	0
T47	6802	0	0	0
T50	2645	0	0	0
T51	661	0	0	0
T62	2876	0	0	0
T63	18154	0	0	0
T77	531	0	0	0
T88	8403	0	0	0
T150	0	1	0	0
T183	402	0	0	0
T230	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T15
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T15
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T34,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T34,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T34,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T34,T78
1	0	Covered	T4,T15,T17
1	1	Covered	T34,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T36
0	1	Covered	T180
1	0	Covered	T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T36
0	1	Covered	T34,T35,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T35,T36
1	-	Covered	T34,T35,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T35,T36
DetectSt	168	Covered	T34,T35,T36
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T34,T35,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T35,T36
DebounceSt->IdleSt	163	Covered	T163,T102,T146
DetectSt->IdleSt	186	Covered	T180,T61
DetectSt->StableSt	191	Covered	T34,T35,T36
IdleSt->DebounceSt	148	Covered	T34,T35,T36
StableSt->IdleSt	206	Covered	T34,T35,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T34,T35,T36
0	1	Covered	T34,T35,T36
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T35,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T163,T146,T181
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T180,T61
DetectSt	-	-	-	-	0	1	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T35,T36
StableSt	-	-	-	-	-	-	0	Covered	T34,T35,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	86	0	0
CntIncr_A	6481552	33295	0	0
CntNoWrap_A	6481552	5865648	0	0
DetectStDropOut_A	6481552	1	0	0
DetectedOut_A	6481552	3091	0	0
DetectedPulseOut_A	6481552	39	0	0
DisabledIdleSt_A	6481552	5591320	0	0
DisabledNoDetection_A	6481552	5593545	0	0
EnterDebounceSt_A	6481552	45	0	0
EnterDetectSt_A	6481552	41	0	0
EnterStableSt_A	6481552	39	0	0
PulseIsPulse_A	6481552	39	0	0
StayInStableSt	6481552	3039	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6481552	6459	0	0
gen_low_level_sva.LowLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	86	0	0
T34	177265	2	0	0
T35	0	2	0	0
T36	0	4	0	0
T107	0	2	0	0
T119	4672	0	0	0
T120	10516	0	0	0
T150	0	2	0	0
T163	0	3	0	0
T167	0	2	0	0
T180	0	8	0	0
T184	0	4	0	0
T206	0	4	0	0
T241	15029	0	0	0
T242	751	0	0	0
T243	441	0	0	0
T244	430	0	0	0
T245	415	0	0	0
T246	402	0	0	0
T247	35835	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	33295	0	0
T34	177265	31059	0	0
T35	0	90	0	0
T36	0	182	0	0
T107	0	92	0	0
T119	4672	0	0	0
T120	10516	0	0	0
T150	0	10	0	0
T163	0	142	0	0
T167	0	84	0	0
T180	0	98	0	0
T184	0	98	0	0
T206	0	130	0	0
T241	15029	0	0	0
T242	751	0	0	0
T243	441	0	0	0
T244	430	0	0	0
T245	415	0	0	0
T246	402	0	0	0
T247	35835	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5865648	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	1	0	0
T165	574	0	0	0
T171	521	0	0	0
T172	708	0	0	0
T173	552	0	0	0
T174	506	0	0	0
T175	21457	0	0	0
T176	425	0	0	0
T177	868	0	0	0
T178	404	0	0	0
T180	3098	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	3091	0	0
T34	177265	42	0	0
T35	0	43	0	0
T36	0	310	0	0
T107	0	220	0	0
T119	4672	0	0	0
T120	10516	0	0	0
T150	0	8	0	0
T163	0	6	0	0
T167	0	45	0	0
T180	0	57	0	0
T184	0	87	0	0
T206	0	147	0	0
T241	15029	0	0	0
T242	751	0	0	0
T243	441	0	0	0
T244	430	0	0	0
T245	415	0	0	0
T246	402	0	0	0
T247	35835	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	39	0	0
T34	177265	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T107	0	1	0	0
T119	4672	0	0	0
T120	10516	0	0	0
T150	0	1	0	0
T163	0	1	0	0
T167	0	1	0	0
T180	0	3	0	0
T184	0	2	0	0
T206	0	2	0	0
T241	15029	0	0	0
T242	751	0	0	0
T243	441	0	0	0
T244	430	0	0	0
T245	415	0	0	0
T246	402	0	0	0
T247	35835	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5591320	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5593545	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	45	0	0
T34	177265	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T107	0	1	0	0
T119	4672	0	0	0
T120	10516	0	0	0
T150	0	1	0	0
T163	0	2	0	0
T167	0	1	0	0
T180	0	4	0	0
T184	0	2	0	0
T206	0	2	0	0
T241	15029	0	0	0
T242	751	0	0	0
T243	441	0	0	0
T244	430	0	0	0
T245	415	0	0	0
T246	402	0	0	0
T247	35835	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	41	0	0
T34	177265	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T107	0	1	0	0
T119	4672	0	0	0
T120	10516	0	0	0
T150	0	1	0	0
T163	0	1	0	0
T167	0	1	0	0
T180	0	4	0	0
T184	0	2	0	0
T206	0	2	0	0
T241	15029	0	0	0
T242	751	0	0	0
T243	441	0	0	0
T244	430	0	0	0
T245	415	0	0	0
T246	402	0	0	0
T247	35835	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	39	0	0
T34	177265	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T107	0	1	0	0
T119	4672	0	0	0
T120	10516	0	0	0
T150	0	1	0	0
T163	0	1	0	0
T167	0	1	0	0
T180	0	3	0	0
T184	0	2	0	0
T206	0	2	0	0
T241	15029	0	0	0
T242	751	0	0	0
T243	441	0	0	0
T244	430	0	0	0
T245	415	0	0	0
T246	402	0	0	0
T247	35835	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	39	0	0
T34	177265	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T107	0	1	0	0
T119	4672	0	0	0
T120	10516	0	0	0
T150	0	1	0	0
T163	0	1	0	0
T167	0	1	0	0
T180	0	3	0	0
T184	0	2	0	0
T206	0	2	0	0
T241	15029	0	0	0
T242	751	0	0	0
T243	441	0	0	0
T244	430	0	0	0
T245	415	0	0	0
T246	402	0	0	0
T247	35835	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	3039	0	0
T34	177265	41	0	0
T35	0	42	0	0
T36	0	307	0	0
T107	0	219	0	0
T119	4672	0	0	0
T120	10516	0	0	0
T150	0	7	0	0
T163	0	5	0	0
T167	0	43	0	0
T180	0	53	0	0
T184	0	84	0	0
T206	0	145	0	0
T241	15029	0	0	0
T242	751	0	0	0
T243	441	0	0	0
T244	430	0	0	0
T245	415	0	0	0
T246	402	0	0	0
T247	35835	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	6459	0	0
T1	189379	0	0	0
T2	551	0	0	0
T3	298636	22	0	0
T4	525	4	0	0
T5	681	0	0	0
T13	526	0	0	0
T14	745	0	0	0
T15	664	3	0	0
T16	4402	0	0	0
T17	521	4	0	0
T18	0	26	0	0
T22	0	10	0	0
T26	0	23	0	0
T56	0	2	0	0
T57	0	6	0	0
T59	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	26	0	0
T34	177265	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T107	0	1	0	0
T119	4672	0	0	0
T120	10516	0	0	0
T150	0	1	0	0
T163	0	1	0	0
T180	0	2	0	0
T184	0	1	0	0
T206	0	2	0	0
T216	0	2	0	0
T241	15029	0	0	0
T242	751	0	0	0
T243	441	0	0	0
T244	430	0	0	0
T245	415	0	0	0
T246	402	0	0	0
T247	35835	0	0	0