Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T26,T27
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T26,T27,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T26,T27,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T26,T27,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T26,T27
1	0	Covered	T18,T27,T8
1	1	Covered	T26,T27,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T8
0	1	Covered	T26,T47,T79
1	0	Covered	T27,T47,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T45,T46
0	1	Covered	T8,T48,T81
1	0	Covered	T104

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T45,T46
1	-	Covered	T8,T48,T81

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T27,T8
DetectSt	168	Covered	T26,T27,T8
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T8,T45,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T26,T27,T8
DebounceSt->IdleSt	163	Covered	T270,T271,T61
DetectSt->IdleSt	186	Covered	T26,T27,T47
DetectSt->StableSt	191	Covered	T8,T45,T46
IdleSt->DebounceSt	148	Covered	T26,T27,T8
StableSt->IdleSt	206	Covered	T8,T48,T81

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T8
0	1	Covered	T26,T27,T8
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T8
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T26,T27,T8
IdleSt	0	-	-	-	-	-	-	Covered	T18,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T102
DebounceSt	-	0	1	1	-	-	-	Covered	T26,T27,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T270,T271,T61
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T27,T8
DetectSt	-	-	-	-	1	-	-	Covered	T26,T27,T47
DetectSt	-	-	-	-	0	1	-	Covered	T8,T45,T46
DetectSt	-	-	-	-	0	0	-	Covered	T26,T27,T8
StableSt	-	-	-	-	-	-	1	Covered	T8,T48,T81
StableSt	-	-	-	-	-	-	0	Covered	T8,T45,T46
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	3011	0	0
CntIncr_A	6481552	99055	0	0
CntNoWrap_A	6481552	5862723	0	0
DetectStDropOut_A	6481552	418	0	0
DetectedOut_A	6481552	65822	0	0
DetectedPulseOut_A	6481552	838	0	0
DisabledIdleSt_A	6481552	5429170	0	0
DisabledNoDetection_A	6481552	5431266	0	0
EnterDebounceSt_A	6481552	1529	0	0
EnterDetectSt_A	6481552	1483	0	0
EnterStableSt_A	6481552	838	0	0
PulseIsPulse_A	6481552	838	0	0
StayInStableSt	6481552	64891	0	0
gen_high_event_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_high_level_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	738	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	3011	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	26	0	0
T23	9472	0	0	0
T26	5021	30	0	0
T27	12374	6	0	0
T31	0	50	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	60	0	0
T48	0	16	0	0
T60	424	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T79	0	10	0	0
T80	0	30	0	0
T97	411	0	0	0
T115	432	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	99055	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	559	0	0
T23	9472	0	0	0
T26	5021	711	0	0
T27	12374	119	0	0
T31	0	3212	0	0
T45	0	21	0	0
T46	0	21	0	0
T47	0	1554	0	0
T48	0	664	0	0
T60	424	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T79	0	332	0	0
T80	0	693	0	0
T97	411	0	0	0
T115	432	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5862723	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	418	0	0
T6	3381	0	0	0
T7	767	0	0	0
T23	9472	0	0	0
T26	5021	15	0	0
T27	12374	0	0	0
T31	0	14	0	0
T47	0	6	0	0
T60	424	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T79	0	3	0	0
T80	0	15	0	0
T97	411	0	0	0
T115	432	0	0	0
T119	0	12	0	0
T120	0	2	0	0
T121	0	11	0	0
T122	0	10	0	0
T272	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	65822	0	0
T8	12632	308	0	0
T9	953	0	0	0
T10	30263	0	0	0
T11	1939	0	0	0
T12	23039	0	0	0
T25	661	0	0	0
T45	518	92	0	0
T46	0	83	0	0
T48	0	502	0	0
T64	495	0	0	0
T81	0	1367	0	0
T98	402	0	0	0
T104	0	7	0	0
T144	404	0	0	0
T148	0	592	0	0
T186	0	34	0	0
T241	0	1173	0	0
T273	0	2255	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	838	0	0
T8	12632	13	0	0
T9	953	0	0	0
T10	30263	0	0	0
T11	1939	0	0	0
T12	23039	0	0	0
T25	661	0	0	0
T45	518	1	0	0
T46	0	1	0	0
T48	0	8	0	0
T64	495	0	0	0
T81	0	23	0	0
T98	402	0	0	0
T104	0	7	0	0
T144	404	0	0	0
T148	0	12	0	0
T186	0	2	0	0
T241	0	8	0	0
T273	0	27	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5429170	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5431266	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	1529	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	13	0	0
T23	9472	0	0	0
T26	5021	15	0	0
T27	12374	3	0	0
T31	0	25	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	30	0	0
T48	0	8	0	0
T60	424	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T79	0	5	0	0
T80	0	15	0	0
T97	411	0	0	0
T115	432	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	1483	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	13	0	0
T23	9472	0	0	0
T26	5021	15	0	0
T27	12374	3	0	0
T31	0	25	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	30	0	0
T48	0	8	0	0
T60	424	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T79	0	5	0	0
T80	0	15	0	0
T97	411	0	0	0
T115	432	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	838	0	0
T8	12632	13	0	0
T9	953	0	0	0
T10	30263	0	0	0
T11	1939	0	0	0
T12	23039	0	0	0
T25	661	0	0	0
T45	518	1	0	0
T46	0	1	0	0
T48	0	8	0	0
T64	495	0	0	0
T81	0	23	0	0
T98	402	0	0	0
T104	0	7	0	0
T144	404	0	0	0
T148	0	12	0	0
T186	0	2	0	0
T241	0	8	0	0
T273	0	27	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	838	0	0
T8	12632	13	0	0
T9	953	0	0	0
T10	30263	0	0	0
T11	1939	0	0	0
T12	23039	0	0	0
T25	661	0	0	0
T45	518	1	0	0
T46	0	1	0	0
T48	0	8	0	0
T64	495	0	0	0
T81	0	23	0	0
T98	402	0	0	0
T104	0	7	0	0
T144	404	0	0	0
T148	0	12	0	0
T186	0	2	0	0
T241	0	8	0	0
T273	0	27	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	64891	0	0
T8	12632	293	0	0
T9	953	0	0	0
T10	30263	0	0	0
T11	1939	0	0	0
T12	23039	0	0	0
T25	661	0	0	0
T45	518	90	0	0
T46	0	81	0	0
T48	0	493	0	0
T64	495	0	0	0
T81	0	1342	0	0
T98	402	0	0	0
T144	404	0	0	0
T148	0	580	0	0
T186	0	32	0	0
T241	0	1163	0	0
T273	0	2227	0	0
T274	0	2462	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	738	0	0
T8	12632	11	0	0
T9	953	0	0	0
T10	30263	0	0	0
T11	1939	0	0	0
T12	23039	0	0	0
T25	661	0	0	0
T45	518	0	0	0
T48	0	7	0	0
T64	495	0	0	0
T81	0	21	0	0
T98	402	0	0	0
T144	404	0	0	0
T148	0	12	0	0
T186	0	2	0	0
T241	0	6	0	0
T273	0	26	0	0
T274	0	9	0	0
T275	0	9	0	0
T276	0	23	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T18,T28
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T18,T28
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T28,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T3,T28,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T28,T6
1	0	Covered	T3,T18,T26
1	1	Covered	T3,T28,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T8
0	1	Covered	T117,T118,T123
1	0	Covered	T61,T102

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T8
0	1	Covered	T3,T6,T8
1	0	Covered	T103,T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T8
1	-	Covered	T3,T6,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T28,T6
DetectSt	168	Covered	T3,T6,T8
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T3,T6,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T8
DebounceSt->IdleSt	163	Covered	T28,T12,T49
DetectSt->IdleSt	186	Covered	T117,T118,T123
DetectSt->StableSt	191	Covered	T3,T6,T8
IdleSt->DebounceSt	148	Covered	T3,T28,T6
StableSt->IdleSt	206	Covered	T3,T6,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T28,T6
0	1	Covered	T3,T28,T6
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T8
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T28,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T102
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T12,T49
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T28,T6
DetectSt	-	-	-	-	1	-	-	Covered	T117,T118,T123
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T8
DetectSt	-	-	-	-	0	0	-	Covered	T3,T6,T8
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T8
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	955	0	0
CntIncr_A	6481552	47768	0	0
CntNoWrap_A	6481552	5864779	0	0
DetectStDropOut_A	6481552	73	0	0
DetectedOut_A	6481552	14350	0	0
DetectedPulseOut_A	6481552	358	0	0
DisabledIdleSt_A	6481552	5478298	0	0
DisabledNoDetection_A	6481552	5479796	0	0
EnterDebounceSt_A	6481552	520	0	0
EnterDetectSt_A	6481552	435	0	0
EnterStableSt_A	6481552	358	0	0
PulseIsPulse_A	6481552	358	0	0
StayInStableSt	6481552	13960	0	0
gen_high_level_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	320	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	955	0	0
T3	298636	2	0	0
T6	3381	2	0	0
T8	0	2	0	0
T10	0	2	0	0
T12	0	14	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	1	0	0
T45	0	2	0	0
T49	0	7	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T63	0	9	0	0
T101	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	47768	0	0
T3	298636	25	0	0
T6	3381	25	0	0
T8	0	51	0	0
T10	0	55	0	0
T12	0	798	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	20	0	0
T45	0	25	0	0
T49	0	276	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T63	0	458	0	0
T101	0	1221	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5864779	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292110	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	73	0	0
T40	557	0	0	0
T69	492	0	0	0
T81	14576	0	0	0
T82	1799	0	0	0
T117	11712	2	0	0
T118	24325	10	0	0
T123	0	3	0	0
T124	0	2	0	0
T125	0	5	0	0
T126	0	13	0	0
T127	0	2	0	0
T128	0	4	0	0
T129	0	11	0	0
T130	0	7	0	0
T134	524	0	0	0
T135	715	0	0	0
T136	2843	0	0	0
T137	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	14350	0	0
T3	298636	3	0	0
T6	3381	4	0	0
T8	0	67	0	0
T10	0	33	0	0
T12	0	272	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T45	0	4	0	0
T49	0	15	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T63	0	24	0	0
T66	0	176	0	0
T101	0	519	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	358	0	0
T3	298636	1	0	0
T6	3381	1	0	0
T8	0	1	0	0
T10	0	1	0	0
T12	0	6	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T45	0	1	0	0
T49	0	3	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T63	0	4	0	0
T66	0	2	0	0
T101	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5478298	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292034	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5479796	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292048	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	520	0	0
T3	298636	1	0	0
T6	3381	1	0	0
T8	0	1	0	0
T10	0	1	0	0
T12	0	8	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	1	0	0
T45	0	1	0	0
T49	0	4	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T63	0	5	0	0
T101	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	435	0	0
T3	298636	1	0	0
T6	3381	1	0	0
T8	0	1	0	0
T10	0	1	0	0
T12	0	6	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T45	0	1	0	0
T49	0	3	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T63	0	4	0	0
T66	0	2	0	0
T101	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	358	0	0
T3	298636	1	0	0
T6	3381	1	0	0
T8	0	1	0	0
T10	0	1	0	0
T12	0	6	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T45	0	1	0	0
T49	0	3	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T63	0	4	0	0
T66	0	2	0	0
T101	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	358	0	0
T3	298636	1	0	0
T6	3381	1	0	0
T8	0	1	0	0
T10	0	1	0	0
T12	0	6	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T45	0	1	0	0
T49	0	3	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T63	0	4	0	0
T66	0	2	0	0
T101	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	13960	0	0
T3	298636	2	0	0
T6	3381	3	0	0
T8	0	66	0	0
T10	0	32	0	0
T12	0	266	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T45	0	3	0	0
T49	0	12	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T63	0	20	0	0
T66	0	174	0	0
T101	0	508	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	320	0	0
T3	298636	1	0	0
T6	3381	1	0	0
T8	0	1	0	0
T10	0	1	0	0
T12	0	6	0	0
T18	11652	0	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T45	0	1	0	0
T49	0	3	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T63	0	4	0	0
T66	0	2	0	0
T101	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T26,T27
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T18,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T18,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T18,T26,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T26,T27
1	0	Covered	T18,T27,T8
1	1	Covered	T18,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T26,T27
0	1	Covered	T18,T26,T79
1	0	Covered	T18,T27,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T47,T31
0	1	Covered	T8,T47,T31
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T47,T31
1	-	Covered	T8,T47,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T26,T27
DetectSt	168	Covered	T18,T26,T27
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T8,T47,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T26,T27
DebounceSt->IdleSt	163	Covered	T270,T271,T61
DetectSt->IdleSt	186	Covered	T18,T26,T27
DetectSt->StableSt	191	Covered	T8,T47,T31
IdleSt->DebounceSt	148	Covered	T18,T26,T27
StableSt->IdleSt	206	Covered	T8,T47,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T26,T27
0	1	Covered	T18,T26,T27
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T26,T27
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T18,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T18,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T102
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T26,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T270,T271,T61
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T18,T26,T27
DetectSt	-	-	-	-	0	1	-	Covered	T8,T47,T31
DetectSt	-	-	-	-	0	0	-	Covered	T18,T26,T27
StableSt	-	-	-	-	-	-	1	Covered	T8,T47,T31
StableSt	-	-	-	-	-	-	0	Covered	T8,T47,T31
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	3081	0	0
CntIncr_A	6481552	98967	0	0
CntNoWrap_A	6481552	5862653	0	0
DetectStDropOut_A	6481552	440	0	0
DetectedOut_A	6481552	67927	0	0
DetectedPulseOut_A	6481552	849	0	0
DisabledIdleSt_A	6481552	5428873	0	0
DisabledNoDetection_A	6481552	5430960	0	0
EnterDebounceSt_A	6481552	1573	0	0
EnterDetectSt_A	6481552	1510	0	0
EnterStableSt_A	6481552	849	0	0
PulseIsPulse_A	6481552	849	0	0
StayInStableSt	6481552	66976	0	0
gen_high_event_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_high_level_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	745	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	3081	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	60	0	0
T18	11652	62	0	0
T22	495	0	0	0
T26	5021	14	0	0
T27	0	16	0	0
T28	453	0	0	0
T31	0	32	0	0
T47	0	50	0	0
T48	0	44	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T79	0	50	0	0
T80	0	18	0	0
T81	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	98967	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	900	0	0
T18	11652	1961	0	0
T22	495	0	0	0
T26	5021	331	0	0
T27	0	317	0	0
T28	453	0	0	0
T31	0	1168	0	0
T47	0	1175	0	0
T48	0	1716	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T79	0	1691	0	0
T80	0	408	0	0
T81	0	1950	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5862653	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	440	0	0
T6	3381	0	0	0
T7	767	0	0	0
T18	11652	22	0	0
T22	495	0	0	0
T26	5021	7	0	0
T28	453	0	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T79	0	13	0	0
T80	0	9	0	0
T119	0	23	0	0
T120	0	8	0	0
T121	0	27	0	0
T122	0	20	0	0
T275	0	15	0	0
T277	0	29	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	67927	0	0
T8	12632	1618	0	0
T9	953	0	0	0
T10	30263	0	0	0
T11	1939	0	0	0
T12	23039	0	0	0
T25	661	0	0	0
T31	0	2199	0	0
T45	518	0	0	0
T47	0	1528	0	0
T48	0	1182	0	0
T64	495	0	0	0
T81	0	942	0	0
T98	402	0	0	0
T144	404	0	0	0
T148	0	2498	0	0
T186	0	477	0	0
T241	0	138	0	0
T273	0	265	0	0
T274	0	2673	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	849	0	0
T8	12632	30	0	0
T9	953	0	0	0
T10	30263	0	0	0
T11	1939	0	0	0
T12	23039	0	0	0
T25	661	0	0	0
T31	0	16	0	0
T45	518	0	0	0
T47	0	25	0	0
T48	0	22	0	0
T64	495	0	0	0
T81	0	25	0	0
T98	402	0	0	0
T144	404	0	0	0
T148	0	21	0	0
T186	0	14	0	0
T241	0	4	0	0
T273	0	13	0	0
T274	0	21	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5428873	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5430960	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	1573	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	30	0	0
T18	11652	31	0	0
T22	495	0	0	0
T26	5021	7	0	0
T27	0	8	0	0
T28	453	0	0	0
T31	0	16	0	0
T47	0	25	0	0
T48	0	22	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T79	0	25	0	0
T80	0	9	0	0
T81	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	1510	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	30	0	0
T18	11652	31	0	0
T22	495	0	0	0
T26	5021	7	0	0
T27	0	8	0	0
T28	453	0	0	0
T31	0	16	0	0
T47	0	25	0	0
T48	0	22	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T79	0	25	0	0
T80	0	9	0	0
T81	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	849	0	0
T8	12632	30	0	0
T9	953	0	0	0
T10	30263	0	0	0
T11	1939	0	0	0
T12	23039	0	0	0
T25	661	0	0	0
T31	0	16	0	0
T45	518	0	0	0
T47	0	25	0	0
T48	0	22	0	0
T64	495	0	0	0
T81	0	25	0	0
T98	402	0	0	0
T144	404	0	0	0
T148	0	21	0	0
T186	0	14	0	0
T241	0	4	0	0
T273	0	13	0	0
T274	0	21	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	849	0	0
T8	12632	30	0	0
T9	953	0	0	0
T10	30263	0	0	0
T11	1939	0	0	0
T12	23039	0	0	0
T25	661	0	0	0
T31	0	16	0	0
T45	518	0	0	0
T47	0	25	0	0
T48	0	22	0	0
T64	495	0	0	0
T81	0	25	0	0
T98	402	0	0	0
T144	404	0	0	0
T148	0	21	0	0
T186	0	14	0	0
T241	0	4	0	0
T273	0	13	0	0
T274	0	21	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	66976	0	0
T8	12632	1586	0	0
T9	953	0	0	0
T10	30263	0	0	0
T11	1939	0	0	0
T12	23039	0	0	0
T25	661	0	0	0
T31	0	2174	0	0
T45	518	0	0	0
T47	0	1503	0	0
T48	0	1159	0	0
T64	495	0	0	0
T81	0	915	0	0
T98	402	0	0	0
T144	404	0	0	0
T148	0	2474	0	0
T186	0	462	0	0
T241	0	134	0	0
T273	0	251	0	0
T274	0	2649	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	745	0	0
T8	12632	28	0	0
T9	953	0	0	0
T10	30263	0	0	0
T11	1939	0	0	0
T12	23039	0	0	0
T25	661	0	0	0
T31	0	7	0	0
T45	518	0	0	0
T47	0	25	0	0
T48	0	21	0	0
T64	495	0	0	0
T81	0	23	0	0
T98	402	0	0	0
T144	404	0	0	0
T148	0	18	0	0
T186	0	13	0	0
T241	0	4	0	0
T273	0	12	0	0
T274	0	18	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T26,T27
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T26,T27
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T8,T10,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T8,T10,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T8,T10,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T8,T10
1	0	Covered	T3,T18,T26
1	1	Covered	T8,T10,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T12
0	1	Covered	T63,T33,T278
1	0	Covered	T61,T102

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T12
0	1	Covered	T8,T10,T12
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T10,T12
1	-	Covered	T8,T10,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T10,T12
DetectSt	168	Covered	T8,T10,T12
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T8,T10,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T10,T12
DebounceSt->IdleSt	163	Covered	T8,T49,T279
DetectSt->IdleSt	186	Covered	T63,T33,T278
DetectSt->StableSt	191	Covered	T8,T10,T12
IdleSt->DebounceSt	148	Covered	T8,T10,T12
StableSt->IdleSt	206	Covered	T8,T10,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T10,T12
0	1	Covered	T8,T10,T12
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T12
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T10,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T102
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T10,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T49,T279
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T10,T12
DetectSt	-	-	-	-	1	-	-	Covered	T63,T33,T278
DetectSt	-	-	-	-	0	1	-	Covered	T8,T10,T12
DetectSt	-	-	-	-	0	0	-	Covered	T8,T10,T12
StableSt	-	-	-	-	-	-	1	Covered	T8,T10,T12
StableSt	-	-	-	-	-	-	0	Covered	T8,T10,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	874	0	0
CntIncr_A	6481552	47117	0	0
CntNoWrap_A	6481552	5864860	0	0
DetectStDropOut_A	6481552	68	0	0
DetectedOut_A	6481552	14569	0	0
DetectedPulseOut_A	6481552	341	0	0
DisabledIdleSt_A	6481552	5470518	0	0
DisabledNoDetection_A	6481552	5472061	0	0
EnterDebounceSt_A	6481552	463	0	0
EnterDetectSt_A	6481552	412	0	0
EnterStableSt_A	6481552	341	0	0
PulseIsPulse_A	6481552	341	0	0
StayInStableSt	6481552	14202	0	0
gen_high_level_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	312	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	874	0	0
T8	12632	7	0	0
T9	953	0	0	0
T10	30263	14	0	0
T11	1939	0	0	0
T12	23039	6	0	0
T25	661	0	0	0
T31	0	8	0	0
T32	0	2	0	0
T33	0	8	0	0
T45	518	0	0	0
T49	0	3	0	0
T63	0	4	0	0
T64	495	0	0	0
T66	0	6	0	0
T98	402	0	0	0
T144	404	0	0	0
T279	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	47117	0	0
T8	12632	157	0	0
T9	953	0	0	0
T10	30263	511	0	0
T11	1939	0	0	0
T12	23039	315	0	0
T25	661	0	0	0
T31	0	244	0	0
T32	0	170	0	0
T33	0	603	0	0
T45	518	0	0	0
T49	0	80	0	0
T63	0	228	0	0
T64	495	0	0	0
T66	0	462	0	0
T98	402	0	0	0
T144	404	0	0	0
T279	0	43	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5864860	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	68	0	0
T24	492	0	0	0
T33	0	4	0	0
T43	545	0	0	0
T47	6802	0	0	0
T50	2645	0	0	0
T51	661	0	0	0
T63	18154	2	0	0
T65	551	0	0	0
T77	531	0	0	0
T126	0	6	0	0
T131	402	0	0	0
T167	0	3	0	0
T183	402	0	0	0
T278	0	13	0	0
T280	0	2	0	0
T281	0	3	0	0
T282	0	2	0	0
T283	0	5	0	0
T284	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	14569	0	0
T8	12632	207	0	0
T9	953	0	0	0
T10	30263	111	0	0
T11	1939	0	0	0
T12	23039	191	0	0
T25	661	0	0	0
T31	0	148	0	0
T32	0	7	0	0
T45	518	0	0	0
T48	0	104	0	0
T49	0	27	0	0
T64	495	0	0	0
T66	0	111	0	0
T81	0	158	0	0
T98	402	0	0	0
T117	0	12	0	0
T144	404	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	341	0	0
T8	12632	3	0	0
T9	953	0	0	0
T10	30263	7	0	0
T11	1939	0	0	0
T12	23039	3	0	0
T25	661	0	0	0
T31	0	4	0	0
T32	0	1	0	0
T45	518	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T64	495	0	0	0
T66	0	3	0	0
T81	0	2	0	0
T98	402	0	0	0
T117	0	2	0	0
T144	404	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5470518	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5472061	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	463	0	0
T8	12632	4	0	0
T9	953	0	0	0
T10	30263	7	0	0
T11	1939	0	0	0
T12	23039	3	0	0
T25	661	0	0	0
T31	0	4	0	0
T32	0	1	0	0
T33	0	4	0	0
T45	518	0	0	0
T49	0	2	0	0
T63	0	2	0	0
T64	495	0	0	0
T66	0	3	0	0
T98	402	0	0	0
T144	404	0	0	0
T279	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	412	0	0
T8	12632	3	0	0
T9	953	0	0	0
T10	30263	7	0	0
T11	1939	0	0	0
T12	23039	3	0	0
T25	661	0	0	0
T31	0	4	0	0
T32	0	1	0	0
T33	0	4	0	0
T45	518	0	0	0
T49	0	1	0	0
T63	0	2	0	0
T64	495	0	0	0
T66	0	3	0	0
T98	402	0	0	0
T144	404	0	0	0
T278	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	341	0	0
T8	12632	3	0	0
T9	953	0	0	0
T10	30263	7	0	0
T11	1939	0	0	0
T12	23039	3	0	0
T25	661	0	0	0
T31	0	4	0	0
T32	0	1	0	0
T45	518	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T64	495	0	0	0
T66	0	3	0	0
T81	0	2	0	0
T98	402	0	0	0
T117	0	2	0	0
T144	404	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	341	0	0
T8	12632	3	0	0
T9	953	0	0	0
T10	30263	7	0	0
T11	1939	0	0	0
T12	23039	3	0	0
T25	661	0	0	0
T31	0	4	0	0
T32	0	1	0	0
T45	518	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T64	495	0	0	0
T66	0	3	0	0
T81	0	2	0	0
T98	402	0	0	0
T117	0	2	0	0
T144	404	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	14202	0	0
T8	12632	204	0	0
T9	953	0	0	0
T10	30263	104	0	0
T11	1939	0	0	0
T12	23039	188	0	0
T25	661	0	0	0
T31	0	144	0	0
T32	0	6	0	0
T45	518	0	0	0
T48	0	102	0	0
T49	0	26	0	0
T64	495	0	0	0
T66	0	108	0	0
T81	0	156	0	0
T98	402	0	0	0
T117	0	10	0	0
T144	404	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	312	0	0
T8	12632	3	0	0
T9	953	0	0	0
T10	30263	7	0	0
T11	1939	0	0	0
T12	23039	3	0	0
T25	661	0	0	0
T31	0	4	0	0
T32	0	1	0	0
T45	518	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T64	495	0	0	0
T66	0	3	0	0
T81	0	2	0	0
T98	402	0	0	0
T117	0	2	0	0
T144	404	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T26,T27
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T18,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T18,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T18,T26,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T26,T27
1	0	Covered	T18,T27,T8
1	1	Covered	T18,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T26,T27
0	1	Covered	T26,T8,T47
1	0	Covered	T27,T8,T47

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T31,T48
0	1	Covered	T18,T31,T48
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T31,T48
1	-	Covered	T18,T31,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T26,T27
DetectSt	168	Covered	T18,T26,T27
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T18,T31,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T26,T27
DebounceSt->IdleSt	163	Covered	T270,T271,T61
DetectSt->IdleSt	186	Covered	T26,T27,T8
DetectSt->StableSt	191	Covered	T18,T31,T48
IdleSt->DebounceSt	148	Covered	T18,T26,T27
StableSt->IdleSt	206	Covered	T18,T31,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T26,T27
0	1	Covered	T18,T26,T27
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T26,T27
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T18,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T18,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T102
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T26,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T270,T271,T61
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T26,T27,T8
DetectSt	-	-	-	-	0	1	-	Covered	T18,T31,T48
DetectSt	-	-	-	-	0	0	-	Covered	T18,T26,T27
StableSt	-	-	-	-	-	-	1	Covered	T18,T31,T48
StableSt	-	-	-	-	-	-	0	Covered	T18,T31,T48
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	3155	0	0
CntIncr_A	6481552	108779	0	0
CntNoWrap_A	6481552	5862579	0	0
DetectStDropOut_A	6481552	381	0	0
DetectedOut_A	6481552	77581	0	0
DetectedPulseOut_A	6481552	946	0	0
DisabledIdleSt_A	6481552	5419242	0	0
DisabledNoDetection_A	6481552	5421340	0	0
EnterDebounceSt_A	6481552	1599	0	0
EnterDetectSt_A	6481552	1556	0	0
EnterStableSt_A	6481552	946	0	0
PulseIsPulse_A	6481552	946	0	0
StayInStableSt	6481552	76543	0	0
gen_high_event_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_high_level_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	853	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	3155	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	36	0	0
T18	11652	26	0	0
T22	495	0	0	0
T26	5021	42	0	0
T27	0	30	0	0
T28	453	0	0	0
T31	0	16	0	0
T47	0	66	0	0
T48	0	22	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T79	0	50	0	0
T80	0	8	0	0
T81	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	108779	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	806	0	0
T18	11652	767	0	0
T22	495	0	0	0
T26	5021	1005	0	0
T27	0	596	0	0
T28	453	0	0	0
T31	0	520	0	0
T47	0	1712	0	0
T48	0	836	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T79	0	1691	0	0
T80	0	180	0	0
T81	0	1050	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5862579	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	381	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	3	0	0
T23	9472	0	0	0
T26	5021	21	0	0
T27	12374	0	0	0
T47	0	7	0	0
T60	424	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T79	0	13	0	0
T80	0	4	0	0
T97	411	0	0	0
T115	432	0	0	0
T119	0	23	0	0
T120	0	26	0	0
T121	0	11	0	0
T122	0	8	0	0
T285	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	77581	0	0
T6	3381	0	0	0
T7	767	0	0	0
T18	11652	1871	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T31	0	1366	0	0
T48	0	1043	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T81	0	912	0	0
T104	0	1411	0	0
T148	0	969	0	0
T186	0	955	0	0
T241	0	2768	0	0
T272	0	2028	0	0
T273	0	392	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	946	0	0
T6	3381	0	0	0
T7	767	0	0	0
T18	11652	13	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T31	0	8	0	0
T48	0	11	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T81	0	14	0	0
T104	0	28	0	0
T148	0	15	0	0
T186	0	7	0	0
T241	0	22	0	0
T272	0	28	0	0
T273	0	14	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5419242	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5421340	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	1599	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	18	0	0
T18	11652	13	0	0
T22	495	0	0	0
T26	5021	21	0	0
T27	0	15	0	0
T28	453	0	0	0
T31	0	8	0	0
T47	0	33	0	0
T48	0	11	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T79	0	25	0	0
T80	0	4	0	0
T81	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	1556	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	18	0	0
T18	11652	13	0	0
T22	495	0	0	0
T26	5021	21	0	0
T27	0	15	0	0
T28	453	0	0	0
T31	0	8	0	0
T47	0	33	0	0
T48	0	11	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T79	0	25	0	0
T80	0	4	0	0
T81	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	946	0	0
T6	3381	0	0	0
T7	767	0	0	0
T18	11652	13	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T31	0	8	0	0
T48	0	11	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T81	0	14	0	0
T104	0	28	0	0
T148	0	15	0	0
T186	0	7	0	0
T241	0	22	0	0
T272	0	28	0	0
T273	0	14	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	946	0	0
T6	3381	0	0	0
T7	767	0	0	0
T18	11652	13	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T31	0	8	0	0
T48	0	11	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T81	0	14	0	0
T104	0	28	0	0
T148	0	15	0	0
T186	0	7	0	0
T241	0	22	0	0
T272	0	28	0	0
T273	0	14	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	76543	0	0
T6	3381	0	0	0
T7	767	0	0	0
T18	11652	1856	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T31	0	1353	0	0
T48	0	1032	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T81	0	896	0	0
T104	0	1381	0	0
T148	0	954	0	0
T186	0	947	0	0
T241	0	2743	0	0
T272	0	1999	0	0
T273	0	377	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	853	0	0
T6	3381	0	0	0
T7	767	0	0	0
T18	11652	11	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T31	0	3	0	0
T48	0	11	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T81	0	12	0	0
T104	0	26	0	0
T148	0	15	0	0
T186	0	6	0	0
T241	0	19	0	0
T272	0	27	0	0
T273	0	13	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T26,T27
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T26,T27
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T18,T10,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T18,T10,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T18,T10,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T10,T12
1	0	Covered	T3,T18,T26
1	1	Covered	T18,T10,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T10,T12
0	1	Covered	T63,T101,T32
1	0	Covered	T61,T102

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T10,T12
0	1	Covered	T10,T12,T49
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T10,T12
1	-	Covered	T10,T12,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T10,T12
DetectSt	168	Covered	T18,T10,T12
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T18,T10,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T10,T12
DebounceSt->IdleSt	163	Covered	T49,T278,T44
DetectSt->IdleSt	186	Covered	T63,T101,T32
DetectSt->StableSt	191	Covered	T18,T10,T12
IdleSt->DebounceSt	148	Covered	T18,T10,T12
StableSt->IdleSt	206	Covered	T18,T10,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T10,T12
0	1	Covered	T18,T10,T12
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T10,T12
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T10,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T102
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T10,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T278,T44
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T10,T12
DetectSt	-	-	-	-	1	-	-	Covered	T63,T101,T32
DetectSt	-	-	-	-	0	1	-	Covered	T18,T10,T12
DetectSt	-	-	-	-	0	0	-	Covered	T18,T10,T12
StableSt	-	-	-	-	-	-	1	Covered	T10,T12,T49
StableSt	-	-	-	-	-	-	0	Covered	T18,T10,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	921	0	0
CntIncr_A	6481552	55282	0	0
CntNoWrap_A	6481552	5864813	0	0
DetectStDropOut_A	6481552	66	0	0
DetectedOut_A	6481552	15318	0	0
DetectedPulseOut_A	6481552	366	0	0
DisabledIdleSt_A	6481552	5468020	0	0
DisabledNoDetection_A	6481552	5469583	0	0
EnterDebounceSt_A	6481552	486	0	0
EnterDetectSt_A	6481552	436	0	0
EnterStableSt_A	6481552	366	0	0
PulseIsPulse_A	6481552	366	0	0
StayInStableSt	6481552	14936	0	0
gen_high_level_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	348	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	921	0	0
T6	3381	0	0	0
T7	767	0	0	0
T10	0	10	0	0
T12	0	6	0	0
T18	11652	4	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T31	0	10	0	0
T33	0	20	0	0
T49	0	24	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T63	0	2	0	0
T66	0	2	0	0
T101	0	12	0	0
T279	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	55282	0	0
T6	3381	0	0	0
T7	767	0	0	0
T10	0	230	0	0
T12	0	390	0	0
T18	11652	114	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T31	0	250	0	0
T33	0	1150	0	0
T49	0	602	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T63	0	114	0	0
T66	0	139	0	0
T101	0	944	0	0
T279	0	178	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5864813	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	66	0	0
T24	492	0	0	0
T32	0	1	0	0
T43	545	0	0	0
T44	0	4	0	0
T47	6802	0	0	0
T50	2645	0	0	0
T51	661	0	0	0
T63	18154	1	0	0
T65	551	0	0	0
T77	531	0	0	0
T101	0	6	0	0
T110	0	6	0	0
T123	0	5	0	0
T131	402	0	0	0
T183	402	0	0	0
T198	0	5	0	0
T261	0	6	0	0
T282	0	6	0	0
T286	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	15318	0	0
T6	3381	0	0	0
T7	767	0	0	0
T10	0	213	0	0
T12	0	116	0	0
T18	11652	177	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T31	0	242	0	0
T33	0	354	0	0
T48	0	71	0	0
T49	0	456	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T66	0	52	0	0
T278	0	134	0	0
T279	0	96	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	366	0	0
T6	3381	0	0	0
T7	767	0	0	0
T10	0	5	0	0
T12	0	3	0	0
T18	11652	2	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T31	0	5	0	0
T33	0	10	0	0
T48	0	1	0	0
T49	0	11	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T66	0	1	0	0
T278	0	2	0	0
T279	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5468020	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5469583	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	486	0	0
T6	3381	0	0	0
T7	767	0	0	0
T10	0	5	0	0
T12	0	3	0	0
T18	11652	2	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T31	0	5	0	0
T33	0	10	0	0
T49	0	13	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T63	0	1	0	0
T66	0	1	0	0
T101	0	6	0	0
T279	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	436	0	0
T6	3381	0	0	0
T7	767	0	0	0
T10	0	5	0	0
T12	0	3	0	0
T18	11652	2	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T31	0	5	0	0
T33	0	10	0	0
T49	0	11	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T63	0	1	0	0
T66	0	1	0	0
T101	0	6	0	0
T279	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	366	0	0
T6	3381	0	0	0
T7	767	0	0	0
T10	0	5	0	0
T12	0	3	0	0
T18	11652	2	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T31	0	5	0	0
T33	0	10	0	0
T48	0	1	0	0
T49	0	11	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T66	0	1	0	0
T278	0	2	0	0
T279	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	366	0	0
T6	3381	0	0	0
T7	767	0	0	0
T10	0	5	0	0
T12	0	3	0	0
T18	11652	2	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T31	0	5	0	0
T33	0	10	0	0
T48	0	1	0	0
T49	0	11	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T66	0	1	0	0
T278	0	2	0	0
T279	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	14936	0	0
T6	3381	0	0	0
T7	767	0	0	0
T10	0	208	0	0
T12	0	113	0	0
T18	11652	173	0	0
T22	495	0	0	0
T26	5021	0	0	0
T28	453	0	0	0
T31	0	237	0	0
T33	0	344	0	0
T48	0	70	0	0
T49	0	445	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T66	0	51	0	0
T278	0	132	0	0
T279	0	94	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	348	0	0
T10	30263	5	0	0
T11	1939	0	0	0
T12	23039	3	0	0
T25	661	0	0	0
T31	0	5	0	0
T33	0	10	0	0
T39	2881	0	0	0
T45	518	0	0	0
T48	0	1	0	0
T49	27298	10	0	0
T66	0	1	0	0
T88	8403	0	0	0
T98	402	0	0	0
T117	0	11	0	0
T144	404	0	0	0
T278	0	2	0	0
T279	0	2	0	0