Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T26,T27
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T18,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T18,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T18,T26,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T26,T27
1	0	Covered	T18,T27,T8
1	1	Covered	T18,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T26,T27
0	1	Covered	T26,T80,T119
1	0	Covered	T285,T221,T232

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T27,T8
0	1	Covered	T18,T27,T8
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T27,T8
1	-	Covered	T18,T27,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T26,T27
DetectSt	168	Covered	T18,T26,T27
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T18,T27,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T26,T27
DebounceSt->IdleSt	163	Covered	T270,T271,T61
DetectSt->IdleSt	186	Covered	T26,T80,T119
DetectSt->StableSt	191	Covered	T18,T27,T8
IdleSt->DebounceSt	148	Covered	T18,T26,T27
StableSt->IdleSt	206	Covered	T18,T27,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T26,T27
0	1	Covered	T18,T26,T27
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T26,T27
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T18,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T18,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T102
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T26,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T270,T271,T61
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T26,T80,T119
DetectSt	-	-	-	-	0	1	-	Covered	T18,T27,T8
DetectSt	-	-	-	-	0	0	-	Covered	T18,T26,T27
StableSt	-	-	-	-	-	-	1	Covered	T18,T27,T8
StableSt	-	-	-	-	-	-	0	Covered	T18,T27,T8
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	2732	0	0
CntIncr_A	6481552	86751	0	0
CntNoWrap_A	6481552	5863002	0	0
DetectStDropOut_A	6481552	319	0	0
DetectedOut_A	6481552	71278	0	0
DetectedPulseOut_A	6481552	936	0	0
DisabledIdleSt_A	6481552	5422844	0	0
DisabledNoDetection_A	6481552	5424925	0	0
EnterDebounceSt_A	6481552	1380	0	0
EnterDetectSt_A	6481552	1352	0	0
EnterStableSt_A	6481552	936	0	0
PulseIsPulse_A	6481552	936	0	0
StayInStableSt	6481552	70232	0	0
gen_high_event_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_high_level_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	826	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	2732	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	48	0	0
T18	11652	4	0	0
T22	495	0	0	0
T26	5021	62	0	0
T27	0	58	0	0
T28	453	0	0	0
T31	0	44	0	0
T47	0	50	0	0
T48	0	12	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T79	0	42	0	0
T80	0	12	0	0
T81	0	20	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	86751	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	888	0	0
T18	11652	120	0	0
T22	495	0	0	0
T26	5021	1486	0	0
T27	0	1015	0	0
T28	453	0	0	0
T31	0	1562	0	0
T47	0	1250	0	0
T48	0	468	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T79	0	1365	0	0
T80	0	275	0	0
T81	0	510	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5863002	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	319	0	0
T6	3381	0	0	0
T7	767	0	0	0
T23	9472	0	0	0
T26	5021	31	0	0
T27	12374	0	0	0
T60	424	0	0	0
T75	530	0	0	0
T76	526	0	0	0
T80	0	6	0	0
T97	411	0	0	0
T115	432	0	0	0
T119	0	3	0	0
T120	0	5	0	0
T121	0	9	0	0
T122	0	24	0	0
T221	0	6	0	0
T232	0	9	0	0
T239	0	21	0	0
T277	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	71278	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	992	0	0
T18	11652	10	0	0
T22	495	0	0	0
T26	5021	0	0	0
T27	0	1842	0	0
T28	453	0	0	0
T31	0	3300	0	0
T47	0	250	0	0
T48	0	226	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T79	0	1703	0	0
T81	0	324	0	0
T241	0	1878	0	0
T273	0	52	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	936	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	24	0	0
T18	11652	2	0	0
T22	495	0	0	0
T26	5021	0	0	0
T27	0	29	0	0
T28	453	0	0	0
T31	0	22	0	0
T47	0	25	0	0
T48	0	6	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T79	0	21	0	0
T81	0	10	0	0
T241	0	20	0	0
T273	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5422844	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5424925	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	1380	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	24	0	0
T18	11652	2	0	0
T22	495	0	0	0
T26	5021	31	0	0
T27	0	29	0	0
T28	453	0	0	0
T31	0	22	0	0
T47	0	25	0	0
T48	0	6	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T79	0	21	0	0
T80	0	6	0	0
T81	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	1352	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	24	0	0
T18	11652	2	0	0
T22	495	0	0	0
T26	5021	31	0	0
T27	0	29	0	0
T28	453	0	0	0
T31	0	22	0	0
T47	0	25	0	0
T48	0	6	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T79	0	21	0	0
T80	0	6	0	0
T81	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	936	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	24	0	0
T18	11652	2	0	0
T22	495	0	0	0
T26	5021	0	0	0
T27	0	29	0	0
T28	453	0	0	0
T31	0	22	0	0
T47	0	25	0	0
T48	0	6	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T79	0	21	0	0
T81	0	10	0	0
T241	0	20	0	0
T273	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	936	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	24	0	0
T18	11652	2	0	0
T22	495	0	0	0
T26	5021	0	0	0
T27	0	29	0	0
T28	453	0	0	0
T31	0	22	0	0
T47	0	25	0	0
T48	0	6	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T79	0	21	0	0
T81	0	10	0	0
T241	0	20	0	0
T273	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	70232	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	965	0	0
T18	11652	8	0	0
T22	495	0	0	0
T26	5021	0	0	0
T27	0	1810	0	0
T28	453	0	0	0
T31	0	3269	0	0
T47	0	225	0	0
T48	0	220	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T79	0	1682	0	0
T81	0	314	0	0
T241	0	1855	0	0
T273	0	44	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	826	0	0
T6	3381	0	0	0
T7	767	0	0	0
T8	0	21	0	0
T18	11652	2	0	0
T22	495	0	0	0
T26	5021	0	0	0
T27	0	26	0	0
T28	453	0	0	0
T31	0	13	0	0
T47	0	25	0	0
T48	0	6	0	0
T56	426	0	0	0
T57	548	0	0	0
T58	402	0	0	0
T59	502	0	0	0
T79	0	21	0	0
T81	0	10	0	0
T241	0	17	0	0
T273	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T26,T27
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T26,T27
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T27,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T27,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T27,T8
1	0	Covered	T3,T18,T26
1	1	Covered	T27,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T8,T10
0	1	Covered	T44,T287,T281
1	0	Covered	T61,T102

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T8,T10
0	1	Covered	T8,T10,T63
1	0	Covered	T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T8,T10
1	-	Covered	T8,T10,T63

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T8,T10
DetectSt	168	Covered	T27,T8,T10
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T27,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T8,T10
DebounceSt->IdleSt	163	Covered	T10,T279,T117
DetectSt->IdleSt	186	Covered	T44,T287,T281
DetectSt->StableSt	191	Covered	T27,T8,T10
IdleSt->DebounceSt	148	Covered	T27,T8,T10
StableSt->IdleSt	206	Covered	T27,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T27,T8,T10
0	1	Covered	T27,T8,T10
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T8,T10
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T27,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T102
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T279,T117
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T44,T287,T281
DetectSt	-	-	-	-	0	1	-	Covered	T27,T8,T10
DetectSt	-	-	-	-	0	0	-	Covered	T27,T8,T10
StableSt	-	-	-	-	-	-	1	Covered	T8,T10,T63
StableSt	-	-	-	-	-	-	0	Covered	T27,T8,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6481552	825	0	0
CntIncr_A	6481552	43997	0	0
CntNoWrap_A	6481552	5864909	0	0
DetectStDropOut_A	6481552	42	0	0
DetectedOut_A	6481552	15651	0	0
DetectedPulseOut_A	6481552	347	0	0
DisabledIdleSt_A	6481552	5475654	0	0
DisabledNoDetection_A	6481552	5477207	0	0
EnterDebounceSt_A	6481552	434	0	0
EnterDetectSt_A	6481552	392	0	0
EnterStableSt_A	6481552	347	0	0
PulseIsPulse_A	6481552	347	0	0
StayInStableSt	6481552	15269	0	0
gen_high_level_sva.HighLevelEvent_A	6481552	5868014	0	0
gen_not_sticky_sva.StableStDropOut_A	6481552	308	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	825	0	0
T8	12632	4	0	0
T9	953	0	0	0
T10	0	17	0	0
T23	9472	0	0	0
T27	12374	6	0	0
T33	0	10	0	0
T47	0	2	0	0
T63	0	4	0	0
T64	495	0	0	0
T66	0	16	0	0
T75	530	0	0	0
T76	526	0	0	0
T79	0	6	0	0
T97	411	0	0	0
T101	0	2	0	0
T115	432	0	0	0
T116	450	0	0	0
T279	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	43997	0	0
T8	12632	94	0	0
T9	953	0	0	0
T10	0	370	0	0
T23	9472	0	0	0
T27	12374	129	0	0
T33	0	425	0	0
T47	0	72	0	0
T63	0	126	0	0
T64	495	0	0	0
T66	0	992	0	0
T75	530	0	0	0
T76	526	0	0	0
T79	0	183	0	0
T97	411	0	0	0
T101	0	151	0	0
T115	432	0	0	0
T116	450	0	0	0
T279	0	43	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5864909	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	42	0	0
T44	17909	6	0	0
T61	0	1	0	0
T72	494	0	0	0
T104	15917	0	0	0
T106	1429	0	0	0
T121	5320	0	0	0
T122	5620	0	0	0
T127	0	2	0	0
T130	0	3	0	0
T148	16228	0	0	0
T149	436	0	0	0
T150	607	0	0	0
T168	0	3	0	0
T198	0	6	0	0
T206	0	7	0	0
T274	21044	0	0	0
T281	0	5	0	0
T286	0	1	0	0
T287	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	15651	0	0
T8	12632	142	0	0
T9	953	0	0	0
T10	0	350	0	0
T23	9472	0	0	0
T27	12374	239	0	0
T31	0	451	0	0
T33	0	330	0	0
T47	0	75	0	0
T63	0	102	0	0
T64	495	0	0	0
T66	0	544	0	0
T75	530	0	0	0
T76	526	0	0	0
T79	0	448	0	0
T97	411	0	0	0
T101	0	7	0	0
T115	432	0	0	0
T116	450	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	347	0	0
T8	12632	2	0	0
T9	953	0	0	0
T10	0	8	0	0
T23	9472	0	0	0
T27	12374	3	0	0
T31	0	9	0	0
T33	0	5	0	0
T47	0	1	0	0
T63	0	2	0	0
T64	495	0	0	0
T66	0	8	0	0
T75	530	0	0	0
T76	526	0	0	0
T79	0	3	0	0
T97	411	0	0	0
T101	0	1	0	0
T115	432	0	0	0
T116	450	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5475654	0	0
T1	189379	188978	0	0
T2	551	150	0	0
T3	298636	292112	0	0
T4	525	124	0	0
T5	681	280	0	0
T13	526	125	0	0
T14	745	344	0	0
T15	664	263	0	0
T16	4402	1	0	0
T17	521	120	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5477207	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	434	0	0
T8	12632	2	0	0
T9	953	0	0	0
T10	0	9	0	0
T23	9472	0	0	0
T27	12374	3	0	0
T33	0	5	0	0
T47	0	1	0	0
T63	0	2	0	0
T64	495	0	0	0
T66	0	8	0	0
T75	530	0	0	0
T76	526	0	0	0
T79	0	3	0	0
T97	411	0	0	0
T101	0	1	0	0
T115	432	0	0	0
T116	450	0	0	0
T279	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	392	0	0
T8	12632	2	0	0
T9	953	0	0	0
T10	0	8	0	0
T23	9472	0	0	0
T27	12374	3	0	0
T31	0	9	0	0
T33	0	5	0	0
T47	0	1	0	0
T63	0	2	0	0
T64	495	0	0	0
T66	0	8	0	0
T75	530	0	0	0
T76	526	0	0	0
T79	0	3	0	0
T97	411	0	0	0
T101	0	1	0	0
T115	432	0	0	0
T116	450	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	347	0	0
T8	12632	2	0	0
T9	953	0	0	0
T10	0	8	0	0
T23	9472	0	0	0
T27	12374	3	0	0
T31	0	9	0	0
T33	0	5	0	0
T47	0	1	0	0
T63	0	2	0	0
T64	495	0	0	0
T66	0	8	0	0
T75	530	0	0	0
T76	526	0	0	0
T79	0	3	0	0
T97	411	0	0	0
T101	0	1	0	0
T115	432	0	0	0
T116	450	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	347	0	0
T8	12632	2	0	0
T9	953	0	0	0
T10	0	8	0	0
T23	9472	0	0	0
T27	12374	3	0	0
T31	0	9	0	0
T33	0	5	0	0
T47	0	1	0	0
T63	0	2	0	0
T64	495	0	0	0
T66	0	8	0	0
T75	530	0	0	0
T76	526	0	0	0
T79	0	3	0	0
T97	411	0	0	0
T101	0	1	0	0
T115	432	0	0	0
T116	450	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	15269	0	0
T8	12632	140	0	0
T9	953	0	0	0
T10	0	342	0	0
T23	9472	0	0	0
T27	12374	233	0	0
T31	0	442	0	0
T33	0	325	0	0
T47	0	74	0	0
T63	0	100	0	0
T64	495	0	0	0
T66	0	536	0	0
T75	530	0	0	0
T76	526	0	0	0
T79	0	445	0	0
T97	411	0	0	0
T101	0	6	0	0
T115	432	0	0	0
T116	450	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	5868014	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6481552	308	0	0
T8	12632	2	0	0
T9	953	0	0	0
T10	30263	8	0	0
T11	1939	0	0	0
T12	23039	0	0	0
T25	661	0	0	0
T31	0	9	0	0
T32	0	3	0	0
T33	0	5	0	0
T45	518	0	0	0
T47	0	1	0	0
T63	0	2	0	0
T64	495	0	0	0
T66	0	8	0	0
T79	0	2	0	0
T98	402	0	0	0
T101	0	1	0	0
T144	404	0	0	0