Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1150178757	10978	0	0
auto_block_debounce_ctl_rd_A	1150178757	2366	0	0
auto_block_out_ctl_rd_A	1150178757	3121	0	0
com_det_ctl_0_rd_A	1150178757	4533	0	0
com_det_ctl_1_rd_A	1150178757	4969	0	0
com_det_ctl_2_rd_A	1150178757	4915	0	0
com_det_ctl_3_rd_A	1150178757	4708	0	0
com_out_ctl_0_rd_A	1150178757	5426	0	0
com_out_ctl_1_rd_A	1150178757	5685	0	0
com_out_ctl_2_rd_A	1150178757	5497	0	0
com_out_ctl_3_rd_A	1150178757	5871	0	0
com_pre_det_ctl_0_rd_A	1150178757	1836	0	0
com_pre_det_ctl_1_rd_A	1150178757	1858	0	0
com_pre_det_ctl_2_rd_A	1150178757	1834	0	0
com_pre_det_ctl_3_rd_A	1150178757	1690	0	0
com_pre_sel_ctl_0_rd_A	1150178757	5551	0	0
com_pre_sel_ctl_1_rd_A	1150178757	5695	0	0
com_pre_sel_ctl_2_rd_A	1150178757	5623	0	0
com_pre_sel_ctl_3_rd_A	1150178757	6008	0	0
com_sel_ctl_0_rd_A	1150178757	5741	0	0
com_sel_ctl_1_rd_A	1150178757	5832	0	0
com_sel_ctl_2_rd_A	1150178757	5836	0	0
com_sel_ctl_3_rd_A	1150178757	5527	0	0
ec_rst_ctl_rd_A	1150178757	3321	0	0
intr_enable_rd_A	1150178757	2534	0	0
key_intr_ctl_rd_A	1150178757	5285	0	0
key_intr_debounce_ctl_rd_A	1150178757	1941	0	0
key_invert_ctl_rd_A	1150178757	5909	0	0
pin_allowed_ctl_rd_A	1150178757	8190	0	0
pin_out_ctl_rd_A	1150178757	5745	0	0
pin_out_value_rd_A	1150178757	5913	0	0
regwen_rd_A	1150178757	2080	0	0
ulp_ac_debounce_ctl_rd_A	1150178757	1923	0	0
ulp_ctl_rd_A	1150178757	2000	0	0
ulp_lid_debounce_ctl_rd_A	1150178757	1960	0	0
ulp_pwrb_debounce_ctl_rd_A	1150178757	1964	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	10978	0	0
T3	423384	21	0	0
T6	885350	0	0	0
T18	192275	0	0	0
T22	57038	0	0	0
T23	0	8	0	0
T26	627646	0	0	0
T28	36301	0	0	0
T37	0	8	0	0
T42	0	5	0	0
T44	0	12	0	0
T53	0	8	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T71	0	5	0	0
T73	0	3	0	0
T84	0	19	0	0
T279	0	5	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	2366	0	0
T8	631614	0	0	0
T9	54964	0	0	0
T10	136186	0	0	0
T23	236822	7	0	0
T37	0	2	0	0
T44	0	40	0	0
T55	0	6	0	0
T64	205358	0	0	0
T73	0	25	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T84	0	15	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T199	0	12	0	0
T279	0	8	0	0
T290	0	5	0	0
T291	0	12	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	3121	0	0
T8	631614	0	0	0
T9	54964	0	0	0
T10	136186	0	0	0
T23	236822	34	0	0
T44	0	31	0	0
T55	0	8	0	0
T64	205358	0	0	0
T73	0	22	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T84	0	6	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T151	0	15	0	0
T199	0	14	0	0
T279	0	3	0	0
T290	0	9	0	0
T291	0	14	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	4533	0	0
T8	631614	53	0	0
T9	54964	0	0	0
T10	136186	71	0	0
T23	236822	25	0	0
T32	0	18	0	0
T33	0	81	0	0
T49	0	37	0	0
T63	0	59	0	0
T64	205358	0	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T118	0	77	0	0
T278	0	59	0	0
T279	0	29	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	4969	0	0
T8	631614	56	0	0
T9	54964	0	0	0
T10	136186	56	0	0
T23	236822	15	0	0
T32	0	31	0	0
T33	0	77	0	0
T49	0	46	0	0
T63	0	37	0	0
T64	205358	0	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T118	0	71	0	0
T278	0	71	0	0
T279	0	22	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	4915	0	0
T8	631614	58	0	0
T9	54964	0	0	0
T10	136186	86	0	0
T23	236822	13	0	0
T32	0	70	0	0
T33	0	62	0	0
T49	0	50	0	0
T63	0	52	0	0
T64	205358	0	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T118	0	96	0	0
T278	0	65	0	0
T279	0	36	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	4708	0	0
T8	631614	64	0	0
T9	54964	0	0	0
T10	136186	81	0	0
T23	236822	21	0	0
T32	0	21	0	0
T33	0	102	0	0
T49	0	37	0	0
T63	0	39	0	0
T64	205358	0	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T118	0	63	0	0
T278	0	66	0	0
T279	0	21	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	5426	0	0
T8	631614	57	0	0
T9	54964	0	0	0
T10	136186	74	0	0
T23	236822	18	0	0
T32	0	31	0	0
T33	0	64	0	0
T49	0	36	0	0
T63	0	46	0	0
T64	205358	0	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T118	0	68	0	0
T278	0	79	0	0
T279	0	6	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	5685	0	0
T8	631614	48	0	0
T9	54964	0	0	0
T10	136186	83	0	0
T23	236822	15	0	0
T32	0	32	0	0
T33	0	77	0	0
T49	0	44	0	0
T63	0	58	0	0
T64	205358	0	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T118	0	56	0	0
T278	0	63	0	0
T279	0	35	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	5497	0	0
T8	631614	39	0	0
T9	54964	0	0	0
T10	136186	70	0	0
T23	236822	21	0	0
T32	0	50	0	0
T33	0	63	0	0
T49	0	40	0	0
T63	0	29	0	0
T64	205358	0	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T118	0	77	0	0
T278	0	73	0	0
T279	0	27	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	5871	0	0
T8	631614	39	0	0
T9	54964	0	0	0
T10	136186	69	0	0
T23	236822	21	0	0
T32	0	57	0	0
T33	0	87	0	0
T49	0	56	0	0
T63	0	43	0	0
T64	205358	0	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T118	0	54	0	0
T278	0	72	0	0
T279	0	11	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1836	0	0
T8	631614	0	0	0
T9	54964	0	0	0
T10	136186	0	0	0
T23	236822	3	0	0
T37	0	1	0	0
T44	0	30	0	0
T64	205358	0	0	0
T73	0	11	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T84	0	14	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T151	0	26	0	0
T169	0	16	0	0
T206	0	24	0	0
T209	0	24	0	0
T279	0	17	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1858	0	0
T8	631614	0	0	0
T9	54964	0	0	0
T10	136186	0	0	0
T23	236822	30	0	0
T37	0	10	0	0
T44	0	33	0	0
T64	205358	0	0	0
T73	0	12	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T84	0	6	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T151	0	30	0	0
T168	0	4	0	0
T169	0	14	0	0
T206	0	11	0	0
T279	0	5	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1834	0	0
T8	631614	0	0	0
T9	54964	0	0	0
T10	136186	0	0	0
T23	236822	4	0	0
T37	0	4	0	0
T44	0	40	0	0
T64	205358	0	0	0
T73	0	20	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T84	0	13	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T151	0	20	0	0
T168	0	3	0	0
T169	0	4	0	0
T206	0	10	0	0
T279	0	1	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1690	0	0
T8	631614	0	0	0
T9	54964	0	0	0
T10	136186	0	0	0
T23	236822	15	0	0
T37	0	3	0	0
T44	0	25	0	0
T64	205358	0	0	0
T73	0	12	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T84	0	3	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T151	0	16	0	0
T168	0	1	0	0
T169	0	12	0	0
T206	0	16	0	0
T279	0	1	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	5551	0	0
T8	631614	69	0	0
T9	54964	0	0	0
T10	136186	64	0	0
T23	236822	7	0	0
T32	0	29	0	0
T33	0	59	0	0
T49	0	56	0	0
T63	0	29	0	0
T64	205358	0	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T118	0	90	0	0
T278	0	73	0	0
T279	0	18	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	5695	0	0
T8	631614	45	0	0
T9	54964	0	0	0
T10	136186	83	0	0
T23	236822	15	0	0
T32	0	36	0	0
T33	0	86	0	0
T49	0	49	0	0
T63	0	39	0	0
T64	205358	0	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T118	0	79	0	0
T278	0	58	0	0
T279	0	11	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	5623	0	0
T8	631614	48	0	0
T9	54964	0	0	0
T10	136186	49	0	0
T23	236822	9	0	0
T32	0	19	0	0
T33	0	81	0	0
T49	0	35	0	0
T63	0	36	0	0
T64	205358	0	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T118	0	74	0	0
T278	0	70	0	0
T279	0	25	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	6008	0	0
T8	631614	56	0	0
T9	54964	0	0	0
T10	136186	89	0	0
T23	236822	10	0	0
T32	0	58	0	0
T33	0	85	0	0
T49	0	29	0	0
T63	0	58	0	0
T64	205358	0	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T118	0	74	0	0
T278	0	72	0	0
T279	0	24	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	5741	0	0
T8	631614	45	0	0
T9	54964	0	0	0
T10	136186	57	0	0
T23	236822	26	0	0
T32	0	44	0	0
T33	0	46	0	0
T49	0	87	0	0
T63	0	41	0	0
T64	205358	0	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T118	0	62	0	0
T278	0	64	0	0
T279	0	29	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	5832	0	0
T8	631614	41	0	0
T9	54964	0	0	0
T10	136186	67	0	0
T23	236822	29	0	0
T32	0	38	0	0
T33	0	88	0	0
T49	0	39	0	0
T63	0	52	0	0
T64	205358	0	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T118	0	68	0	0
T278	0	90	0	0
T279	0	13	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	5836	0	0
T8	631614	44	0	0
T9	54964	0	0	0
T10	136186	78	0	0
T23	236822	3	0	0
T32	0	45	0	0
T33	0	73	0	0
T49	0	39	0	0
T63	0	25	0	0
T64	205358	0	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T118	0	72	0	0
T278	0	96	0	0
T279	0	20	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	5527	0	0
T8	631614	45	0	0
T9	54964	0	0	0
T10	136186	57	0	0
T23	236822	20	0	0
T32	0	57	0	0
T33	0	70	0	0
T49	0	48	0	0
T63	0	57	0	0
T64	205358	0	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T118	0	67	0	0
T278	0	65	0	0
T279	0	22	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	3321	0	0
T2	35870	0	0	0
T3	423384	0	0	0
T8	0	16	0	0
T10	0	31	0	0
T13	252864	5	0	0
T14	89457	3	0	0
T15	166272	0	0	0
T16	215685	0	0	0
T17	253024	0	0	0
T18	192275	0	0	0
T22	57038	0	0	0
T23	0	21	0	0
T26	0	3	0	0
T28	36301	0	0	0
T33	0	53	0	0
T49	0	31	0	0
T63	0	22	0	0
T279	0	27	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	2534	0	0
T8	631614	0	0	0
T9	54964	0	0	0
T10	136186	0	0	0
T23	236822	45	0	0
T37	0	11	0	0
T44	0	49	0	0
T64	205358	0	0	0
T73	0	17	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T84	0	10	0	0
T96	0	35	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T151	0	52	0	0
T168	0	42	0	0
T279	0	5	0	0
T292	0	18	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	5285	0	0
T7	78220	4	0	0
T8	631614	0	0	0
T23	236822	7	0	0
T27	148502	0	0	0
T35	0	2	0	0
T36	0	5	0	0
T44	0	42	0	0
T60	106309	0	0	0
T73	0	16	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T84	0	1	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T151	0	15	0	0
T182	0	3	0	0
T279	0	13	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1941	0	0
T8	631614	0	0	0
T9	54964	0	0	0
T10	136186	0	0	0
T23	236822	17	0	0
T37	0	4	0	0
T44	0	43	0	0
T64	205358	0	0	0
T73	0	22	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T84	0	4	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T151	0	27	0	0
T168	0	6	0	0
T169	0	14	0	0
T206	0	22	0	0
T279	0	11	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	5909	0	0
T8	631614	0	0	0
T9	54964	0	0	0
T10	136186	0	0	0
T23	236822	51	0	0
T24	0	76	0	0
T44	0	46	0	0
T64	205358	0	0	0
T73	0	84	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T84	0	16	0	0
T97	30893	0	0	0
T110	0	51	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T279	0	21	0	0
T293	0	71	0	0
T294	0	71	0	0
T295	0	61	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	8190	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T23	236822	178	0	0
T26	627646	0	0	0
T27	148502	0	0	0
T37	0	51	0	0
T44	0	33	0	0
T57	16438	73	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T60	106309	0	0	0
T73	0	23	0	0
T75	42434	0	0	0
T110	0	95	0	0
T191	0	59	0	0
T279	0	12	0	0
T296	0	75	0	0
T297	0	68	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	5745	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T23	236822	126	0	0
T26	627646	0	0	0
T27	148502	0	0	0
T37	0	43	0	0
T44	0	25	0	0
T57	16438	65	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T60	106309	0	0	0
T73	0	12	0	0
T75	42434	0	0	0
T84	0	10	0	0
T110	0	60	0	0
T191	0	83	0	0
T279	0	16	0	0
T296	0	59	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	5913	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T23	236822	167	0	0
T26	627646	0	0	0
T27	148502	0	0	0
T37	0	46	0	0
T44	0	37	0	0
T57	16438	70	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T60	106309	0	0	0
T73	0	17	0	0
T75	42434	0	0	0
T84	0	7	0	0
T110	0	51	0	0
T191	0	66	0	0
T279	0	5	0	0
T296	0	76	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	2080	0	0
T8	631614	0	0	0
T9	54964	0	0	0
T10	136186	0	0	0
T23	236822	27	0	0
T37	0	16	0	0
T44	0	26	0	0
T64	205358	0	0	0
T73	0	18	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T84	0	10	0	0
T97	30893	0	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T151	0	21	0	0
T168	0	1	0	0
T169	0	17	0	0
T206	0	4	0	0
T279	0	9	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1923	0	0
T6	885350	9	0	0
T7	78220	0	0	0
T11	0	13	0	0
T23	236822	18	0	0
T27	148502	0	0	0
T44	0	46	0	0
T60	106309	0	0	0
T67	0	1	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T83	0	3	0	0
T84	0	2	0	0
T96	0	5	0	0
T97	30893	0	0	0
T111	0	8	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T279	0	3	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	2000	0	0
T6	885350	4	0	0
T7	78220	0	0	0
T9	0	5	0	0
T11	0	12	0	0
T23	236822	30	0	0
T27	148502	0	0	0
T44	0	36	0	0
T60	106309	0	0	0
T67	0	1	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T84	0	25	0	0
T96	0	3	0	0
T97	30893	0	0	0
T111	0	15	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T279	0	5	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1960	0	0
T8	631614	0	0	0
T9	54964	5	0	0
T10	136186	0	0	0
T11	0	12	0	0
T23	236822	7	0	0
T44	0	42	0	0
T64	205358	0	0	0
T67	0	1	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T84	0	16	0	0
T96	0	2	0	0
T97	30893	0	0	0
T106	0	7	0	0
T111	0	10	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T279	0	11	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1964	0	0
T6	885350	3	0	0
T7	78220	0	0	0
T9	0	2	0	0
T11	0	9	0	0
T23	236822	2	0	0
T27	148502	0	0	0
T44	0	36	0	0
T60	106309	0	0	0
T67	0	8	0	0
T75	42434	0	0	0
T76	63120	0	0	0
T84	0	6	0	0
T97	30893	0	0	0
T106	0	3	0	0
T111	0	21	0	0
T115	51814	0	0	0
T116	107980	0	0	0
T279	0	10	0	0