Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	89.20			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_status_cdc	96.88	100.00	87.50			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_invert_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_value_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T4,T5,T13

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T5,T13
1	1	Covered	T4,T5,T13

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T4,T5,T13

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T13
1	1	Covered	T4,T5,T13

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_ulp_ctl_cdc

SCORE	COND
96.88	87.50

tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T3,T6,T8

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T3,T6,T8
1	1	Covered	T3,T6,T8

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T9
1	-	Covered	T3,T6,T8

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T8

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T6,T8
1	1	Covered	T3,T6,T8

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T5,T13,T14
0	0	1	Covered	T5,T13,T14
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T5,T13,T14
0	0	1	Covered	T5,T13,T14
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	96749612	0	0
DstReqKnown_A	228752782	201657978	0	0
SrcAckBusyChk_A	2147483647	111827	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	96749612	0	0
T1	463564	0	0	0
T2	179350	0	0	0
T3	3387072	1432	0	0
T5	981234	0	0	0
T6	18592350	1944	0	0
T7	1407960	0	0	0
T8	0	14502	0	0
T10	0	3310	0	0
T12	0	2228	0	0
T13	758592	0	0	0
T14	268371	0	0	0
T15	831360	4425	0	0
T16	1078425	0	0	0
T17	1265120	0	0	0
T18	4806875	2904	0	0
T22	1311874	0	0	0
T23	0	12611	0	0
T25	0	3821	0	0
T26	13180566	906	0	0
T27	148502	3026	0	0
T28	834923	294	0	0
T39	0	7161	0	0
T45	0	129	0	0
T49	0	4992	0	0
T50	0	2249	0	0
T51	0	11339	0	0
T52	0	14338	0	0
T53	0	10275	0	0
T54	0	6489	0	0
T55	0	5908	0	0
T56	4900311	0	0	0
T57	378074	0	0	0
T58	3842958	0	0	0
T59	5114760	0	0	0
T60	106309	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228752782	201657978	0	0
T1	6438886	6425286	0	0
T2	18734	5134	0	0
T3	10153624	9932318	0	0
T4	17850	4250	0	0
T5	23154	9554	0	0
T13	17884	4284	0	0
T14	25330	11730	0	0
T15	22576	8976	0	0
T16	149668	68	0	0
T17	17714	4114	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	111827	0	0
T1	463564	0	0	0
T2	179350	0	0	0
T3	3387072	1	0	0
T5	981234	0	0	0
T6	18592350	1	0	0
T7	1407960	0	0	0
T8	0	8	0	0
T10	0	24	0	0
T12	0	18	0	0
T13	758592	0	0	0
T14	268371	0	0	0
T15	831360	6	0	0
T16	1078425	0	0	0
T17	1265120	0	0	0
T18	4806875	6	0	0
T22	1311874	0	0	0
T23	0	16	0	0
T25	0	8	0	0
T26	13180566	2	0	0
T27	148502	8	0	0
T28	834923	1	0	0
T39	0	8	0	0
T45	0	1	0	0
T49	0	12	0	0
T50	0	7	0	0
T51	0	7	0	0
T52	0	8	0	0
T53	0	6	0	0
T54	0	7	0	0
T55	0	7	0	0
T56	4900311	0	0	0
T57	378074	0	0	0
T58	3842958	0	0	0
T59	5114760	0	0	0
T60	106309	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7880588	7878174	0	0
T2	1219580	1216282	0	0
T3	14395056	14285644	0	0
T4	2054722	2051798	0	0
T5	11120652	11118952	0	0
T13	8597376	8595064	0	0
T14	3041538	3038818	0	0
T15	5653248	5651174	0	0
T16	7333290	7330264	0	0
T17	8602816	8599994	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T3,T6,T8

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T3,T6,T8
1	1	Covered	T3,T6,T8

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T61,T19,T29
1	-	Covered	T3,T6,T8

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T8

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T6,T8
1	1	Covered	T3,T6,T8

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T3,T6,T8
0	0	1	Covered	T3,T6,T8
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T3,T6,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	1037212	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	1171	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1037212	0	0
T3	423384	1432	0	0
T6	885350	3367	0	0
T8	0	5418	0	0
T9	0	431	0	0
T10	0	1195	0	0
T11	0	333	0	0
T12	0	385	0	0
T18	192275	0	0	0
T22	57038	0	0	0
T26	627646	0	0	0
T28	36301	0	0	0
T33	0	18988	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T62	0	447	0	0
T63	0	307	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1171	0	0
T3	423384	1	0	0
T6	885350	2	0	0
T8	0	3	0	0
T9	0	1	0	0
T10	0	10	0	0
T11	0	1	0	0
T12	0	3	0	0
T18	192275	0	0	0
T22	57038	0	0	0
T26	627646	0	0	0
T28	36301	0	0	0
T33	0	13	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T62	0	1	0	0
T63	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T5,T13,T14

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T5,T13,T14
1	1	Covered	T5,T13,T14

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T5,T13,T14

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T13,T14
1	1	Covered	T5,T13,T14

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T5,T13,T14
0	0	1	Covered	T5,T13,T14
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T5,T13,T14
0	0	1	Covered	T5,T13,T14
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	1631590	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	1977	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1631590	0	0
T2	35870	0	0	0
T3	423384	4783	0	0
T5	327078	1437	0	0
T6	0	1928	0	0
T8	0	6606	0	0
T13	252864	1427	0	0
T14	89457	333	0	0
T15	166272	0	0	0
T16	215685	0	0	0
T17	253024	0	0	0
T18	192275	1365	0	0
T26	0	449	0	0
T27	0	1602	0	0
T28	36301	280	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1977	0	0
T2	35870	0	0	0
T3	423384	3	0	0
T5	327078	1	0	0
T6	0	1	0	0
T8	0	4	0	0
T13	252864	1	0	0
T14	89457	1	0	0
T15	166272	0	0	0
T16	215685	0	0	0
T17	253024	0	0	0
T18	192275	3	0	0
T26	0	1	0	0
T27	0	4	0	0
T28	36301	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T3,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T3,T6,T9
1	1	Covered	T3,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T3,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T6,T9
1	1	Covered	T3,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T3,T6,T9
0	0	1	Covered	T3,T6,T9
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T3,T6,T9
0	0	1	Covered	T3,T6,T9
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	832689	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	983	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	832689	0	0
T3	423384	3354	0	0
T6	885350	3409	0	0
T9	0	462	0	0
T11	0	1141	0	0
T18	192275	0	0	0
T22	57038	0	0	0
T26	627646	0	0	0
T28	36301	0	0	0
T53	0	1466	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T62	0	1342	0	0
T64	0	1496	0	0
T65	0	76	0	0
T66	0	301	0	0
T67	0	1444	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	983	0	0
T3	423384	2	0	0
T6	885350	2	0	0
T9	0	1	0	0
T11	0	3	0	0
T18	192275	0	0	0
T22	57038	0	0	0
T26	627646	0	0	0
T28	36301	0	0	0
T53	0	1	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T62	0	3	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T3,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T3,T6,T9
1	1	Covered	T3,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T3,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T6,T9
1	1	Covered	T3,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T3,T6,T9
0	0	1	Covered	T3,T6,T9
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T3,T6,T9
0	0	1	Covered	T3,T6,T9
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	871879	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	1017	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	871879	0	0
T3	423384	3350	0	0
T6	885350	3391	0	0
T9	0	450	0	0
T11	0	1102	0	0
T18	192275	0	0	0
T22	57038	0	0	0
T26	627646	0	0	0
T28	36301	0	0	0
T53	0	1464	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T62	0	1311	0	0
T64	0	1494	0	0
T65	0	73	0	0
T66	0	295	0	0
T67	0	1434	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1017	0	0
T3	423384	2	0	0
T6	885350	2	0	0
T9	0	1	0	0
T11	0	3	0	0
T18	192275	0	0	0
T22	57038	0	0	0
T26	627646	0	0	0
T28	36301	0	0	0
T53	0	1	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T62	0	3	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T3,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T3,T6,T9
1	1	Covered	T3,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T3,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T6,T9
1	1	Covered	T3,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T3,T6,T9
0	0	1	Covered	T3,T6,T9
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T3,T6,T9
0	0	1	Covered	T3,T6,T9
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	862682	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	1012	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	862682	0	0
T3	423384	3346	0	0
T6	885350	3370	0	0
T9	0	433	0	0
T11	0	1058	0	0
T18	192275	0	0	0
T22	57038	0	0	0
T26	627646	0	0	0
T28	36301	0	0	0
T53	0	1462	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T62	0	1288	0	0
T64	0	1492	0	0
T65	0	63	0	0
T66	0	290	0	0
T67	0	1424	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1012	0	0
T3	423384	2	0	0
T6	885350	2	0	0
T9	0	1	0	0
T11	0	3	0	0
T18	192275	0	0	0
T22	57038	0	0	0
T26	627646	0	0	0
T28	36301	0	0	0
T53	0	1	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T62	0	3	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T22,T23,T24

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T22,T23,T24

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T22,T23,T24
0	0	1	Covered	T22,T23,T24
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T22,T23,T24
0	0	1	Covered	T22,T23,T24
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	1998550	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	2591	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1998550	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T22	57038	7936	0	0
T23	0	16389	0	0
T24	0	11965	0	0
T26	627646	0	0	0
T27	148502	0	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T60	106309	0	0	0
T68	0	8526	0	0
T69	0	16803	0	0
T70	0	34439	0	0
T71	0	35538	0	0
T72	0	5608	0	0
T73	0	33006	0	0
T74	0	9236	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	2591	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T22	57038	20	0	0
T23	0	20	0	0
T24	0	20	0	0
T26	627646	0	0	0
T27	148502	0	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T60	106309	0	0	0
T68	0	20	0	0
T69	0	20	0	0
T70	0	20	0	0
T71	0	20	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T4,T17,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T17,T3
1	1	Covered	T4,T17,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T4,T17,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T17,T3
1	1	Covered	T4,T17,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T4,T17,T3
0	0	1	Covered	T4,T17,T3
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T4,T17,T3
0	0	1	Covered	T4,T17,T3
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	4881643	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	5800	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	4881643	0	0
T1	231782	0	0	0
T2	35870	0	0	0
T3	423384	64170	0	0
T4	60433	7535	0	0
T5	327078	0	0	0
T13	252864	0	0	0
T14	89457	0	0	0
T15	166272	0	0	0
T16	215685	0	0	0
T17	253024	33576	0	0
T22	0	455	0	0
T23	0	95481	0	0
T57	0	1769	0	0
T59	0	33393	0	0
T75	0	5378	0	0
T76	0	8810	0	0
T77	0	2941	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	5800	0	0
T1	231782	0	0	0
T2	35870	0	0	0
T3	423384	40	0	0
T4	60433	20	0	0
T5	327078	0	0	0
T13	252864	0	0	0
T14	89457	0	0	0
T15	166272	0	0	0
T16	215685	0	0	0
T17	253024	20	0	0
T22	0	1	0	0
T23	0	113	0	0
T57	0	20	0	0
T59	0	20	0	0
T75	0	20	0	0
T76	0	20	0	0
T77	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T4,T5,T13

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T5,T13
1	1	Covered	T4,T5,T13

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T4,T5,T13

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T13
1	1	Covered	T4,T5,T13

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T4,T5,T13
0	0	1	Covered	T4,T5,T13
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T4,T5,T13
0	0	1	Covered	T4,T5,T13
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	5922016	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	6967	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	5922016	0	0
T1	231782	0	0	0
T2	35870	0	0	0
T3	423384	69602	0	0
T4	60433	7944	0	0
T5	327078	1439	0	0
T13	252864	1434	0	0
T14	89457	351	0	0
T15	166272	0	0	0
T16	215685	0	0	0
T17	253024	33864	0	0
T18	0	1467	0	0
T22	0	457	0	0
T28	0	310	0	0
T57	0	1953	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	6967	0	0
T1	231782	0	0	0
T2	35870	0	0	0
T3	423384	44	0	0
T4	60433	20	0	0
T5	327078	1	0	0
T13	252864	1	0	0
T14	89457	1	0	0
T15	166272	0	0	0
T16	215685	0	0	0
T17	253024	20	0	0
T18	0	3	0	0
T22	0	1	0	0
T28	0	1	0	0
T57	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T4,T17,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T17,T3
1	1	Covered	T4,T17,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T4,T17,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T17,T3
1	1	Covered	T4,T17,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T4,T17,T3
0	0	1	Covered	T4,T17,T3
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T4,T17,T3
0	0	1	Covered	T4,T17,T3
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	4825494	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	5692	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	4825494	0	0
T1	231782	0	0	0
T2	35870	0	0	0
T3	423384	64250	0	0
T4	60433	7767	0	0
T5	327078	0	0	0
T13	252864	0	0	0
T14	89457	0	0	0
T15	166272	0	0	0
T16	215685	0	0	0
T17	253024	33721	0	0
T23	0	95526	0	0
T50	0	7314	0	0
T57	0	1740	0	0
T59	0	33433	0	0
T75	0	5517	0	0
T76	0	8850	0	0
T77	0	2981	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	5692	0	0
T1	231782	0	0	0
T2	35870	0	0	0
T3	423384	40	0	0
T4	60433	20	0	0
T5	327078	0	0	0
T13	252864	0	0	0
T14	89457	0	0	0
T15	166272	0	0	0
T16	215685	0	0	0
T17	253024	20	0	0
T23	0	112	0	0
T50	0	20	0	0
T57	0	20	0	0
T59	0	20	0	0
T75	0	20	0	0
T76	0	20	0	0
T77	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T1,T2,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T1,T2,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	868169	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	1022	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	868169	0	0
T1	231782	1466	0	0
T2	35870	317	0	0
T3	423384	0	0	0
T5	327078	0	0	0
T7	0	365	0	0
T13	252864	0	0	0
T14	89457	0	0	0
T15	166272	0	0	0
T16	215685	0	0	0
T17	253024	0	0	0
T18	192275	0	0	0
T34	0	1940	0	0
T35	0	471	0	0
T39	0	993	0	0
T40	0	706	0	0
T41	0	725	0	0
T43	0	824	0	0
T78	0	1976	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1022	0	0
T1	231782	1	0	0
T2	35870	1	0	0
T3	423384	0	0	0
T5	327078	0	0	0
T7	0	1	0	0
T13	252864	0	0	0
T14	89457	0	0	0
T15	166272	0	0	0
T16	215685	0	0	0
T17	253024	0	0	0
T18	192275	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T78	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	1643653	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	2017	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1643653	0	0
T1	231782	1464	0	0
T2	35870	315	0	0
T3	423384	1426	0	0
T5	327078	0	0	0
T6	0	1913	0	0
T7	0	358	0	0
T8	0	6562	0	0
T13	252864	0	0	0
T14	89457	0	0	0
T15	166272	0	0	0
T16	215685	0	0	0
T17	253024	0	0	0
T18	192275	1359	0	0
T26	0	446	0	0
T27	0	1571	0	0
T28	0	277	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	2017	0	0
T1	231782	1	0	0
T2	35870	1	0	0
T3	423384	1	0	0
T5	327078	0	0	0
T6	0	1	0	0
T7	0	1	0	0
T8	0	4	0	0
T13	252864	0	0	0
T14	89457	0	0	0
T15	166272	0	0	0
T16	215685	0	0	0
T17	253024	0	0	0
T18	192275	3	0	0
T26	0	1	0	0
T27	0	4	0	0
T28	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T15,T23,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T15,T23,T25
1	1	Covered	T15,T23,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T15,T23,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T15,T23,T25
1	1	Covered	T15,T23,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T15,T23,T25
0	0	1	Covered	T15,T23,T25
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T15,T23,T25
0	0	1	Covered	T15,T23,T25
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	1063237	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	1224	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1063237	0	0
T2	35870	0	0	0
T3	423384	0	0	0
T15	166272	2224	0	0
T16	215685	0	0	0
T17	253024	0	0	0
T18	192275	0	0	0
T22	57038	0	0	0
T23	0	7950	0	0
T25	0	2352	0	0
T28	36301	0	0	0
T39	0	4458	0	0
T50	0	1298	0	0
T51	0	6357	0	0
T52	0	8905	0	0
T53	0	6855	0	0
T54	0	3746	0	0
T55	0	3425	0	0
T56	213057	0	0	0
T57	16438	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1224	0	0
T2	35870	0	0	0
T3	423384	0	0	0
T15	166272	3	0	0
T16	215685	0	0	0
T17	253024	0	0	0
T18	192275	0	0	0
T22	57038	0	0	0
T23	0	10	0	0
T25	0	5	0	0
T28	36301	0	0	0
T39	0	5	0	0
T50	0	4	0	0
T51	0	4	0	0
T52	0	5	0	0
T53	0	4	0	0
T54	0	4	0	0
T55	0	4	0	0
T56	213057	0	0	0
T57	16438	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T15,T23,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T15,T23,T25
1	1	Covered	T15,T23,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T15,T23,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T15,T23,T25
1	1	Covered	T15,T23,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T15,T23,T25
0	0	1	Covered	T15,T23,T25
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T15,T23,T25
0	0	1	Covered	T15,T23,T25
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	970449	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	1130	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	970449	0	0
T2	35870	0	0	0
T3	423384	0	0	0
T15	166272	2201	0	0
T16	215685	0	0	0
T17	253024	0	0	0
T18	192275	0	0	0
T22	57038	0	0	0
T23	0	4661	0	0
T25	0	1469	0	0
T28	36301	0	0	0
T39	0	2703	0	0
T50	0	951	0	0
T51	0	4982	0	0
T52	0	5433	0	0
T53	0	3420	0	0
T54	0	2743	0	0
T55	0	2483	0	0
T56	213057	0	0	0
T57	16438	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1130	0	0
T2	35870	0	0	0
T3	423384	0	0	0
T15	166272	3	0	0
T16	215685	0	0	0
T17	253024	0	0	0
T18	192275	0	0	0
T22	57038	0	0	0
T23	0	6	0	0
T25	0	3	0	0
T28	36301	0	0	0
T39	0	3	0	0
T50	0	3	0	0
T51	0	3	0	0
T52	0	3	0	0
T53	0	2	0	0
T54	0	3	0	0
T55	0	3	0	0
T56	213057	0	0	0
T57	16438	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	6399136	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	7062	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	6399136	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	139476	0	0
T18	192275	38368	0	0
T22	57038	0	0	0
T26	627646	22456	0	0
T27	0	34494	0	0
T28	36301	0	0	0
T31	0	68704	0	0
T45	0	137	0	0
T46	0	560	0	0
T47	0	156731	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T79	0	119799	0	0
T80	0	21889	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	7062	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	82	0	0
T18	192275	68	0	0
T22	57038	0	0	0
T26	627646	51	0	0
T27	0	83	0	0
T28	36301	0	0	0
T31	0	82	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	89	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T79	0	72	0	0
T80	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	6193488	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	6999	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	6193488	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	108790	0	0
T18	192275	38078	0	0
T22	57038	0	0	0
T26	627646	21449	0	0
T27	0	33334	0	0
T28	36301	0	0	0
T31	0	54358	0	0
T47	0	111010	0	0
T48	0	97743	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T79	0	119505	0	0
T80	0	21679	0	0
T81	0	26815	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	6999	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	65	0	0
T18	192275	68	0	0
T22	57038	0	0	0
T26	627646	51	0	0
T27	0	83	0	0
T28	36301	0	0	0
T31	0	66	0	0
T47	0	64	0	0
T48	0	57	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T79	0	72	0	0
T80	0	51	0	0
T81	0	66	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	6201649	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	6909	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	6201649	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	160419	0	0
T18	192275	30329	0	0
T22	57038	0	0	0
T26	627646	20436	0	0
T27	0	32039	0	0
T28	36301	0	0	0
T31	0	59626	0	0
T47	0	156114	0	0
T48	0	115552	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T79	0	119211	0	0
T80	0	21469	0	0
T81	0	30867	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	6909	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	95	0	0
T18	192275	55	0	0
T22	57038	0	0	0
T26	627646	51	0	0
T27	0	83	0	0
T28	36301	0	0	0
T31	0	74	0	0
T47	0	89	0	0
T48	0	68	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T79	0	72	0	0
T80	0	51	0	0
T81	0	77	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	6151838	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	6944	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	6151838	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	116629	0	0
T18	192275	36430	0	0
T22	57038	0	0	0
T26	627646	19524	0	0
T27	0	19802	0	0
T28	36301	0	0	0
T31	0	47083	0	0
T47	0	110560	0	0
T48	0	123843	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T79	0	84644	0	0
T80	0	21259	0	0
T81	0	31396	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	6944	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	71	0	0
T18	192275	66	0	0
T22	57038	0	0	0
T26	627646	51	0	0
T27	0	54	0	0
T28	36301	0	0	0
T31	0	60	0	0
T47	0	64	0	0
T48	0	73	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T79	0	51	0	0
T80	0	51	0	0
T81	0	81	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	1015633	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	1207	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1015633	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	7444	0	0
T18	192275	1479	0	0
T22	57038	0	0	0
T26	627646	494	0	0
T27	0	1641	0	0
T28	36301	0	0	0
T31	0	8456	0	0
T45	0	135	0	0
T46	0	553	0	0
T47	0	1999	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T79	0	1438	0	0
T80	0	358	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1207	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	4	0	0
T18	192275	3	0	0
T22	57038	0	0	0
T26	627646	1	0	0
T27	0	4	0	0
T28	36301	0	0	0
T31	0	10	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T79	0	1	0	0
T80	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	1043044	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	1226	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1043044	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	7223	0	0
T18	192275	1449	0	0
T22	57038	0	0	0
T26	627646	454	0	0
T27	0	1503	0	0
T28	36301	0	0	0
T31	0	8083	0	0
T47	0	1989	0	0
T48	0	3328	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T79	0	1428	0	0
T80	0	348	0	0
T81	0	1620	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1226	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	4	0	0
T18	192275	3	0	0
T22	57038	0	0	0
T26	627646	1	0	0
T27	0	4	0	0
T28	36301	0	0	0
T31	0	10	0	0
T47	0	1	0	0
T48	0	2	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	1026795	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	1223	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1026795	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	6986	0	0
T18	192275	1419	0	0
T22	57038	0	0	0
T26	627646	408	0	0
T27	0	1351	0	0
T28	36301	0	0	0
T31	0	7763	0	0
T47	0	1979	0	0
T48	0	3263	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T79	0	1418	0	0
T80	0	338	0	0
T81	0	1483	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1223	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	4	0	0
T18	192275	3	0	0
T22	57038	0	0	0
T26	627646	1	0	0
T27	0	4	0	0
T28	36301	0	0	0
T31	0	10	0	0
T47	0	1	0	0
T48	0	2	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	1028768	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	1212	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1028768	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	6762	0	0
T18	192275	1389	0	0
T22	57038	0	0	0
T26	627646	482	0	0
T27	0	1343	0	0
T28	36301	0	0	0
T31	0	7403	0	0
T47	0	1969	0	0
T48	0	3203	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T79	0	1408	0	0
T80	0	328	0	0
T81	0	1594	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1212	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	4	0	0
T18	192275	3	0	0
T22	57038	0	0	0
T26	627646	1	0	0
T27	0	4	0	0
T28	36301	0	0	0
T31	0	10	0	0
T47	0	1	0	0
T48	0	2	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T3,T18,T28

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T3,T18,T28
1	1	Covered	T3,T18,T28

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T3,T18,T28

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T18,T28
1	1	Covered	T3,T18,T28

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T3,T18,T28
0	0	1	Covered	T3,T18,T28
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T3,T18,T28
0	0	1	Covered	T3,T18,T28
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	6980706	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	7748	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	6980706	0	0
T3	423384	1434	0	0
T6	885350	1951	0	0
T8	0	140150	0	0
T10	0	1729	0	0
T12	0	1291	0	0
T18	192275	38486	0	0
T22	57038	0	0	0
T26	627646	22909	0	0
T27	0	34992	0	0
T28	36301	301	0	0
T45	0	131	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	7748	0	0
T3	423384	1	0	0
T6	885350	1	0	0
T8	0	82	0	0
T10	0	12	0	0
T12	0	9	0	0
T18	192275	68	0	0
T22	57038	0	0	0
T26	627646	51	0	0
T27	0	83	0	0
T28	36301	1	0	0
T45	0	1	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	6784305	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	7676	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	6784305	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	109364	0	0
T10	0	1594	0	0
T12	0	1217	0	0
T18	192275	38196	0	0
T22	57038	0	0	0
T26	627646	21899	0	0
T27	0	33720	0	0
T28	36301	0	0	0
T33	0	20960	0	0
T47	0	111132	0	0
T49	0	5362	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T63	0	590	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	7676	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	65	0	0
T10	0	12	0	0
T12	0	9	0	0
T18	192275	68	0	0
T22	57038	0	0	0
T26	627646	51	0	0
T27	0	83	0	0
T28	36301	0	0	0
T33	0	14	0	0
T47	0	64	0	0
T49	0	12	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T63	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	6822147	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	7610	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	6822147	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	161302	0	0
T10	0	1462	0	0
T12	0	1161	0	0
T18	192275	30421	0	0
T22	57038	0	0	0
T26	627646	20876	0	0
T27	0	32537	0	0
T28	36301	0	0	0
T33	0	20818	0	0
T47	0	156286	0	0
T49	0	5236	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T63	0	604	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	7610	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	95	0	0
T10	0	12	0	0
T12	0	9	0	0
T18	192275	55	0	0
T22	57038	0	0	0
T26	627646	51	0	0
T27	0	83	0	0
T28	36301	0	0	0
T33	0	14	0	0
T47	0	89	0	0
T49	0	12	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T63	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	6673673	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	7562	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	6673673	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	117191	0	0
T10	0	1415	0	0
T12	0	1120	0	0
T18	192275	36544	0	0
T22	57038	0	0	0
T26	627646	19964	0	0
T27	0	20235	0	0
T28	36301	0	0	0
T33	0	20675	0	0
T47	0	110682	0	0
T49	0	5156	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T63	0	631	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	7562	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	71	0	0
T10	0	12	0	0
T12	0	9	0	0
T18	192275	66	0	0
T22	57038	0	0	0
T26	627646	51	0	0
T27	0	54	0	0
T28	36301	0	0	0
T33	0	14	0	0
T47	0	64	0	0
T49	0	12	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T63	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T3,T18,T28

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T3,T18,T28
1	1	Covered	T3,T18,T28

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T3,T18,T28

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T18,T28
1	1	Covered	T3,T18,T28

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T3,T18,T28
0	0	1	Covered	T3,T18,T28
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T3,T18,T28
0	0	1	Covered	T3,T18,T28
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	1596061	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	1924	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1596061	0	0
T3	423384	1432	0	0
T6	885350	1944	0	0
T8	0	7354	0	0
T10	0	1676	0	0
T12	0	1055	0	0
T18	192275	1467	0	0
T22	57038	0	0	0
T26	627646	479	0	0
T27	0	1597	0	0
T28	36301	294	0	0
T45	0	129	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1924	0	0
T3	423384	1	0	0
T6	885350	1	0	0
T8	0	4	0	0
T10	0	12	0	0
T12	0	9	0	0
T18	192275	3	0	0
T22	57038	0	0	0
T26	627646	1	0	0
T27	0	4	0	0
T28	36301	1	0	0
T45	0	1	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	1528862	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	1858	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1528862	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	7148	0	0
T10	0	1634	0	0
T12	0	1173	0	0
T18	192275	1437	0	0
T22	57038	0	0	0
T26	627646	427	0	0
T27	0	1429	0	0
T28	36301	0	0	0
T33	0	20378	0	0
T47	0	1985	0	0
T49	0	4992	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T63	0	595	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1858	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	4	0	0
T10	0	12	0	0
T12	0	9	0	0
T18	192275	3	0	0
T22	57038	0	0	0
T26	627646	1	0	0
T27	0	4	0	0
T28	36301	0	0	0
T33	0	14	0	0
T47	0	1	0	0
T49	0	12	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T63	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	1555853	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	1869	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1555853	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	6901	0	0
T10	0	1527	0	0
T12	0	1230	0	0
T18	192275	1407	0	0
T22	57038	0	0	0
T26	627646	388	0	0
T27	0	1299	0	0
T28	36301	0	0	0
T33	0	20206	0	0
T47	0	1975	0	0
T49	0	4880	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T63	0	582	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1869	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	4	0	0
T10	0	12	0	0
T12	0	9	0	0
T18	192275	3	0	0
T22	57038	0	0	0
T26	627646	1	0	0
T27	0	4	0	0
T28	36301	0	0	0
T33	0	14	0	0
T47	0	1	0	0
T49	0	12	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T63	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	1483299	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	1825	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1483299	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	6686	0	0
T10	0	1535	0	0
T12	0	1186	0	0
T18	192275	1377	0	0
T22	57038	0	0	0
T26	627646	461	0	0
T27	0	1539	0	0
T28	36301	0	0	0
T33	0	20060	0	0
T47	0	1965	0	0
T49	0	4784	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T63	0	620	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1825	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	4	0	0
T10	0	12	0	0
T12	0	9	0	0
T18	192275	3	0	0
T22	57038	0	0	0
T26	627646	1	0	0
T27	0	4	0	0
T28	36301	0	0	0
T33	0	14	0	0
T47	0	1	0	0
T49	0	12	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T63	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T3,T18,T28

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T3,T18,T28
1	1	Covered	T3,T18,T28

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T3,T18,T28

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T18,T28
1	1	Covered	T3,T18,T28

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T3,T18,T28
0	0	1	Covered	T3,T18,T28
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T3,T18,T28
0	0	1	Covered	T3,T18,T28
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	1520992	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	1867	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1520992	0	0
T3	423384	1430	0	0
T6	885350	1937	0	0
T8	0	7320	0	0
T10	0	1545	0	0
T12	0	1127	0	0
T18	192275	1461	0	0
T22	57038	0	0	0
T26	627646	473	0	0
T27	0	1561	0	0
T28	36301	287	0	0
T45	0	127	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1867	0	0
T3	423384	1	0	0
T6	885350	1	0	0
T8	0	4	0	0
T10	0	12	0	0
T12	0	9	0	0
T18	192275	3	0	0
T22	57038	0	0	0
T26	627646	1	0	0
T27	0	4	0	0
T28	36301	1	0	0
T45	0	1	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	1508190	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	1839	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1508190	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	7101	0	0
T10	0	1499	0	0
T12	0	1094	0	0
T18	192275	1431	0	0
T22	57038	0	0	0
T26	627646	424	0	0
T27	0	1398	0	0
T28	36301	0	0	0
T33	0	19779	0	0
T47	0	1983	0	0
T49	0	4560	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T63	0	575	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1839	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	4	0	0
T10	0	12	0	0
T12	0	9	0	0
T18	192275	3	0	0
T22	57038	0	0	0
T26	627646	1	0	0
T27	0	4	0	0
T28	36301	0	0	0
T33	0	14	0	0
T47	0	1	0	0
T49	0	12	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T63	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	1468678	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	1813	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1468678	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	6858	0	0
T10	0	1550	0	0
T12	0	1115	0	0
T18	192275	1401	0	0
T22	57038	0	0	0
T26	627646	378	0	0
T27	0	1282	0	0
T28	36301	0	0	0
T33	0	19645	0	0
T47	0	1973	0	0
T49	0	4437	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T63	0	593	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1813	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	4	0	0
T10	0	12	0	0
T12	0	9	0	0
T18	192275	3	0	0
T22	57038	0	0	0
T26	627646	1	0	0
T27	0	4	0	0
T28	36301	0	0	0
T33	0	14	0	0
T47	0	1	0	0
T49	0	12	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T63	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T26,T27
1	1	Covered	T18,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T18,T26,T27
0	0	1	Covered	T18,T26,T27
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	1524098	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	1861	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1524098	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	6644	0	0
T10	0	1650	0	0
T12	0	1124	0	0
T18	192275	1371	0	0
T22	57038	0	0	0
T26	627646	451	0	0
T27	0	1626	0	0
T28	36301	0	0	0
T33	0	19504	0	0
T47	0	1963	0	0
T49	0	4337	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T63	0	591	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1861	0	0
T6	885350	0	0	0
T7	78220	0	0	0
T8	0	4	0	0
T10	0	12	0	0
T12	0	9	0	0
T18	192275	3	0	0
T22	57038	0	0	0
T26	627646	1	0	0
T27	0	4	0	0
T28	36301	0	0	0
T33	0	14	0	0
T47	0	1	0	0
T49	0	12	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T63	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T3,T6,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T3,T6,T9
1	1	Covered	T3,T6,T9

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T9
1	-	Covered	T3,T6,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T3,T6,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T6,T9
1	1	Covered	T3,T6,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T3,T6,T9
0	0	1	Covered	T3,T6,T9
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T3,T6,T9
0	0	1	Covered	T3,T6,T9
0	0	0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1150178757	833134	0	0
DstReqKnown_A	6728023	5931117	0	0
SrcAckBusyChk_A	1150178757	990	0	0
SrcBusyKnown_A	1150178757	1148532477	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	833134	0	0
T3	423384	2870	0	0
T6	885350	6325	0	0
T9	0	914	0	0
T11	0	802	0	0
T18	192275	0	0	0
T22	57038	0	0	0
T26	627646	0	0	0
T28	36301	0	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T62	0	955	0	0
T66	0	585	0	0
T67	0	2885	0	0
T82	0	6421	0	0
T83	0	3462	0	0
T84	0	1608	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6728023	5931117	0	0
T1	189379	188979	0	0
T2	551	151	0	0
T3	298636	292127	0	0
T4	525	125	0	0
T5	681	281	0	0
T13	526	126	0	0
T14	745	345	0	0
T15	664	264	0	0
T16	4402	2	0	0
T17	521	121	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	990	0	0
T3	423384	2	0	0
T6	885350	4	0	0
T9	0	2	0	0
T11	0	2	0	0
T18	192275	0	0	0
T22	57038	0	0	0
T26	627646	0	0	0
T28	36301	0	0	0
T56	213057	0	0	0
T57	16438	0	0	0
T58	182998	0	0	0
T59	243560	0	0	0
T62	0	2	0	0
T66	0	2	0	0
T67	0	2	0	0
T82	0	4	0	0
T83	0	2	0	0
T84	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150178757	1148532477	0	0
T1	231782	231711	0	0
T2	35870	35773	0	0
T3	423384	420166	0	0
T4	60433	60347	0	0
T5	327078	327028	0	0
T13	252864	252796	0	0
T14	89457	89377	0	0
T15	166272	166211	0	0
T16	215685	215596	0	0
T17	253024	252941	0	0