Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
873 |
1 |
|
|
T1 |
7 |
|
T14 |
7 |
|
T21 |
12 |
| auto[1] |
887 |
1 |
|
|
T1 |
13 |
|
T14 |
13 |
|
T21 |
8 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
892 |
1 |
|
|
T1 |
11 |
|
T14 |
11 |
|
T21 |
9 |
| auto[1] |
868 |
1 |
|
|
T1 |
9 |
|
T14 |
9 |
|
T21 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
845 |
1 |
|
|
T1 |
7 |
|
T14 |
12 |
|
T21 |
10 |
| auto[1] |
915 |
1 |
|
|
T1 |
13 |
|
T14 |
8 |
|
T21 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
883 |
1 |
|
|
T1 |
13 |
|
T14 |
10 |
|
T21 |
8 |
| auto[1] |
877 |
1 |
|
|
T1 |
7 |
|
T14 |
10 |
|
T21 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
864 |
1 |
|
|
T1 |
13 |
|
T14 |
11 |
|
T21 |
9 |
| auto[1] |
896 |
1 |
|
|
T1 |
7 |
|
T14 |
9 |
|
T21 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
862 |
1 |
|
|
T1 |
9 |
|
T14 |
11 |
|
T21 |
7 |
| auto[1] |
898 |
1 |
|
|
T1 |
11 |
|
T14 |
9 |
|
T21 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
870 |
1 |
|
|
T1 |
13 |
|
T14 |
5 |
|
T21 |
10 |
| auto[1] |
890 |
1 |
|
|
T1 |
7 |
|
T14 |
15 |
|
T21 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
895 |
1 |
|
|
T1 |
10 |
|
T14 |
5 |
|
T21 |
12 |
| auto[1] |
865 |
1 |
|
|
T1 |
10 |
|
T14 |
15 |
|
T21 |
8 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
865 |
1 |
|
|
T1 |
9 |
|
T14 |
8 |
|
T21 |
12 |
| auto[1] |
895 |
1 |
|
|
T1 |
11 |
|
T14 |
12 |
|
T21 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
888 |
1 |
|
|
T1 |
12 |
|
T14 |
11 |
|
T21 |
10 |
| auto[1] |
872 |
1 |
|
|
T1 |
8 |
|
T14 |
9 |
|
T21 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
840 |
1 |
|
|
T1 |
10 |
|
T14 |
7 |
|
T21 |
10 |
| auto[1] |
920 |
1 |
|
|
T1 |
10 |
|
T14 |
13 |
|
T21 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
871 |
1 |
|
|
T1 |
8 |
|
T14 |
10 |
|
T21 |
11 |
| auto[1] |
889 |
1 |
|
|
T1 |
12 |
|
T14 |
10 |
|
T21 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
927 |
1 |
|
|
T1 |
12 |
|
T14 |
13 |
|
T21 |
12 |
| auto[1] |
833 |
1 |
|
|
T1 |
8 |
|
T14 |
7 |
|
T21 |
8 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
892 |
1 |
|
|
T1 |
11 |
|
T14 |
11 |
|
T21 |
9 |
| auto[1] |
868 |
1 |
|
|
T1 |
9 |
|
T14 |
9 |
|
T21 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
847 |
1 |
|
|
T1 |
8 |
|
T14 |
7 |
|
T21 |
9 |
| auto[1] |
913 |
1 |
|
|
T1 |
12 |
|
T14 |
13 |
|
T21 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
913 |
1 |
|
|
T1 |
12 |
|
T14 |
13 |
|
T21 |
11 |
| auto[1] |
847 |
1 |
|
|
T1 |
8 |
|
T14 |
7 |
|
T21 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
911 |
1 |
|
|
T1 |
10 |
|
T14 |
9 |
|
T21 |
12 |
| auto[1] |
849 |
1 |
|
|
T1 |
10 |
|
T14 |
11 |
|
T21 |
8 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
859 |
1 |
|
|
T1 |
8 |
|
T14 |
11 |
|
T21 |
10 |
| auto[1] |
901 |
1 |
|
|
T1 |
12 |
|
T14 |
9 |
|
T21 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
891 |
1 |
|
|
T1 |
13 |
|
T14 |
11 |
|
T21 |
13 |
| auto[1] |
869 |
1 |
|
|
T1 |
7 |
|
T14 |
9 |
|
T21 |
7 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
896 |
1 |
|
|
T1 |
12 |
|
T14 |
11 |
|
T21 |
9 |
| auto[1] |
864 |
1 |
|
|
T1 |
8 |
|
T14 |
9 |
|
T21 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
859 |
1 |
|
|
T1 |
9 |
|
T14 |
12 |
|
T21 |
7 |
| auto[1] |
901 |
1 |
|
|
T1 |
11 |
|
T14 |
8 |
|
T21 |
13 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
899 |
1 |
|
|
T1 |
8 |
|
T14 |
10 |
|
T21 |
12 |
| auto[1] |
861 |
1 |
|
|
T1 |
12 |
|
T14 |
10 |
|
T21 |
8 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
893 |
1 |
|
|
T1 |
14 |
|
T14 |
12 |
|
T21 |
8 |
| auto[1] |
867 |
1 |
|
|
T1 |
6 |
|
T14 |
8 |
|
T21 |
12 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
871 |
1 |
|
|
T1 |
8 |
|
T14 |
10 |
|
T21 |
11 |
| auto[1] |
889 |
1 |
|
|
T1 |
12 |
|
T14 |
10 |
|
T21 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
404 |
1 |
|
|
T1 |
4 |
|
T14 |
5 |
|
T21 |
4 |
| auto[0] |
auto[1] |
443 |
1 |
|
|
T1 |
4 |
|
T14 |
2 |
|
T21 |
5 |
| auto[1] |
auto[0] |
441 |
1 |
|
|
T1 |
3 |
|
T14 |
7 |
|
T21 |
6 |
| auto[1] |
auto[1] |
472 |
1 |
|
|
T1 |
9 |
|
T14 |
6 |
|
T21 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
456 |
1 |
|
|
T1 |
9 |
|
T14 |
7 |
|
T21 |
4 |
| auto[0] |
auto[1] |
457 |
1 |
|
|
T1 |
3 |
|
T14 |
6 |
|
T21 |
7 |
| auto[1] |
auto[0] |
427 |
1 |
|
|
T1 |
4 |
|
T14 |
3 |
|
T21 |
4 |
| auto[1] |
auto[1] |
420 |
1 |
|
|
T1 |
4 |
|
T14 |
4 |
|
T21 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
442 |
1 |
|
|
T1 |
8 |
|
T14 |
5 |
|
T21 |
4 |
| auto[0] |
auto[1] |
469 |
1 |
|
|
T1 |
2 |
|
T14 |
4 |
|
T21 |
8 |
| auto[1] |
auto[0] |
422 |
1 |
|
|
T1 |
5 |
|
T14 |
6 |
|
T21 |
5 |
| auto[1] |
auto[1] |
427 |
1 |
|
|
T1 |
5 |
|
T14 |
5 |
|
T21 |
3 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
415 |
1 |
|
|
T1 |
5 |
|
T14 |
6 |
|
T21 |
2 |
| auto[0] |
auto[1] |
444 |
1 |
|
|
T1 |
3 |
|
T14 |
5 |
|
T21 |
8 |
| auto[1] |
auto[0] |
447 |
1 |
|
|
T1 |
4 |
|
T14 |
5 |
|
T21 |
5 |
| auto[1] |
auto[1] |
454 |
1 |
|
|
T1 |
8 |
|
T14 |
4 |
|
T21 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
426 |
1 |
|
|
T1 |
8 |
|
T14 |
1 |
|
T21 |
6 |
| auto[0] |
auto[1] |
465 |
1 |
|
|
T1 |
5 |
|
T14 |
10 |
|
T21 |
7 |
| auto[1] |
auto[0] |
444 |
1 |
|
|
T1 |
5 |
|
T14 |
4 |
|
T21 |
4 |
| auto[1] |
auto[1] |
425 |
1 |
|
|
T1 |
2 |
|
T14 |
5 |
|
T21 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
441 |
1 |
|
|
T1 |
6 |
|
T14 |
1 |
|
T21 |
5 |
| auto[0] |
auto[1] |
455 |
1 |
|
|
T1 |
6 |
|
T14 |
10 |
|
T21 |
4 |
| auto[1] |
auto[0] |
454 |
1 |
|
|
T1 |
4 |
|
T14 |
4 |
|
T21 |
7 |
| auto[1] |
auto[1] |
410 |
1 |
|
|
T1 |
4 |
|
T14 |
5 |
|
T21 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
464 |
1 |
|
|
T1 |
5 |
|
T14 |
4 |
|
T21 |
6 |
| auto[0] |
auto[1] |
435 |
1 |
|
|
T1 |
3 |
|
T14 |
6 |
|
T21 |
6 |
| auto[1] |
auto[0] |
424 |
1 |
|
|
T1 |
7 |
|
T14 |
7 |
|
T21 |
4 |
| auto[1] |
auto[1] |
437 |
1 |
|
|
T1 |
5 |
|
T14 |
3 |
|
T21 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
437 |
1 |
|
|
T1 |
7 |
|
T14 |
3 |
|
T21 |
4 |
| auto[0] |
auto[1] |
456 |
1 |
|
|
T1 |
7 |
|
T14 |
9 |
|
T21 |
4 |
| auto[1] |
auto[0] |
403 |
1 |
|
|
T1 |
3 |
|
T14 |
4 |
|
T21 |
6 |
| auto[1] |
auto[1] |
464 |
1 |
|
|
T1 |
3 |
|
T14 |
4 |
|
T21 |
6 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
462 |
1 |
|
|
T1 |
3 |
|
T14 |
4 |
|
T21 |
8 |
| auto[0] |
auto[1] |
465 |
1 |
|
|
T1 |
9 |
|
T14 |
9 |
|
T21 |
4 |
| auto[1] |
auto[0] |
411 |
1 |
|
|
T1 |
4 |
|
T14 |
3 |
|
T21 |
4 |
| auto[1] |
auto[1] |
422 |
1 |
|
|
T1 |
4 |
|
T14 |
4 |
|
T21 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
892 |
1 |
|
|
T1 |
11 |
|
T14 |
11 |
|
T21 |
9 |
| auto[1] |
auto[1] |
868 |
1 |
|
|
T1 |
9 |
|
T14 |
9 |
|
T21 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
406 |
1 |
|
|
T1 |
4 |
|
T14 |
3 |
|
T21 |
7 |
| auto[0] |
auto[1] |
453 |
1 |
|
|
T1 |
5 |
|
T14 |
9 |
|
T71 |
3 |
| auto[1] |
auto[0] |
459 |
1 |
|
|
T1 |
5 |
|
T14 |
5 |
|
T21 |
5 |
| auto[1] |
auto[1] |
442 |
1 |
|
|
T1 |
6 |
|
T14 |
3 |
|
T21 |
8 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
871 |
1 |
|
|
T1 |
8 |
|
T14 |
10 |
|
T21 |
11 |
| auto[1] |
auto[1] |
889 |
1 |
|
|
T1 |
12 |
|
T14 |
10 |
|
T21 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
134 |
1 |
|
|
T74 |
13 |
|
T41 |
12 |
|
T94 |
11 |
| auto[1] |
126 |
1 |
|
|
T74 |
7 |
|
T41 |
8 |
|
T94 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
122 |
1 |
|
|
T74 |
13 |
|
T41 |
9 |
|
T94 |
7 |
| auto[1] |
138 |
1 |
|
|
T74 |
7 |
|
T41 |
11 |
|
T94 |
13 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
122 |
1 |
|
|
T74 |
7 |
|
T41 |
11 |
|
T94 |
9 |
| auto[1] |
138 |
1 |
|
|
T74 |
13 |
|
T41 |
9 |
|
T94 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
137 |
1 |
|
|
T74 |
12 |
|
T41 |
11 |
|
T94 |
9 |
| auto[1] |
123 |
1 |
|
|
T74 |
8 |
|
T41 |
9 |
|
T94 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
139 |
1 |
|
|
T74 |
8 |
|
T41 |
15 |
|
T94 |
8 |
| auto[1] |
121 |
1 |
|
|
T74 |
12 |
|
T41 |
5 |
|
T94 |
12 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
137 |
1 |
|
|
T74 |
12 |
|
T41 |
9 |
|
T94 |
10 |
| auto[1] |
123 |
1 |
|
|
T74 |
8 |
|
T41 |
11 |
|
T94 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
143 |
1 |
|
|
T74 |
10 |
|
T41 |
7 |
|
T94 |
9 |
| auto[1] |
117 |
1 |
|
|
T74 |
10 |
|
T41 |
13 |
|
T94 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T74 |
10 |
|
T41 |
9 |
|
T94 |
9 |
| auto[1] |
134 |
1 |
|
|
T74 |
10 |
|
T41 |
11 |
|
T94 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T74 |
12 |
|
T41 |
13 |
|
T94 |
11 |
| auto[1] |
134 |
1 |
|
|
T74 |
8 |
|
T41 |
7 |
|
T94 |
9 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
132 |
1 |
|
|
T74 |
11 |
|
T41 |
9 |
|
T94 |
12 |
| auto[1] |
128 |
1 |
|
|
T74 |
9 |
|
T41 |
11 |
|
T94 |
8 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
132 |
1 |
|
|
T74 |
13 |
|
T41 |
10 |
|
T94 |
11 |
| auto[1] |
128 |
1 |
|
|
T74 |
7 |
|
T41 |
10 |
|
T94 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123 |
1 |
|
|
T74 |
12 |
|
T41 |
7 |
|
T94 |
13 |
| auto[1] |
137 |
1 |
|
|
T74 |
8 |
|
T41 |
13 |
|
T94 |
7 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125 |
1 |
|
|
T74 |
10 |
|
T41 |
7 |
|
T94 |
11 |
| auto[1] |
135 |
1 |
|
|
T74 |
10 |
|
T41 |
13 |
|
T94 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
122 |
1 |
|
|
T74 |
13 |
|
T41 |
9 |
|
T94 |
7 |
| auto[1] |
138 |
1 |
|
|
T74 |
7 |
|
T41 |
11 |
|
T94 |
13 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
132 |
1 |
|
|
T74 |
8 |
|
T41 |
11 |
|
T94 |
10 |
| auto[1] |
128 |
1 |
|
|
T74 |
12 |
|
T41 |
9 |
|
T94 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131 |
1 |
|
|
T74 |
11 |
|
T41 |
11 |
|
T94 |
6 |
| auto[1] |
129 |
1 |
|
|
T74 |
9 |
|
T41 |
9 |
|
T94 |
14 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
128 |
1 |
|
|
T74 |
10 |
|
T41 |
8 |
|
T94 |
10 |
| auto[1] |
132 |
1 |
|
|
T74 |
10 |
|
T41 |
12 |
|
T94 |
10 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136 |
1 |
|
|
T74 |
10 |
|
T41 |
8 |
|
T94 |
12 |
| auto[1] |
124 |
1 |
|
|
T74 |
10 |
|
T41 |
12 |
|
T94 |
8 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T74 |
9 |
|
T41 |
12 |
|
T94 |
10 |
| auto[1] |
134 |
1 |
|
|
T74 |
11 |
|
T41 |
8 |
|
T94 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
133 |
1 |
|
|
T74 |
11 |
|
T41 |
12 |
|
T94 |
8 |
| auto[1] |
127 |
1 |
|
|
T74 |
9 |
|
T41 |
8 |
|
T94 |
12 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
130 |
1 |
|
|
T74 |
8 |
|
T41 |
13 |
|
T94 |
13 |
| auto[1] |
130 |
1 |
|
|
T74 |
12 |
|
T41 |
7 |
|
T94 |
7 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T74 |
10 |
|
T41 |
11 |
|
T94 |
9 |
| auto[1] |
133 |
1 |
|
|
T74 |
10 |
|
T41 |
9 |
|
T94 |
11 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125 |
1 |
|
|
T74 |
10 |
|
T41 |
10 |
|
T94 |
10 |
| auto[1] |
135 |
1 |
|
|
T74 |
10 |
|
T41 |
10 |
|
T94 |
10 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123 |
1 |
|
|
T74 |
12 |
|
T41 |
7 |
|
T94 |
13 |
| auto[1] |
137 |
1 |
|
|
T74 |
8 |
|
T41 |
13 |
|
T94 |
7 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
61 |
1 |
|
|
T74 |
1 |
|
T41 |
4 |
|
T94 |
5 |
| auto[0] |
auto[1] |
71 |
1 |
|
|
T74 |
7 |
|
T41 |
7 |
|
T94 |
5 |
| auto[1] |
auto[0] |
61 |
1 |
|
|
T74 |
6 |
|
T41 |
7 |
|
T94 |
4 |
| auto[1] |
auto[1] |
67 |
1 |
|
|
T74 |
6 |
|
T41 |
2 |
|
T94 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
68 |
1 |
|
|
T74 |
5 |
|
T41 |
4 |
|
T94 |
3 |
| auto[0] |
auto[1] |
63 |
1 |
|
|
T74 |
6 |
|
T41 |
7 |
|
T94 |
3 |
| auto[1] |
auto[0] |
69 |
1 |
|
|
T74 |
7 |
|
T41 |
7 |
|
T94 |
6 |
| auto[1] |
auto[1] |
60 |
1 |
|
|
T74 |
2 |
|
T41 |
2 |
|
T94 |
8 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
73 |
1 |
|
|
T74 |
1 |
|
T41 |
7 |
|
T94 |
4 |
| auto[0] |
auto[1] |
55 |
1 |
|
|
T74 |
9 |
|
T41 |
1 |
|
T94 |
6 |
| auto[1] |
auto[0] |
66 |
1 |
|
|
T74 |
7 |
|
T41 |
8 |
|
T94 |
4 |
| auto[1] |
auto[1] |
66 |
1 |
|
|
T74 |
3 |
|
T41 |
4 |
|
T94 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
76 |
1 |
|
|
T74 |
3 |
|
T41 |
4 |
|
T94 |
6 |
| auto[0] |
auto[1] |
60 |
1 |
|
|
T74 |
7 |
|
T41 |
4 |
|
T94 |
6 |
| auto[1] |
auto[0] |
61 |
1 |
|
|
T74 |
9 |
|
T41 |
5 |
|
T94 |
4 |
| auto[1] |
auto[1] |
63 |
1 |
|
|
T74 |
1 |
|
T41 |
7 |
|
T94 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
68 |
1 |
|
|
T74 |
2 |
|
T41 |
4 |
|
T94 |
5 |
| auto[0] |
auto[1] |
58 |
1 |
|
|
T74 |
7 |
|
T41 |
8 |
|
T94 |
5 |
| auto[1] |
auto[0] |
75 |
1 |
|
|
T74 |
8 |
|
T41 |
3 |
|
T94 |
4 |
| auto[1] |
auto[1] |
59 |
1 |
|
|
T74 |
3 |
|
T41 |
5 |
|
T94 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
63 |
1 |
|
|
T74 |
3 |
|
T41 |
5 |
|
T94 |
4 |
| auto[0] |
auto[1] |
70 |
1 |
|
|
T74 |
8 |
|
T41 |
7 |
|
T94 |
4 |
| auto[1] |
auto[0] |
63 |
1 |
|
|
T74 |
7 |
|
T41 |
4 |
|
T94 |
5 |
| auto[1] |
auto[1] |
64 |
1 |
|
|
T74 |
2 |
|
T41 |
4 |
|
T94 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
62 |
1 |
|
|
T74 |
5 |
|
T41 |
5 |
|
T94 |
5 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T74 |
5 |
|
T41 |
6 |
|
T94 |
4 |
| auto[1] |
auto[0] |
70 |
1 |
|
|
T74 |
6 |
|
T41 |
4 |
|
T94 |
7 |
| auto[1] |
auto[1] |
63 |
1 |
|
|
T74 |
4 |
|
T41 |
5 |
|
T94 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
61 |
1 |
|
|
T74 |
6 |
|
T41 |
5 |
|
T94 |
5 |
| auto[0] |
auto[1] |
64 |
1 |
|
|
T74 |
4 |
|
T41 |
5 |
|
T94 |
5 |
| auto[1] |
auto[0] |
71 |
1 |
|
|
T74 |
7 |
|
T41 |
5 |
|
T94 |
6 |
| auto[1] |
auto[1] |
64 |
1 |
|
|
T74 |
3 |
|
T41 |
5 |
|
T94 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
67 |
1 |
|
|
T74 |
6 |
|
T41 |
5 |
|
T94 |
6 |
| auto[0] |
auto[1] |
58 |
1 |
|
|
T74 |
4 |
|
T41 |
2 |
|
T94 |
5 |
| auto[1] |
auto[0] |
67 |
1 |
|
|
T74 |
7 |
|
T41 |
7 |
|
T94 |
5 |
| auto[1] |
auto[1] |
68 |
1 |
|
|
T74 |
3 |
|
T41 |
6 |
|
T94 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
122 |
1 |
|
|
T74 |
13 |
|
T41 |
9 |
|
T94 |
7 |
| auto[1] |
auto[1] |
138 |
1 |
|
|
T74 |
7 |
|
T41 |
11 |
|
T94 |
13 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
61 |
1 |
|
|
T74 |
4 |
|
T41 |
8 |
|
T94 |
8 |
| auto[0] |
auto[1] |
69 |
1 |
|
|
T74 |
4 |
|
T41 |
5 |
|
T94 |
5 |
| auto[1] |
auto[0] |
65 |
1 |
|
|
T74 |
8 |
|
T41 |
5 |
|
T94 |
3 |
| auto[1] |
auto[1] |
65 |
1 |
|
|
T74 |
4 |
|
T41 |
2 |
|
T94 |
4 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
123 |
1 |
|
|
T74 |
12 |
|
T41 |
7 |
|
T94 |
13 |
| auto[1] |
auto[1] |
137 |
1 |
|
|
T74 |
8 |
|
T41 |
13 |
|
T94 |
7 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
40 |
1 |
|
|
T94 |
11 |
|
T158 |
9 |
|
T185 |
9 |
| auto[1] |
40 |
1 |
|
|
T94 |
9 |
|
T158 |
11 |
|
T185 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
33 |
1 |
|
|
T94 |
8 |
|
T158 |
8 |
|
T185 |
10 |
| auto[1] |
47 |
1 |
|
|
T94 |
12 |
|
T158 |
12 |
|
T185 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
41 |
1 |
|
|
T94 |
10 |
|
T158 |
12 |
|
T185 |
11 |
| auto[1] |
39 |
1 |
|
|
T94 |
10 |
|
T158 |
8 |
|
T185 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
42 |
1 |
|
|
T94 |
13 |
|
T158 |
11 |
|
T185 |
11 |
| auto[1] |
38 |
1 |
|
|
T94 |
7 |
|
T158 |
9 |
|
T185 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
39 |
1 |
|
|
T94 |
8 |
|
T158 |
10 |
|
T185 |
5 |
| auto[1] |
41 |
1 |
|
|
T94 |
12 |
|
T158 |
10 |
|
T185 |
15 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
47 |
1 |
|
|
T94 |
10 |
|
T158 |
10 |
|
T185 |
15 |
| auto[1] |
33 |
1 |
|
|
T94 |
10 |
|
T158 |
10 |
|
T185 |
5 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
43 |
1 |
|
|
T94 |
8 |
|
T158 |
16 |
|
T185 |
9 |
| auto[1] |
37 |
1 |
|
|
T94 |
12 |
|
T158 |
4 |
|
T185 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
35 |
1 |
|
|
T94 |
8 |
|
T158 |
6 |
|
T185 |
9 |
| auto[1] |
45 |
1 |
|
|
T94 |
12 |
|
T158 |
14 |
|
T185 |
11 |