Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2020

1

T1

2

T6

6

T7

12

auto[1]

671

1

T6

2

T37

8

T22

12

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2057

1

T6

2

T7

9

T37

10

auto[1]

634

1

T1

2

T6

6

T7

3

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2025

1

T6

8

T7

12

T37

16

auto[1]

666

1

T1

2

T21

1

T23

2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1996

1

T1

2

T6

6

T7

9

auto[1]

695

1

T6

2

T7

3

T37

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2413

1

T1

2

T6

8

T7

9

auto[1]

278

1

T7

3

T23

2

T24

8

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2473

1

T1

2

T6

8

T7

12

auto[1]

218

1

T23

2

T24

5

T25

1

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2487

1

T1

2

T6

4

T7

12

auto[1]

204

1

T6

4

T23

7

T98

22

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2479

1

T1

2

T6

4

T7

12

auto[1]

212

1

T6

4

T24

5

T25

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2446

1

T1

2

T6

8

T7

9

auto[1]

245

1

T7

3

T36

3

T24

13

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2133

1

T1

2

T6

6

T7

12

auto[1]

558

1

T6

2

T37

10

T21

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	*	[auto[1]]	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	882	1			T1	2		T37	8		T21	1
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	93	1			T59	1		T234	20		T151	22
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	55	1			T36	3		T59	1		T325	15
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	40	1			T7	3		T24	4		T234	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	95	1			T6	2		T24	3		T325	11
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	42	1			T98	14		T321	2		T324	4
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	37	1			T25	2		T339	2		T340	28
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	5	1			T64	1		T332	4		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	56	1			T6	2		T23	1		T98	8
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	31	1			T68	7		T330	6		T339	6
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	39	1			T98	4		T325	6		T321	3
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	6	1			T6	2		T252	1		T335	3
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	1	1			T233	1		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	3	1			T341	1		T342	2		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	117	1			T233	4		T325	9		T343	3
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	22	1			T23	1		T335	6		T344	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	21	1			T24	5		T345	1		T151	6
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	8	1			T346	2		T335	6		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	11	1			T25	1		T346	6		T341	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	1	1			T347	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	2	1			T321	1		T348	1		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	16	1			T233	1		T349	3		T335	5
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	7	1			T350	2		T351	2		T352	3
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	3	1			T353	2		T354	1		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	2	1			T355	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

116

1

T321

3

T323

12

T335

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

111

1

T23

1

T98

7

T233

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

57

1

T233

1

T349

3

T89

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

169

1

T234

2

T107

10

T322

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

85

1

T22

7

T233

4

T325

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

33

1

T356

5

T321

5

T88

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

20

1

T37

2

T26

4

T143

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

111

1

T24

7

T234

10

T321

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

82

1

T62

3

T25

1

T215

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

54

1

T23

1

T24

3

T98

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

37

1

T145

4

T325

11

T357

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

61

1

T59

1

T145

5

T325

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

37

1

T143

2

T356

2

T80

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

37

1

T357

2

T86

3

T337

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T237

2

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

128

1

T6

2

T24

2

T25

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

52

1

T6

2

T37

6

T80

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

17

1

T344

2

T358

2

T359

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

29

1

T98

8

T215

3

T143

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

86

1

T7

3

T36

3

T22

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

39

1

T22

5

T323

4

T253

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

16

1

T6

2

T341

2

T232

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

14

1

T323

2

T131

1

T86

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

62

1

T1

2

T59

1

T325

15

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

36

1

T62

3

T26

2

T360

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

35

1

T26

5

T101

1

T151

11

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

17

1

T80

1

T323

3

T338

11

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

39

1

T145

2

T242

2

T228

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T329

1

T361

2

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

8

1

T21

1

T145

2

T322

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T107

1

T334

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded