Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1004

1

T5

11

T2

15

T8

8

auto[1]

996

1

T5

9

T2

5

T8

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

456

1

T5

5

T2

6

T8

4

from_0to1

464

1

T5

6

T2

6

T8

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

999

1

T5

11

T2

12

T8

11

auto[1]

1001

1

T5

9

T2

8

T8

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

981

1

T5

11

T2

14

T8

10

auto[1]

1019

1

T5

9

T2

6

T8

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T5

1

T2

1

T9

2

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T9

3

T10

1

T12

3

auto[0]

from_1to0

auto[1]

auto[0]

47

1

T5

1

T2

2

T8

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T5

1

T2

1

T8

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T2

4

T8

1

T9

1

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T5

2

T2

1

T9

2

auto[0]

from_0to1

auto[1]

auto[0]

48

1

T5

2

T2

1

T9

2

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T9

1

T282

3

T255

1

auto[1]

from_1to0

auto[0]

auto[0]

53

1

T2

1

T8

1

T9

1

auto[1]

from_1to0

auto[0]

auto[1]

48

1

T9

3

T10

1

T32

1

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T8

1

T10

6

T12

2

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T5

2

T2

1

T9

2

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T5

1

T9

4

T10

4

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T5

1

T8

1

T9

4

auto[1]

from_0to1

auto[1]

auto[0]

52

1

T9

1

T10

2

T255

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T8

2

T9

4

T10

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

932

1

T5

9

T2

8

T8

9

auto[1]

1068

1

T5

11

T2

12

T8

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

480

1

T5

4

T2

7

T8

4

from_0to1

478

1

T5

5

T2

6

T8

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

979

1

T5

12

T2

11

T8

5

auto[1]

1021

1

T5

8

T2

9

T8

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1031

1

T5

7

T2

8

T8

14

auto[1]

969

1

T5

13

T2

12

T8

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T10

3

T12

1

T255

1

auto[0]

from_1to0

auto[0]

auto[1]

48

1

T2

1

T9

3

T10

2

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T5

1

T2

1

T9

1

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T5

2

T9

1

T10

2

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T5

1

T2

2

T8

1

auto[0]

from_0to1

auto[0]

auto[1]

53

1

T2

2

T9

2

T10

2

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T8

1

T9

2

T10

2

auto[0]

from_0to1

auto[1]

auto[1]

50

1

T5

1

T8

1

T9

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T9

7

T10

2

T12

2

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T2

1

T8

1

T9

3

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T2

2

T8

2

T9

3

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T5

1

T2

2

T8

1

auto[1]

from_0to1

auto[0]

auto[0]

55

1

T9

2

T10

6

T12

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T5

3

T2

2

T9

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T8

1

T9

4

T10

2

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T9

4

T10

3

T12

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1004

1

T5

11

T2

15

T8

9

auto[1]

996

1

T5

9

T2

5

T8

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

469

1

T5

3

T2

4

T8

3

from_0to1

466

1

T5

2

T2

5

T8

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1014

1

T5

16

T2

14

T8

8

auto[1]

986

1

T5

4

T2

6

T8

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1008

1

T5

11

T2

15

T8

10

auto[1]

992

1

T5

9

T2

5

T8

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T5

2

T2

2

T8

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T2

1

T9

1

T10

6

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T9

1

T282

1

T223

1

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T8

1

T9

1

T10

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T2

3

T9

3

T10

3

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T5

1

T8

1

T9

2

auto[0]

from_0to1

auto[1]

auto[0]

47

1

T9

5

T10

1

T12

1

auto[0]

from_0to1

auto[1]

auto[1]

49

1

T9

1

T10

3

T96

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T9

3

T10

3

T12

2

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T5

1

T9

3

T10

2

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T2

1

T8

1

T9

5

auto[1]

from_1to0

auto[1]

auto[1]

48

1

T9

4

T10

3

T255

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T5

1

T2

1

T8

1

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T9

2

T12

3

T223

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T2

1

T9

2

T10

3

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T8

2

T9

3

T10

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1020

1

T5

11

T2

7

T8

6

auto[1]

980

1

T5

9

T2

13

T8

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

489

1

T5

6

T2

4

T8

1

from_0to1

480

1

T5

6

T2

4

T8

1

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1022

1

T5

10

T2

6

T8

4

auto[1]

978

1

T5

10

T2

14

T8

16

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1001

1

T5

13

T2

8

T8

11

auto[1]

999

1

T5

7

T2

12

T8

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T5

2

T9

4

T10

4

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T9

2

T10

3

T282

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T5

1

T9

2

T10

3

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T8

1

T10

2

T12

3

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T5

2

T9

2

T10

6

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T9

3

T10

3

T12

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T5

2

T2

1

T9

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T8

1

T10

3

T12

2

auto[1]

from_1to0

auto[0]

auto[0]

51

1

T9

3

T10

3

T12

3

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T5

1

T2

1

T9

2

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T5

1

T2

1

T12

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T5

1

T2

2

T9

3

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T10

2

T12

2

T223

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T2

2

T9

7

T10

3

auto[1]

from_0to1

auto[1]

auto[0]

57

1

T9

1

T10

2

T12

2

auto[1]

from_0to1

auto[1]

auto[1]

50

1

T5

2

T2

1

T9

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1010

1

T5

6

T2

10

T8

13

auto[1]

990

1

T5

14

T2

10

T8

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

495

1

T5

4

T2

3

T8

6

from_0to1

508

1

T5

3

T2

4

T8

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1008

1

T5

8

T2

13

T8

11

auto[1]

992

1

T5

12

T2

7

T8

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

991

1

T5

7

T2

10

T8

9

auto[1]

1009

1

T5

13

T2

10

T8

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T8

2

T9

4

T10

3

auto[0]

from_1to0

auto[0]

auto[1]

51

1

T2

1

T9

3

T10

1

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T2

1

T8

1

T9

4

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T5

1

T8

1

T9

6

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T8

1

T9

5

T10

1

auto[0]

from_0to1

auto[0]

auto[1]

76

1

T8

3

T9

1

T10

1

auto[0]

from_0to1

auto[1]

auto[0]

45

1

T8

1

T9

2

T10

4

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T9

2

T10

5

T282

1

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T5

1

T2

1

T10

4

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T5

1

T8

1

T9

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T9

1

T10

1

T12

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T5

1

T8

1

T9

2

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T2

1

T9

2

T10

2

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T5

1

T2

2

T9

4

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T5

1

T2

1

T9

1

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T5

1

T8

1

T9

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1006

1

T5

11

T2

11

T8

9

auto[1]

994

1

T5

9

T2

9

T8

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

475

1

T5

3

T2

3

T8

3

from_0to1

472

1

T5

4

T2

3

T8

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1002

1

T5

12

T2

10

T8

9

auto[1]

998

1

T5

8

T2

10

T8

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

949

1

T5

8

T2

8

T8

9

auto[1]

1051

1

T5

12

T2

12

T8

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T2

1

T9

2

T12

2

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T5

1

T10

1

T12

2

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T9

2

T10

4

T282

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T5

1

T9

5

T10

4

auto[0]

from_0to1

auto[0]

auto[0]

44

1

T2

1

T8

1

T9

1

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T9

7

T10

1

T12

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T5

1

T8

1

T9

2

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T9

5

T10

1

T12

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T8

1

T9

3

T10

2

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T5

1

T2

2

T9

3

auto[1]

from_1to0

auto[1]

auto[0]

54

1

T8

1

T9

2

T10

2

auto[1]

from_1to0

auto[1]

auto[1]

49

1

T8

1

T9

4

T10

4

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T5

1

T2

1

T10

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T5

2

T2

1

T8

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T8

1

T9

3

T10

4

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T9

2

T10

6

T12

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

955

1

T5

14

T2

7

T8

12

auto[1]

1045

1

T5

6

T2

13

T8

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

478

1

T5

5

T2

6

T8

4

from_0to1

480

1

T5

4

T2

6

T8

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1024

1

T5

13

T2

7

T8

13

auto[1]

976

1

T5

7

T2

13

T8

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1007

1

T5

9

T2

12

T8

8

auto[1]

993

1

T5

11

T2

8

T8

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T5

1

T9

3

T282

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T5

1

T2

1

T8

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T5

1

T2

1

T9

5

auto[0]

from_1to0

auto[1]

auto[1]

52

1

T5

1

T8

1

T9

2

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T5

2

T9

4

T10

2

auto[0]

from_0to1

auto[0]

auto[1]

51

1

T2

1

T8

1

T9

2

auto[0]

from_0to1

auto[1]

auto[0]

51

1

T5

1

T2

1

T8

1

auto[0]

from_0to1

auto[1]

auto[1]

52

1

T10

4

T12

1

T96

1

auto[1]

from_1to0

auto[0]

auto[0]

54

1

T9

1

T10

5

T12

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T5

1

T2

1

T8

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T2

2

T8

1

T9

2

auto[1]

from_1to0

auto[1]

auto[1]

55

1

T2

1

T9

2

T10

3

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T5

1

T8

1

T9

3

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T8

1

T9

4

T10

1

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T2

3

T9

5

T10

2

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T2

1

T9

2

T10

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1019

1

T5

11

T2

14

T8

7

auto[1]

981

1

T5

9

T2

6

T8

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

485

1

T5

3

T2

4

T8

5

from_0to1

476

1

T5

2

T2

4

T8

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

989

1

T5

14

T2

10

T8

13

auto[1]

1011

1

T5

6

T2

10

T8

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1016

1

T5

9

T2

8

T8

8

auto[1]

984

1

T5

11

T2

12

T8

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T5

2

T8

1

T9

3

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T2

1

T9

1

T12

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T9

4

T10

4

T12

1

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T2

1

T8

1

T9

2

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T9

2

T10

1

T282

1

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T2

2

T8

1

T9

2

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T9

2

T10

4

T12

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T2

2

T8

1

T9

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T2

1

T8

1

T9

1

auto[1]

from_1to0

auto[0]

auto[1]

52

1

T5

1

T9

5

T10

1

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T8

1

T9

2

T10

3

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T2

1

T8

1

T9

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T5

1

T8

2

T9

3

auto[1]

from_0to1

auto[0]

auto[1]

44

1

T5

1

T8

1

T9

3

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T9

3

T10

4

T12

3

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T9

3

T10

3

T288

1