Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151270	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

116816

1

T1

254

T4

2

T5

34

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	136749	1			T1	363		T4	2		T5	62
values[0x0]	64958	1			T1	94		T5	29		T2	41
values[0x1]	66379	1			T1	114		T5	31		T2	49

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	122886	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145200

1

T1

315

T4

2

T5

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	852	1			T5	2		T6	6		T8	4
valid_sources[0x01]	941	1			T6	1		T7	1		T9	3
valid_sources[0x02]	909	1			T5	1		T6	3		T8	4
valid_sources[0x03]	718	1			T6	7		T7	1		T8	6
valid_sources[0x04]	902	1			T5	1		T6	4		T8	1
valid_sources[0x05]	1023	1			T6	3		T7	14		T9	5
valid_sources[0x06]	930	1			T5	1		T6	4		T7	8
valid_sources[0x07]	825	1			T6	3		T8	6		T45	1
valid_sources[0x08]	757	1			T5	3		T6	8		T8	16
valid_sources[0x09]	831	1			T6	5		T8	1		T10	4
valid_sources[0x0a]	825	1			T14	4		T45	1		T10	6
valid_sources[0x0b]	892	1			T6	5		T14	1		T9	3
valid_sources[0x0c]	853	1			T6	4		T7	10		T8	3
valid_sources[0x0d]	741	1			T5	1		T6	5		T7	3
valid_sources[0x0e]	954	1			T5	1		T6	5		T7	6
valid_sources[0x0f]	923	1			T5	2		T6	3		T7	4
valid_sources[0x10]	1483	1			T6	4		T7	3		T8	8
valid_sources[0x11]	1182	1			T5	1		T6	5		T7	10
valid_sources[0x12]	1327	1			T8	5		T18	2		T9	2
valid_sources[0x13]	774	1			T6	5		T8	2		T14	4
valid_sources[0x14]	1349	1			T7	3		T8	1		T9	2
valid_sources[0x15]	1203	1			T5	1		T6	8		T7	6
valid_sources[0x16]	767	1			T5	2		T6	6		T7	2
valid_sources[0x17]	1164	1			T5	1		T6	3		T7	2
valid_sources[0x18]	798	1			T5	1		T6	3		T7	6
valid_sources[0x19]	883	1			T6	3		T14	2		T9	4
valid_sources[0x1a]	883	1			T5	2		T7	3		T8	4
valid_sources[0x1b]	976	1			T6	3		T7	5		T8	2
valid_sources[0x1c]	955	1			T6	7		T9	4		T93	3
valid_sources[0x1d]	734	1			T6	1		T8	2		T47	1
valid_sources[0x1e]	2495	1			T6	1		T7	3		T46	2
valid_sources[0x1f]	1065	1			T6	3		T8	1		T46	1
valid_sources[0x20]	995	1			T6	4		T14	5		T9	3
valid_sources[0x21]	890	1			T6	2		T8	1		T9	1
valid_sources[0x22]	879	1			T6	5		T7	3		T8	4
valid_sources[0x23]	772	1			T6	6		T7	2		T8	6
valid_sources[0x24]	1103	1			T6	6		T8	3		T9	6
valid_sources[0x25]	738	1			T6	10		T9	6		T10	6
valid_sources[0x26]	989	1			T5	1		T6	1		T9	1
valid_sources[0x27]	869	1			T1	18		T5	1		T6	1
valid_sources[0x28]	2800	1			T5	1		T6	2		T10	3
valid_sources[0x29]	909	1			T5	1		T6	5		T7	15
valid_sources[0x2a]	913	1			T7	5		T9	1		T10	2
valid_sources[0x2b]	1013	1			T5	1		T6	4		T8	1
valid_sources[0x2c]	978	1			T6	3		T8	1		T9	5
valid_sources[0x2d]	856	1			T5	1		T6	5		T8	1
valid_sources[0x2e]	988	1			T5	1		T6	2		T46	2
valid_sources[0x2f]	1236	1			T5	1		T6	5		T8	1
valid_sources[0x30]	852	1			T5	1		T6	3		T7	9
valid_sources[0x31]	895	1			T6	5		T8	3		T9	2
valid_sources[0x32]	2082	1			T6	2		T9	5		T10	7
valid_sources[0x33]	1051	1			T6	3		T7	6		T8	2
valid_sources[0x34]	886	1			T5	1		T6	6		T7	2
valid_sources[0x35]	824	1			T5	2		T6	3		T9	6
valid_sources[0x36]	775	1			T6	2		T8	4		T9	7
valid_sources[0x37]	907	1			T6	3		T7	3		T8	2
valid_sources[0x38]	948	1			T6	6		T8	6		T9	1
valid_sources[0x39]	936	1			T5	3		T6	10		T7	5
valid_sources[0x3a]	887	1			T6	3		T8	3		T14	8
valid_sources[0x3b]	946	1			T6	4		T8	2		T14	5
valid_sources[0x3c]	846	1			T6	6		T7	5		T8	7
valid_sources[0x3d]	1124	1			T5	1		T2	187		T6	3
valid_sources[0x3e]	913	1			T6	4		T7	5		T8	1
valid_sources[0x3f]	1344	1			T6	8		T8	6		T10	4
valid_sources[0x40]	1486	1			T6	6		T10	6		T37	3
valid_sources[0x41]	901	1			T6	2		T7	4		T8	2
valid_sources[0x42]	1294	1			T5	1		T6	4		T8	4
valid_sources[0x43]	968	1			T5	1		T6	2		T9	2
valid_sources[0x44]	1062	1			T1	1		T5	1		T6	1
valid_sources[0x45]	976	1			T6	3		T7	11		T8	1
valid_sources[0x46]	1143	1			T1	208		T5	1		T6	2
valid_sources[0x47]	981	1			T5	1		T6	2		T7	5
valid_sources[0x48]	830	1			T6	5		T7	2		T9	9
valid_sources[0x49]	738	1			T6	5		T7	1		T8	3
valid_sources[0x4a]	798	1			T6	1		T8	3		T14	9
valid_sources[0x4b]	1688	1			T6	7		T7	16		T8	4
valid_sources[0x4c]	1693	1			T6	4		T8	3		T14	2
valid_sources[0x4d]	1788	1			T5	1		T6	6		T8	3
valid_sources[0x4e]	794	1			T6	5		T8	8		T9	2
valid_sources[0x4f]	1169	1			T5	1		T6	4		T8	2
valid_sources[0x50]	1684	1			T5	3		T6	3		T7	1
valid_sources[0x51]	1082	1			T6	6		T8	11		T9	1
valid_sources[0x52]	1749	1			T1	4		T6	1		T7	7
valid_sources[0x53]	854	1			T5	4		T6	2		T7	6
valid_sources[0x54]	1227	1			T5	1		T6	1		T9	1
valid_sources[0x55]	828	1			T5	1		T6	1		T9	2
valid_sources[0x56]	1050	1			T5	1		T6	4		T9	6
valid_sources[0x57]	957	1			T6	4		T14	6		T9	5
valid_sources[0x58]	819	1			T5	1		T6	6		T7	23
valid_sources[0x59]	903	1			T6	2		T7	3		T8	5
valid_sources[0x5a]	832	1			T6	3		T8	3		T14	5
valid_sources[0x5b]	952	1			T5	1		T6	5		T8	1
valid_sources[0x5c]	1518	1			T1	256		T6	2		T7	7
valid_sources[0x5d]	820	1			T6	6		T7	9		T8	11
valid_sources[0x5e]	892	1			T6	4		T7	3		T8	9
valid_sources[0x5f]	1540	1			T6	8		T9	11		T10	3
valid_sources[0x60]	994	1			T6	3		T8	3		T9	3
valid_sources[0x61]	1714	1			T6	2		T8	1		T9	1
valid_sources[0x62]	1773	1			T3	17		T6	5		T7	3
valid_sources[0x63]	998	1			T6	3		T7	3		T14	3
valid_sources[0x64]	1100	1			T5	1		T6	2		T7	3
valid_sources[0x65]	823	1			T6	3		T7	2		T14	5
valid_sources[0x66]	944	1			T6	3		T7	2		T8	5
valid_sources[0x67]	843	1			T6	4		T7	6		T10	3
valid_sources[0x68]	954	1			T5	1		T6	3		T7	13
valid_sources[0x69]	840	1			T1	3		T5	1		T6	1
valid_sources[0x6a]	892	1			T6	6		T14	2		T9	1
valid_sources[0x6b]	820	1			T6	3		T14	9		T9	4
valid_sources[0x6c]	835	1			T6	1		T8	1		T9	8
valid_sources[0x6d]	1184	1			T7	10		T8	4		T9	5
valid_sources[0x6e]	1800	1			T6	2		T8	2		T9	4
valid_sources[0x6f]	874	1			T6	3		T9	5		T10	7
valid_sources[0x70]	1068	1			T6	4		T7	14		T8	4
valid_sources[0x71]	1236	1			T5	1		T6	3		T7	2
valid_sources[0x72]	896	1			T5	1		T6	3		T7	2
valid_sources[0x73]	769	1			T7	2		T8	5		T14	6
valid_sources[0x74]	925	1			T5	1		T6	2		T7	5
valid_sources[0x75]	774	1			T5	1		T6	5		T7	5
valid_sources[0x76]	990	1			T6	1		T9	2		T10	3
valid_sources[0x77]	1817	1			T5	1		T6	6		T7	8
valid_sources[0x78]	1045	1			T6	2		T7	3		T8	5
valid_sources[0x79]	953	1			T7	5		T8	2		T9	3
valid_sources[0x7a]	1007	1			T6	3		T8	9		T14	4
valid_sources[0x7b]	898	1			T6	4		T7	14		T9	10
valid_sources[0x7c]	1241	1			T6	2		T8	2		T9	12
valid_sources[0x7d]	800	1			T5	2		T6	3		T14	3
valid_sources[0x7e]	1371	1			T5	2		T6	4		T8	2
valid_sources[0x7f]	2091	1			T6	4		T7	6		T8	3
valid_sources[0x80]	854	1			T5	1		T6	2		T8	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62307

1

T1

174

T4

2

T5

17

values[0x0]

all_enables

biggest_size

31590

1

T1

44

T5

11

T2

19

values[0x1]

all_enables

biggest_size

22919

1

T1

36

T5

6

T2

6