Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1096436920	11815	0	0
auto_block_debounce_ctl_rd_A	1096436920	1217	0	0
auto_block_out_ctl_rd_A	1096436920	1554	0	0
com_det_ctl_0_rd_A	1096436920	3264	0	0
com_det_ctl_1_rd_A	1096436920	3452	0	0
com_det_ctl_2_rd_A	1096436920	3325	0	0
com_det_ctl_3_rd_A	1096436920	3639	0	0
com_out_ctl_0_rd_A	1096436920	3626	0	0
com_out_ctl_1_rd_A	1096436920	3522	0	0
com_out_ctl_2_rd_A	1096436920	3792	0	0
com_out_ctl_3_rd_A	1096436920	3578	0	0
com_pre_det_ctl_0_rd_A	1096436920	1018	0	0
com_pre_det_ctl_1_rd_A	1096436920	1004	0	0
com_pre_det_ctl_2_rd_A	1096436920	1042	0	0
com_pre_det_ctl_3_rd_A	1096436920	1017	0	0
com_pre_sel_ctl_0_rd_A	1096436920	3557	0	0
com_pre_sel_ctl_1_rd_A	1096436920	3644	0	0
com_pre_sel_ctl_2_rd_A	1096436920	3653	0	0
com_pre_sel_ctl_3_rd_A	1096436920	3551	0	0
com_sel_ctl_0_rd_A	1096436920	3485	0	0
com_sel_ctl_1_rd_A	1096436920	3698	0	0
com_sel_ctl_2_rd_A	1096436920	3521	0	0
com_sel_ctl_3_rd_A	1096436920	3680	0	0
ec_rst_ctl_rd_A	1096436920	2071	0	0
intr_enable_rd_A	1096436920	1637	0	0
key_intr_ctl_rd_A	1096436920	1605	0	0
key_intr_debounce_ctl_rd_A	1096436920	1067	0	0
key_invert_ctl_rd_A	1096436920	3761	0	0
pin_allowed_ctl_rd_A	1096436920	3783	0	0
pin_out_ctl_rd_A	1096436920	3411	0	0
pin_out_value_rd_A	1096436920	3500	0	0
regwen_rd_A	1096436920	1037	0	0
ulp_ac_debounce_ctl_rd_A	1096436920	1143	0	0
ulp_ctl_rd_A	1096436920	1113	0	0
ulp_lid_debounce_ctl_rd_A	1096436920	1093	0	0
ulp_pwrb_debounce_ctl_rd_A	1096436920	1147	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	11815	0	0
T1	178153	9	0	0
T2	920758	0	0	0
T3	116209	0	0	0
T4	173039	0	0	0
T5	251031	0	0	0
T6	301413	0	0	0
T7	884146	0	0	0
T8	351609	16	0	0
T9	0	3	0	0
T10	0	5	0	0
T13	145401	0	0	0
T14	206139	0	0	0
T27	0	2	0	0
T32	0	9	0	0
T74	0	3	0	0
T75	0	4	0	0
T101	0	21	0	0
T163	0	7	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	1217	0	0
T10	274475	24	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T27	0	6	0	0
T37	270232	0	0	0
T38	0	13	0	0
T39	0	5	0	0
T43	0	10	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T77	0	1	0	0
T97	47164	0	0	0
T147	0	22	0	0
T193	0	9	0	0
T205	69394	0	0	0
T277	0	20	0	0
T278	0	2	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	1554	0	0
T9	216303	0	0	0
T10	274475	21	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T18	68722	13	0	0
T37	270232	0	0	0
T38	0	12	0	0
T39	0	6	0	0
T43	0	7	0	0
T47	24921	0	0	0
T52	44542	0	0	0
T57	332798	0	0	0
T77	0	14	0	0
T93	186139	0	0	0
T147	0	40	0	0
T193	0	6	0	0
T277	0	20	0	0
T278	0	14	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	3264	0	0
T10	274475	7	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T25	0	61	0	0
T26	0	57	0	0
T27	0	2	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T143	0	57	0	0
T145	0	41	0	0
T194	0	40	0	0
T205	69394	0	0	0
T215	0	80	0	0
T233	0	24	0	0
T234	0	63	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	3452	0	0
T10	274475	41	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T25	0	47	0	0
T26	0	52	0	0
T27	0	2	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T143	0	63	0	0
T145	0	33	0	0
T194	0	23	0	0
T205	69394	0	0	0
T215	0	71	0	0
T233	0	38	0	0
T234	0	69	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	3325	0	0
T10	274475	30	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T25	0	30	0	0
T26	0	67	0	0
T27	0	14	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T143	0	56	0	0
T145	0	38	0	0
T194	0	47	0	0
T205	69394	0	0	0
T215	0	59	0	0
T233	0	27	0	0
T234	0	68	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	3639	0	0
T10	274475	27	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T25	0	42	0	0
T26	0	116	0	0
T27	0	2	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T143	0	71	0	0
T145	0	48	0	0
T194	0	42	0	0
T205	69394	0	0	0
T215	0	80	0	0
T233	0	22	0	0
T234	0	65	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	3626	0	0
T10	274475	13	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T25	0	53	0	0
T26	0	73	0	0
T27	0	14	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T143	0	79	0	0
T145	0	46	0	0
T194	0	41	0	0
T205	69394	0	0	0
T215	0	69	0	0
T233	0	54	0	0
T234	0	95	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	3522	0	0
T10	274475	20	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T25	0	38	0	0
T26	0	65	0	0
T27	0	8	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T143	0	78	0	0
T145	0	34	0	0
T194	0	35	0	0
T205	69394	0	0	0
T215	0	59	0	0
T233	0	32	0	0
T234	0	82	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	3792	0	0
T10	274475	11	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T25	0	50	0	0
T26	0	59	0	0
T27	0	3	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T143	0	70	0	0
T145	0	49	0	0
T194	0	46	0	0
T205	69394	0	0	0
T215	0	82	0	0
T233	0	30	0	0
T234	0	65	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	3578	0	0
T10	274475	29	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T25	0	43	0	0
T26	0	61	0	0
T27	0	4	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T143	0	70	0	0
T145	0	24	0	0
T194	0	39	0	0
T205	69394	0	0	0
T215	0	74	0	0
T233	0	27	0	0
T234	0	62	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	1018	0	0
T10	274475	23	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T27	0	1	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T147	0	33	0	0
T162	0	3	0	0
T205	69394	0	0	0
T260	0	52	0	0
T264	0	23	0	0
T277	0	2	0	0
T279	0	10	0	0
T280	0	16	0	0
T281	0	10	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	1004	0	0
T10	274475	39	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T27	0	2	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T76	0	1	0	0
T97	47164	0	0	0
T147	0	27	0	0
T162	0	15	0	0
T205	69394	0	0	0
T239	0	18	0	0
T264	0	5	0	0
T277	0	1	0	0
T279	0	19	0	0
T280	0	29	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	1042	0	0
T10	274475	16	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T27	0	14	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T147	0	39	0	0
T162	0	5	0	0
T205	69394	0	0	0
T239	0	16	0	0
T260	0	17	0	0
T264	0	9	0	0
T277	0	7	0	0
T279	0	17	0	0
T280	0	24	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	1017	0	0
T10	274475	15	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T76	0	3	0	0
T97	47164	0	0	0
T147	0	23	0	0
T162	0	15	0	0
T205	69394	0	0	0
T239	0	17	0	0
T260	0	34	0	0
T264	0	10	0	0
T277	0	2	0	0
T279	0	16	0	0
T280	0	21	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	3557	0	0
T10	274475	26	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T25	0	38	0	0
T26	0	62	0	0
T27	0	3	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T143	0	77	0	0
T145	0	59	0	0
T194	0	25	0	0
T205	69394	0	0	0
T215	0	58	0	0
T233	0	47	0	0
T234	0	89	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	3644	0	0
T10	274475	28	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T25	0	54	0	0
T26	0	80	0	0
T27	0	9	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T143	0	69	0	0
T145	0	37	0	0
T194	0	44	0	0
T205	69394	0	0	0
T215	0	85	0	0
T233	0	35	0	0
T234	0	71	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	3653	0	0
T10	274475	17	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T25	0	38	0	0
T26	0	81	0	0
T27	0	2	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T143	0	74	0	0
T145	0	54	0	0
T194	0	51	0	0
T205	69394	0	0	0
T215	0	81	0	0
T233	0	54	0	0
T234	0	71	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	3551	0	0
T10	274475	36	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T25	0	37	0	0
T26	0	67	0	0
T27	0	8	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T143	0	78	0	0
T145	0	48	0	0
T194	0	46	0	0
T205	69394	0	0	0
T215	0	70	0	0
T233	0	23	0	0
T234	0	73	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	3485	0	0
T10	274475	23	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T25	0	44	0	0
T26	0	72	0	0
T27	0	5	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T143	0	73	0	0
T145	0	23	0	0
T194	0	33	0	0
T205	69394	0	0	0
T215	0	63	0	0
T233	0	37	0	0
T234	0	71	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	3698	0	0
T10	274475	32	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T25	0	54	0	0
T26	0	75	0	0
T27	0	10	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T143	0	50	0	0
T145	0	40	0	0
T194	0	48	0	0
T205	69394	0	0	0
T215	0	52	0	0
T233	0	39	0	0
T234	0	100	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	3521	0	0
T10	274475	18	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T25	0	55	0	0
T26	0	79	0	0
T27	0	4	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T143	0	77	0	0
T145	0	45	0	0
T194	0	49	0	0
T205	69394	0	0	0
T215	0	72	0	0
T233	0	48	0	0
T234	0	87	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	3680	0	0
T10	274475	22	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T25	0	40	0	0
T26	0	60	0	0
T27	0	4	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T143	0	80	0	0
T145	0	40	0	0
T194	0	39	0	0
T205	69394	0	0	0
T215	0	89	0	0
T233	0	24	0	0
T234	0	82	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	2071	0	0
T10	274475	18	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T25	0	21	0	0
T26	0	38	0	0
T27	0	13	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T193	0	2	0	0
T194	0	5	0	0
T205	69394	0	0	0
T215	0	37	0	0
T233	0	2	0	0
T234	0	42	0	0
T282	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	1637	0	0
T10	274475	41	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T27	0	25	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T76	0	1	0	0
T97	47164	0	0	0
T145	0	6	0	0
T147	0	44	0	0
T205	69394	0	0	0
T277	0	32	0	0
T279	0	55	0	0
T280	0	18	0	0
T282	0	45	0	0
T283	0	44	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	1605	0	0
T3	116209	5	0	0
T6	301413	0	0	0
T7	884146	0	0	0
T8	351609	0	0	0
T10	0	35	0	0
T13	145401	0	0	0
T14	206139	0	0	0
T18	68722	0	0	0
T27	0	2	0	0
T28	0	3	0	0
T33	0	9	0	0
T45	58843	0	0	0
T46	110355	0	0	0
T47	24921	0	0	0
T132	0	7	0	0
T133	0	5	0	0
T147	0	32	0	0
T148	0	8	0	0
T277	0	5	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	1067	0	0
T10	274475	30	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T27	0	3	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T76	0	5	0	0
T97	47164	0	0	0
T147	0	30	0	0
T162	0	13	0	0
T205	69394	0	0	0
T239	0	18	0	0
T264	0	11	0	0
T277	0	2	0	0
T279	0	26	0	0
T280	0	20	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	3761	0	0
T10	274475	97	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T27	0	91	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T106	0	56	0	0
T147	0	95	0	0
T148	0	77	0	0
T205	69394	0	0	0
T277	0	142	0	0
T284	0	91	0	0
T285	0	76	0	0
T286	0	50	0	0
T287	0	69	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	3783	0	0
T10	274475	360	0	0
T11	109210	0	0	0
T12	355802	69	0	0
T27	0	5	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T170	0	35	0	0
T193	0	58	0	0
T205	69394	0	0	0
T223	0	74	0	0
T282	0	65	0	0
T288	0	33	0	0
T289	0	56	0	0
T290	0	77	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	3411	0	0
T10	274475	267	0	0
T11	109210	0	0	0
T12	355802	83	0	0
T27	0	3	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T170	0	35	0	0
T193	0	46	0	0
T205	69394	0	0	0
T223	0	66	0	0
T282	0	50	0	0
T288	0	37	0	0
T289	0	60	0	0
T290	0	76	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	3500	0	0
T10	274475	290	0	0
T11	109210	0	0	0
T12	355802	62	0	0
T27	0	2	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T97	47164	0	0	0
T170	0	55	0	0
T193	0	34	0	0
T205	69394	0	0	0
T223	0	54	0	0
T282	0	69	0	0
T288	0	38	0	0
T289	0	61	0	0
T290	0	70	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	1037	0	0
T10	274475	33	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T27	0	5	0	0
T37	270232	0	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T76	0	1	0	0
T97	47164	0	0	0
T147	0	26	0	0
T162	0	7	0	0
T205	69394	0	0	0
T239	0	8	0	0
T264	0	13	0	0
T277	0	8	0	0
T279	0	5	0	0
T280	0	16	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	1143	0	0
T10	274475	29	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T27	0	15	0	0
T37	270232	0	0	0
T49	0	7	0	0
T51	0	3	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T70	0	7	0	0
T73	0	4	0	0
T97	47164	0	0	0
T147	0	52	0	0
T205	69394	0	0	0
T277	0	7	0	0
T291	0	8	0	0
T292	0	5	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	1113	0	0
T10	274475	19	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T27	0	3	0	0
T37	270232	0	0	0
T49	0	10	0	0
T51	0	4	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T70	0	9	0	0
T73	0	13	0	0
T97	47164	0	0	0
T147	0	32	0	0
T205	69394	0	0	0
T277	0	8	0	0
T291	0	3	0	0
T292	0	4	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	1093	0	0
T10	274475	25	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T27	0	13	0	0
T37	270232	0	0	0
T49	0	4	0	0
T51	0	12	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T70	0	9	0	0
T73	0	8	0	0
T97	47164	0	0	0
T147	0	36	0	0
T205	69394	0	0	0
T277	0	5	0	0
T291	0	3	0	0
T292	0	14	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096436920	1147	0	0
T10	274475	31	0	0
T11	109210	0	0	0
T12	355802	0	0	0
T27	0	4	0	0
T37	270232	0	0	0
T49	0	6	0	0
T51	0	3	0	0
T52	44542	0	0	0
T53	59347	0	0	0
T57	332798	0	0	0
T58	21593	0	0	0
T70	0	10	0	0
T73	0	11	0	0
T97	47164	0	0	0
T147	0	50	0	0
T205	69394	0	0	0
T277	0	7	0	0
T291	0	6	0	0
T292	0	12	0	0