Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1386

1

T2

4

T6

9

T9

13

auto[1]

1765

1

T2

8

T6

21

T9

23

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2620

1

T2

12

T6

20

T9

19

auto[1]

531

1

T6

10

T9

17

T22

15

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2988

1

T2

12

T6

20

T9

27

auto[1]

163

1

T6

10

T9

9

T22

11

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3015

1

T2

12

T6

30

T9

34

auto[1]

136

1

T9

2

T34

12

T35

3

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2978

1

T2

11

T6

30

T9

23

auto[1]

173

1

T2

1

T9

13

T22

3

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2008

1

T2

4

T6

30

T9

15

auto[1]

1143

1

T2

8

T9

21

T22

24

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1342

1

T2

2

T6

14

T9

9

auto[1]

1809

1

T2

10

T6

16

T9

27

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1284

1

T2

3

T6

7

T9

9

auto[1]

1867

1

T2

9

T6

23

T9

27

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1321

1

T2

10

T6

12

T9

9

auto[1]

1830

1

T2

2

T6

18

T9

27

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1381

1

T2

2

T6

11

T9

10

auto[1]

1770

1

T2

10

T6

19

T9

26

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

62

1

T41

2

T42

2

T46

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

13

1

T34

1

T97

1

T347

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T22

2

T76

1

T96

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T162

2

T179

1

T264

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

53

1

T2

1

T6

1

T46

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

14

1

T279

2

T101

1

T347

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

40

1

T46

1

T112

2

T263

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T9

1

T279

2

T292

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

60

1

T2

1

T41

1

T46

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

16

1

T34

2

T279

1

T101

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

49

1

T6

1

T263

1

T76

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

23

1

T279

1

T347

1

T278

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

43

1

T112

1

T263

2

T143

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T347

1

T348

1

T349

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

52

1

T112

1

T43

1

T143

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

17

1

T22

1

T279

1

T347

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

63

1

T41

5

T42

1

T49

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

23

1

T22

1

T278

1

T179

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

41

1

T46

1

T43

1

T143

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T101

1

T347

2

T179

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

29

1

T46

1

T112

1

T143

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T22

1

T34

1

T97

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

39

1

T6

1

T46

2

T96

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T22

1

T279

1

T100

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

56

1

T6

2

T41

2

T112

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

13

1

T34

2

T101

1

T278

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

56

1

T6

1

T112

1

T143

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

20

1

T34

1

T128

1

T101

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

39

1

T46

1

T112

1

T43

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

33

1

T22

1

T128

1

T254

9

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

80

1

T112

2

T43

7

T128

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

49

1

T257

5

T279

1

T101

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

43

1

T42

1

T112

1

T43

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

15

1

T22

1

T279

1

T278

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T46

1

T112

2

T263

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

11

1

T97

1

T347

1

T278

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

46

1

T28

1

T43

1

T96

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T9

1

T22

1

T278

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

39

1

T6

1

T263

2

T258

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T278

1

T162

1

T179

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

54

1

T41

1

T112

1

T263

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

10

1

T128

2

T179

1

T350

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

59

1

T112

1

T35

10

T97

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

24

1

T128

1

T126

3

T100

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

41

1

T2

1

T44

1

T76

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

36

1

T97

1

T257

3

T347

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

57

1

T263

2

T143

1

T258

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

35

1

T9

1

T22

1

T128

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

58

1

T2

1

T41

2

T42

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

26

1

T42

7

T128

1

T97

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T263

1

T256

1

T278

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T22

1

T128

1

T97

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

42

1

T6

1

T112

2

T263

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T128

1

T97

2

T257

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

72

1

T6

1

T28

9

T112

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

51

1

T2

8

T97

1

T256

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

68

1

T41

8

T112

1

T263

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

23

1

T22

1

T34

1

T350

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

65

1

T34

1

T263

1

T126

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T9

1

T76

2

T97

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

69

1

T9

1

T263

1

T99

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

49

1

T44

9

T76

3

T256

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

271

1

T6

11

T9

14

T22

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T279

1

T347

1

T278

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

11

1

T9

1

T22

1

T34

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T9

1

T162

1

T281

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T128

2

T278

1

T266

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T34

1

T128

1

T97

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

11

1

T9

1

T22

1

T162

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T97

1

T350

1

T267

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T9

1

T34

1

T279

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

12

1

T34

1

T128

1

T279

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T9

1

T22

1

T97

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T279

1

T351

1

T350

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

11

1

T128

1

T162

1

T170

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

11

1

T97

1

T101

1

T351

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6

1

T9

1

T350

1

T266

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T128

1

T279

1

T101

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T9

1

T170

1

T352

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

10

1

T9

1

T22

1

T278

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

12

1

T34

1

T128

1

T101

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T9

1

T97

1

T179

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T9

1

T34

1

T97

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T128

1

T347

1

T275

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

8

1

T34

1

T179

1

T267

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T22

1

T350

2

T266

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

15

1

T101

1

T347

2

T182

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T34

1

T347

1

T281

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T9

2

T179

1

T292

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T22

1

T278

1

T179

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

10

1

T351

1

T350

1

T348

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

14

1

T128

1

T97

1

T256

5

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T9

1

T22

2

T34

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8

1

T128

1

T126

1

T279

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12

1

T9

1

T179

1

T170

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

127

1

T9

3

T22

6

T34

4

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	31	65	67.71	31
Automatically Generated Cross Bins	96	31	65	67.71	31
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	*	[auto[1]]	--	--	16
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

69

1

T6

2

T41

2

T42

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T9

1

T22

1

T34

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

56

1

T6

1

T22

2

T46

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T9

1

T162

3

T179

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

54

1

T2

1

T6

1

T46

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T128

2

T279

2

T101

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

44

1

T46

2

T112

2

T263

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

26

1

T9

1

T34

1

T128

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

64

1

T2

1

T41

1

T46

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T9

1

T22

1

T34

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

50

1

T6

1

T263

1

T76

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

33

1

T97

1

T279

1

T347

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T6

1

T112

1

T263

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

18

1

T9

1

T34

1

T279

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

55

1

T112

1

T43

1

T143

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

29

1

T22

1

T34

1

T128

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

66

1

T41

5

T22

1

T42

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

30

1

T9

1

T22

2

T97

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T6

1

T46

1

T43

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T279

1

T101

1

T347

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

32

1

T46

1

T112

1

T143

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

33

1

T22

1

T34

1

T128

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T6

2

T46

3

T96

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

38

1

T22

1

T97

1

T279

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

60

1

T6

3

T41

2

T112

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T9

1

T34

2

T101

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

60

1

T6

2

T112

1

T143

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

27

1

T34

1

T128

2

T279

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

43

1

T46

1

T112

1

T43

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

37

1

T9

1

T22

1

T128

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

85

1

T112

2

T43

7

T128

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

59

1

T9

1

T22

1

T257

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

46

1

T42

1

T112

1

T43

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

27

1

T22

1

T34

1

T128

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

49

1

T46

1

T112

2

T263

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T9

1

T97

2

T347

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T28

1

T43

1

T96

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T9

2

T22

1

T34

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

40

1

T6

1

T263

2

T258

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

34

1

T128

1

T347

1

T278

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

54

1

T41

1

T112

1

T263

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T34

1

T128

2

T179

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

62

1

T46

1

T112

1

T35

10

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

29

1

T22

1

T128

1

T126

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

39

1

T2

1

T44

1

T76

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

51

1

T97

1

T257

3

T101

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

59

1

T263

2

T143

1

T258

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

41

1

T9

1

T22

1

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

63

1

T2

1

T41

2

T42

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

33

1

T9

2

T42

7

T128

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

54

1

T6

1

T46

1

T263

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

33

1

T22

2

T128

1

T97

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

42

1

T6

2

T112

2

T263

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

33

1

T128

1

T97

2

T257

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

74

1

T6

1

T28

9

T112

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

65

1

T2

8

T128

1

T97

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

63

1

T41

8

T112

1

T263

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

42

1

T9

1

T22

3

T34

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

66

1

T34

1

T263

1

T99

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

33

1

T9

1

T128

1

T76

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

69

1

T9

1

T263

1

T99

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

61

1

T9

1

T44

9

T76

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

167

1

T6

1

T9

6

T46

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

110

1

T9

2

T22

1

T34

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

28

1

T9

1

T22

5

T128

4

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	29	67	69.79	29
Automatically Generated Cross Bins	96	29	67	69.79	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[0]]	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

69

1

T6

2

T41

2

T42

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T9

1

T22

1

T34

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

56

1

T6

1

T22

2

T46

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T9

1

T162

3

T179

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

54

1

T2

1

T6

1

T46

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T128

2

T279

2

T101

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

44

1

T46

2

T112

2

T263

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

26

1

T9

1

T34

1

T128

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

63

1

T2

1

T41

1

T46

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T9

1

T22

1

T34

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

47

1

T6

1

T263

1

T76

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

33

1

T97

1

T279

1

T347

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T6

1

T112

1

T263

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

18

1

T9

1

T34

1

T279

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

46

1

T112

1

T43

1

T143

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

29

1

T22

1

T34

1

T128

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

66

1

T41

5

T22

1

T42

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

30

1

T9

1

T22

2

T97

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T6

1

T46

1

T43

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T279

1

T101

1

T347

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

33

1

T46

1

T112

1

T143

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

33

1

T22

1

T34

1

T128

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T6

2

T46

3

T96

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

38

1

T22

1

T97

1

T279

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

60

1

T6

3

T41

2

T112

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T9

1

T34

2

T101

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

60

1

T6

2

T112

1

T143

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T34

1

T128

2

T279

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

42

1

T46

1

T112

1

T43

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

37

1

T9

1

T22

1

T128

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

82

1

T112

2

T43

7

T128

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

56

1

T9

1

T22

1

T257

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

46

1

T42

1

T112

1

T43

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

27

1

T22

1

T34

1

T128

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T46

1

T112

2

T263

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T9

1

T97

2

T347

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T28

1

T43

1

T96

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T9

2

T22

1

T34

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

39

1

T6

1

T263

2

T258

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

34

1

T128

1

T347

1

T278

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

55

1

T41

1

T112

1

T263

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T34

1

T128

2

T179

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

55

1

T46

1

T112

1

T35

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

29

1

T22

1

T128

1

T126

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

42

1

T2

1

T44

1

T76

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

51

1

T97

1

T257

3

T101

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

58

1

T263

2

T143

1

T258

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

41

1

T9

1

T22

1

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

68

1

T2

1

T41

2

T42

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

33

1

T9

2

T42

7

T128

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

52

1

T6

1

T46

1

T263

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

33

1

T22

2

T128

1

T97

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

46

1

T6

2

T112

2

T263

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

33

1

T128

1

T97

2

T257

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

72

1

T6

1

T28

9

T112

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

65

1

T2

8

T128

1

T97

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

71

1

T41

8

T112

1

T263

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

42

1

T9

1

T22

3

T34

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

67

1

T34

1

T263

1

T126

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

33

1

T9

1

T128

1

T76

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

66

1

T9

1

T263

1

T99

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

61

1

T9

1

T44

9

T76

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

209

1

T6

11

T9

13

T22

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

112

1

T9

2

T22

6

T34

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T353

2

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T83

3

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

26

1

T9

1

T34

2

T279

3

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	28	68	70.83	28
Automatically Generated Cross Bins	96	28	68	70.83	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo3

Element holes

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo3_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

69

1

T6

2

T41

2

T42

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T9

1

T22

1

T34

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

56

1

T6

1

T22

2

T46

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T9

1

T162

3

T179

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

54

1

T2

1

T6

1

T46

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T128

2

T279

2

T101

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

44

1

T46

2

T112

2

T263

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

26

1

T9

1

T34

1

T128

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

63

1

T2

1

T41

1

T46

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T9

1

T22

1

T34

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

50

1

T6

1

T263

1

T76

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

33

1

T97

1

T279

1

T347

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T6

1

T112

1

T263

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

18

1

T9

1

T34

1

T279

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

55

1

T112

1

T43

1

T143

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

29

1

T22

1

T34

1

T128

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

66

1

T41

5

T22

1

T42

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

30

1

T9

1

T22

2

T97

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T6

1

T46

1

T43

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T279

1

T101

1

T347

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

33

1

T46

1

T112

1

T143

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

31

1

T22

1

T34

1

T128

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T6

2

T46

3

T96

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

38

1

T22

1

T97

1

T279

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

60

1

T6

3

T41

2

T112

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T9

1

T34

2

T101

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

60

1

T6

2

T112

1

T143

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

27

1

T34

1

T128

2

T279

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

41

1

T46

1

T112

1

T43

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

37

1

T9

1

T22

1

T128

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

82

1

T112

2

T43

7

T128

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

59

1

T9

1

T22

1

T257

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

45

1

T42

1

T112

1

T43

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

27

1

T22

1

T34

1

T128

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

48

1

T46

1

T112

2

T263

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T9

1

T97

2

T347

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T28

1

T43

1

T96

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T9

2

T22

1

T34

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

40

1

T6

1

T263

2

T258

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

34

1

T128

1

T347

1

T278

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

55

1

T41

1

T112

1

T263

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T34

1

T128

2

T179

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

60

1

T46

1

T112

1

T35

10

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

29

1

T22

1

T128

1

T126

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

41

1

T44

1

T76

1

T143

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

51

1

T97

1

T257

3

T101

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

59

1

T263

2

T143

1

T258

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

41

1

T9

1

T22

1

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

68

1

T2

1

T41

2

T42

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

33

1

T9

2

T42

7

T128

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

54

1

T6

1

T46

1

T263

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

33

1

T22

2

T128

1

T97

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

46

1

T6

2

T112

2

T263

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

33

1

T128

1

T97

2

T257

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

70

1

T6

1

T28

9

T112

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

65

1

T2

8

T128

1

T97

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

70

1

T41

8

T112

1

T263

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

42

1

T9

1

T22

3

T34

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

58

1

T34

1

T263

1

T126

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

33

1

T9

1

T128

1

T76

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

73

1

T9

1

T263

1

T99

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

61

1

T9

1

T44

9

T76

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

157

1

T6

11

T9

3

T22

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

115

1

T9

1

T22

3

T34

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

2

1

T354

2

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T354

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

2

1

T355

2

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

23

1

T9

2

T22

3

T347

1

User Defined Cross Bins for cross_combo3

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded