dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key2_inXval

Bins
cp_key2_incfg.vif.key2_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 59 1 T38 3 T36 8 T310 6
auto[0] auto[1] 54 1 T38 5 T36 3 T310 6
auto[1] auto[0] 70 1 T38 6 T36 5 T310 3
auto[1] auto[1] 57 1 T38 6 T36 4 T310 5


Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key2_outXval

Bins
cp_key2_outcfg.vif.key2_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 64 1 T38 4 T36 5 T310 7
auto[0] auto[1] 50 1 T38 4 T36 5 T310 4
auto[1] auto[0] 74 1 T38 7 T36 3 T310 5
auto[1] auto[1] 52 1 T38 5 T36 7 T310 4


Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for pwrb_inXval

Bins
cp_pwrb_incfg.vif.pwrb_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 70 1 T38 6 T36 9 T310 5
auto[0] auto[1] 51 1 T38 5 T36 3 T310 5
auto[1] auto[0] 61 1 T38 6 T36 3 T310 4
auto[1] auto[1] 58 1 T38 3 T36 5 T310 6


Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for pwrb_outXval

Bins
cp_pwrb_outcfg.vif.pwrb_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 54 1 T38 2 T36 7 T310 7
auto[0] auto[1] 54 1 T38 3 T36 2 T310 4
auto[1] auto[0] 58 1 T38 8 T36 4 T310 5
auto[1] auto[1] 74 1 T38 7 T36 7 T310 4


Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for ac_presentXval

Bins
cp_ac_presentcfg.vif.ac_presentCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 63 1 T38 3 T36 4 T310 5
auto[0] auto[1] 63 1 T38 10 T36 6 T310 8
auto[1] auto[0] 56 1 T38 3 T36 3 T310 5
auto[1] auto[1] 58 1 T38 4 T36 7 T310 2


Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for bat_disableXval

Bins
cp_bat_disablecfg.vif.bat_disableCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 131 1 T38 13 T36 12 T310 10
auto[1] auto[1] 109 1 T38 7 T36 8 T310 10


User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded


Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for lid_openXval

Bins
cp_lid_opencfg.vif.lid_openCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 63 1 T38 3 T36 3 T310 6
auto[0] auto[1] 49 1 T38 4 T36 5 T310 5
auto[1] auto[0] 61 1 T38 4 T36 7 T310 5
auto[1] auto[1] 67 1 T38 9 T36 5 T310 4


Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for z3_wakeupXval

Bins
cp_z3_wakeupcfg.vif.z3_wakeupCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 132 1 T38 10 T36 10 T310 11
auto[1] auto[1] 108 1 T38 10 T36 10 T310 9


User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%